PSoC 4100/4200 Hardware Design Considerations
AN88619PSoC 4100/4200 Hardware Design ConsiderationsAuthor: Johnny ZhangAssociated Project: NoAssociated Part Family: PSoC 4100/4200Software Version: PSoC Creator 3.1 and higherRelated Documentation: For a complete list, click here.To get the latest version of this application note, or the associated project file, please visithttp://www.cypress.com/go/AN88619.AN88619 shows you how to design a hardware system around a PSoC 4100/4200 device. Subjects include packageselection, power, clocking, reset, I/O usage, programming and debugging interfaces, and analog module design tips.Also included are instructions on how to use PSoC Creator to configure the device for the hardware environment.ContentsIntroductionIntroduction . 1Differences between PSoC 4100 and PSoC 4200 . 2Package Selection . 2Power . 2Power Pin Connections . 3Power Ramp-Up Considerations . 4PSoC Creator Settings for Device Power . 4Thermal Considerations . 4Clocking . 5Reset . 6Programming and Debugging . 6GPIO Pins . 7I/O Pin Selection . 7Port 4 GPIO Pins . 10Component Placement . 12Analog Module Design Tips . 13SAR ADC . 13Opamps . 16Comparators . 17CapSense. 17Current DACs . 18Summary . 19Related Documents . 20Appendix A: PCB Layout Tips . 21Appendix B: Schematic Checklist . 22Worldwide Sales and Design Support . 24PSoC 4 is a powerful, programmable microcontroller withan ARM Cortex -M0 CPU. It provides capability andflexibility for analog and digital applications beyond that oftraditional MCUs.www.cypress.comPSoC 4100 and PSoC 4200 are two families of PSoC 4that have balanced analog and digital performance. ThisapplicationnotedocumentsconsiderationsforPSoC 4100/4200 hardware design, including package,power, clocking, reset, I/O usage, programming,debugging, and design tips for analog modules. Inaddition, it discusses good board layout techniques, whichare particularly important for precision analog applications.The PSoC 4100/4200 device must be configured to workin its hardware environment, which is accomplishedthrough the use of PSoC Creator.This application note assumes that you have some basicfamiliarity with PSoC 4 devices and the PSoC Creatorintegrated design environment (IDE). If you are new toPSoC 4, refer to AN79953 – Getting Started with PSoC 4.If you are new to PSoC Creator, see the PSoC Creatorhome page.Document No. 001-88619 Rev. *B1
PSoC 4100/4200 Hardware Design ConsiderationsDifferences between PSoC 4100 and PSoC 4200PSoC 4100 and PSoC 4200 are two similar families in PSoC 4. There are only a few slight differences between them, as listedin Table 1.Table 1. Differences between PSoC 4100 and PSoC 4200FeaturePSoC 4100PSoC 4200Maximum CPU Speed (MHz)2448Universal Digital Block (UDB) SupportNoYesMaximum SAR ADC Sample Rate (ksps)8061000Package SelectionOne of the first decisions you must make for your PCB is which package you will use. Several considerations drive thisdecision, including the number of PSoC device pins required, PCB and product size, PCB design rules, and thermal andmechanical stresses. PSoC 4100/4200 devices are available in four packages: 48-TQFP, 44-TQFP, 40-QFN, and 28-SSOP.Following are some package selection criteria: 48-TQFP: This package provides 36 I/O pins. It is easy to route signals due to a large pitch and the open area below thepart. Disadvantages are a larger package and lower mechanical stability. 44-TQFP: This package provides the same number of I/O pins as 48-TQFP, but it provides a larger pin width and pin pitchthan 48-TQFP, which facilitates manufacturing. 40-QFN: This package provides 34 I/O pins. It is much smaller than the other two packages. The central exposure padgives the package the best heat dispersion performance and mechanical stability. Disadvantages are that it is moredifficult to route signals due to the center pad. For more information, see AN72845 – Design Guidelines for QFNPackaged Devices. 28-SSOP: This package provides 24 I/O pins and has the same advantages and disadvantages as the 44-TQFP package.As a design reference, see the knowledge base article KBA89265, which contains PSoC 4100/4200 schematics and PCBlibraries. Please note that you may need to adjust or modify the libraries slightly when you apply them in your hardware design.Cypress takes no responsibility for issues related to use of the libraries.PowerPSoC 4100/4200 can be powered by a single supply with a wide voltage range, from 1.71 V to 5.5 V. As listed in Table 2, ithas separate power domains for analog and digital modules. VDDA is the analog power supply pin, VSSA is the analog groundpin, VDDD and VCCD are the digital power supply pins, and VSS is the digital ground pin.Table 2. PSoC 4100/4200 Power DomainsPower DomainAssociated PinsAnalogVDDA, VSSADigitalVDDD, VCCD, VSSNote In the 28-SSOP package, VDDA and VDDD are combined into a single VDDD pin, and VSSA and VSS are combined into asingle VSS pin.www.cypress.comDocument No. 001-88619 Rev. *B2
PSoC 4100/4200 Hardware Design ConsiderationsPower Pin ConnectionsPSoC 4100/4200 devices can be powered in regulated mode or unregulated mode. Power pin connections for these twomodes are illustrated in Figure 1 and Figure 2. In regulated mode, the internal regulators convert VDDD input to the powersupply for the digital domain. Voltages at the VDDD pins can be from 1.8 V to 5.5 V. Outputs of the regulators are also routed toVCCD. Do not connect any external load to VCCD except a capacitor, as Figure 1 shows.Figure 1. PSoC 4100/4200 Single Power Supply Rail for Analog and Digital: Regulated Mode1.8 V – 5.5 VVDDD1 μF0.1 μFRegulatorsDigitalModulesVCCD1 μFVSSVSSAVDDA1 μFAnalogModules0.1 μFYou can also power PSoC 4100/4200 in unregulated mode, as Figure 2 shows. The VCCD pin is directly powered. Its powermust be kept within 1.71 V to 1.89 V. The VDDD pins must be tied to the VCCD pin. The unused regulators can be disabled bysetting the EXT VCCD bit in the PWR CONTROL register to reduce power consumption. For more information, refer to thePSoC 4100/4200 device datasheets, Architecture Technical Reference Manual (TRM), and Registers TRM.Figure 2. PSoC 4100/4200 Single Power Supply Rail for Analog and Digital: Unregulated Mode1.71 V – 1.89 V1 μFVDDD0.1 μFRegulatorsDigitalModulesVCCDVSS1 μF0.1 μFVSSAVDDA1 μFAnalogModules0.1 μFIn both modes, to suppress power supply noise, connect one 0.1-μF and one 1-μF ceramic decoupling capacitor to eachpower supply pin. The PCB trace between the pin and the capacitors should be as short as possible. For more information,see Appendix A: PCB Layout Tips.Note It is a good practice to check the datasheets of your bypass capacitors, specifically the working voltage and the DC biasspecifications. With some capacitors, the actual capacitance can decrease considerably when the DC bias (VDDD, VDDA, orVCCD in Figure 1 and Figure 2) is a significant percentage of the rated working voltage.www.cypress.comDocument No. 001-88619 Rev. *B3
PSoC 4100/4200 Hardware Design ConsiderationsYou can use a single power supply rail for digital power and analog power, which helps to simplify the power design in yourboard. To get better analog performance in a mixed signal circuit design, use separate power supply rails for the digital powerand the analog power. In this case, the voltage at the VDDA pin must always be greater than or equal to the voltage at the VDDDpins. For more mixed signal circuit design techniques, see AN57821 – PSoC Mixed Signal Circuit Board LayoutConsiderationsProper use and layout of capacitors, ferrite beads, and transient voltage suppressor (TVS) diodes help to improve EMCperformance. For more information, see AN80994 – PSoC 3, PSoC 4, and PSoC 5LP EMC Best Practices andRecommendations.The Cypress PSoC 4 kits (CY8CKIT-038 and CY8CKIT-042) include schematics and bills of material (BOMs) that providegood examples of how to incorporate PSoC 4100/4200 into board schematics. For more information, see Related Documents.Power Ramp-Up ConsiderationsAs mentioned previously, if you use separate power rails for the analog and digital power domains, the voltage at the VDDA pinmust always be greater than or equal to the voltage at the VDDD pin. When PSoC 4100/4200 is powered up, the voltage at theVDDA pin must be present prior to or concurrent with the voltage at the VDDD pin. The maximum allowed voltage ramp rate forany power pin is 67 mV/µs.PSoC Creator Settings for Device PowerPSoC Creator automatically configures Components for optimal performance for the voltages applied to the power pins. To doso, it needs to know the value of these voltages. The System tab in the PSoC Creator project's Design-Wide Resources(DWR) window is used for this purpose. To open the DWR window, double-click the .cydw” file in the project navigator, asFigure 3 shows.Figure 3. Device Power Settings in PSoC CreatorVariable VDDA provides a feature that helps the PSoC internal analog routing switch operations by charging pumps when thePSoC analog power supply is low. It is enabled by default when the configured VDDA is lower than or equal to 4.0 V. You candisable it to save power when VDDA exceeds 4.0 V. Refer to the PSoC Creator System Reference Guide for more information.Thermal ConsiderationsThermal considerations are important in the hardware design, such as package selection and PCB layout. PSoC 4100/4200targets low-power applications, as it consumes no more than 0.2 W. The maximum power consumption is low enough thatthermal considerations are unlikely.www.cypress.comDocument No. 001-88619 Rev. *B4
PSoC 4100/4200 Hardware Design ConsiderationsClockingPSoC 4100/4200 has two oscillators: an internal main oscillator (IMO), which drives the high-frequency clock (HFCLK), and aninternal low-speed oscillator (ILO), which drives the low-frequency clock (LFCLK).The IMO is rated at 2 percent accuracy. If you need better accuracy, you can bring in a precision clock via pin P0[6] to drivethe HFCLK. The external clock’s frequency can be up to 48 MHz. Its duty cycle must be from 45 percent to 55 percent; asquare-wave clock is recommended. PSoC 4100/4200 does not support an external crystal connection.To use the external clock, you must configure system clocks to enable external clock input (EXTCLK), enter the external clockfrequency, and select it as HFCLK’s source in the Clocks tab in the DWR window. Double-click any row in the table of clocksto open the Configure System Clocks dialog, as Figure 4 shows.Figure 4. Clock Settings in PSoC Creator IDEUsing HFCLK as the source, internal prescalers and dividers generate clocks for the ARM Cortex-M0 core, analog modules,and digital modules. LFCLK is directly used to drive the watchdog timer (WDT). If necessary, you can output LFCLK andSYSCLK (see Figure 4) via the PSoC 4100/4200 I/O pins (except Port 4).Besides the external clock setting, PSoC 4100/4200 also provides flexible internal clocking routing solutions. You can use upto four digital signals in PSoC 4100/4200 as the routed clock for internal digital logic, which are generally implemented withUDB resources. Select Topics in the PSoC Creator Help menu and search “Configure System Clocks” to get more information.www.cypress.comDocument No. 001-88619 Rev. *B5
PSoC 4100/4200 Hardware Design ConsiderationsResetPSoC 4100/4200 has a reset pin, XRES, which is active LOW. XRES is internally pulled up to VDDD via a 5.6-kΩ resistor; youdo not need an external pull-up resistor for XRES.You can connect a capacitor to the XRES pin, as Figure 5 shows, to filter out glitches and give the reset signal better noiseimmunity. A typical capacitance is 0.1 μF.Figure 5. XRES Pin ConnectionPSoC 4100/4200VDDDDigital Power 5.6 kΩXRES0.1 µFProgramming and DebuggingPSoC 4100/4200 supports serial wire debug (SWD) interfaces for device programming and debugging. For programming ordebugging, you can connect PSoC 4100/4200 to a CY8CKIT-002 MiniProg3 via a 10-pin or 5-pin connector (pin maps areshown in Figure 6). For a 10-pin connector, Samtec FTSH-105-01-L-DV-K (surface mount) or FTSH-105-01-L-D-K (throughhole) is recommended. For a 5-pin connector, Molex 22-23-2051 is recommended. Similar parts are available from othervendors.Figure 6. SWD Connectors Pin Maps for MiniProg31Vtarget DCLK49GndXRESSWDIO510Figure 7 shows the SWD connections.www.cypress.comDocument No. 001-88619 Rev. *B6
PSoC 4100/4200 Hardware Design ConsiderationsFigure 7. SWD Connections to PSoC 4100/4200PSoC 4100/4200SWDIOP3[2] SWDIOSWDCLKP3[3] SWDCLKXRESXRESVtargetVDDDVSSGndIf you want to use P3[3:2] as the SWD interface for run-time debugging, select SWD (serial wire debug) from the DebugSelect pull-down list in the System tab of the DWR window, as Figure 8 shows. Note that if you do so, P3[3:2] cannot be usedas GPIOs.Figure 8. PSoC Creator Debugging SettingsGPIO PinsPSoC 4100/4200 provides flexible GPIO pins. Each pin has a 4-mA source current or an 8-mA sink current capability. Themaximum total source and sink current for all GPIO pins is 200 mA.All GPIO pins can be controlled by firmware. Most of them also have alternative connections to PSoC 4100/4200 peripherals.Different peripherals have different dedicated or fixed pins for their terminals. With dedicated pins, you get the bestperformance when a peripheral is connected to its own dedicated pin or pins. However, for flexibility, you can connect theperipheral to other pins, at the cost of using some internal routing resources.If a peripheral has fixed pins, then you can connect it only to these pins.I/O Pin SelectionWhen you design a hardware system based on PSoC 4100/4200, you should assign the GPIO pins in the following sequence.1.System function pinsa.SWD: If you need run-time debugging, use P3[3:2] .www.cypress.comDocument No. 001-88619 Rev. *B7
PSoC 4100/4200 Hardware Design Considerations2.b.External clock: If you need to use an external clock, use P0[6] .c.Wakeup: This pin is used to wake up PSoC 4100/4200 from the Stop low-power mode. If you need this feature, useP0[7]. For more information, see AN86233 – PSoC 4 Low-Power Modes and Power Reduction Techniques.Analog pinsa.SAR ADC: All the Port 2 pins are used as multichannel inputs to the SAR ADC. Furthermore, if you want a higherADC clock than 3 MHz or you need to apply an external reference, reserve P1[7] for an external bypass capacitorconnection. Refer to the SAR ADC section for details.Port 2 pins are dedicated pins for the SAR ADC. Through the internal analog bus, you can also route signals from theother pins (except Port 4 pins) to the ADC. P1[7] is a fixed pin for the ADC’s reference bypass capacitor connection.b.Low-power comparator: PSoC 4100/4200 has two comparators that can work in the Hibernate low-power mode. Eachcomparator has two fixed pins, as Table 3 shows.Table 3. Pins for Low-Power ComparatorsComponentsc.TerminalsGPIO PinLow-PowerComparator 0Noninverting InputP0[0]Inverting InputP0[1]Low-PowerComparator 1Noninverting InputP0[2]Inverting InputP0[3]Continuous Time Block mini (CTBm): The CTBm module is composed of two opamps. The opamps have dedicatedpins for their noninverting inputs and fixed pins for their inverting inputs and outputs, as Table 4 shows.If you use an opamp as a comparator, you can route the digital output to other GPIO pins (except Port 4).Table 4. Pin List for CTBm OpampsComponentsOp Amp 0Op Amp ng ng InputP1[4]OutputP1[3]P1[6]P1[7]CapSense : When you use this module, note that there are two fixed pins. You must connect a reservoir capacitor(CMOD) to P4[2] in all cases and the other reservoir capacitor (CSH TANK) to P4[3] in some cases. See the PSoC 4CapSense Design Guide for details. You can connect any other pin to a CapSense sensor.Digital pinsa.Timer/Counter Pulse Width Modulator (TCPWM): PSoC 4100/4200 has four TCPWM blocks. Each TCPWM canoutput two complementary PWM signals. All these signals are routed to dedicated GPIO pins via high-speed paths,as Table 5 shows.You can also route these signals via an internal digital connection to other GPIO pins (except Port 4).www.cypress.comDocument No. 001-88619 Rev. *B8
PSoC 4100/4200 Hardware Design ConsiderationsTable 5. Pin List for TCPWMsBlockTCPWM 0TerminalsPWM OutputGPIO PinP2[4]P3[0]Inverted PWM OutputP2[5]P3[1]TCPWM 1PWM OutputP2[6]P3[2]Inverted PWM OutputP2[7]P3[3]TCPWM 2PWM OutputP1[0]P3[4]Inverted PWM OutputP1[1]P3[5]TCPWM 3PWM OutputP1[2]P3[6]Inverted PWM OutputP1[3]P3[7]Serial Communication Block (SCB): PSoC 4100/4200 has two SCBs, which can be configured as SPI, I2C, or UART.Each SCB has fixed pins for its terminals, as Table 6 shows.Unlike TCPWM, the SCB terminals are routed to fixed pins and cannot be routed to any other GPIO pin. You mustfollow the pin assignments in Table 6 when using the SCBs.www.cypress.comDocument No. 001-88619 Rev. *B9
PSoC 4100/4200 Hardware Design ConsiderationsTable 6. Pin List for SCBsBlockSCB 0TerminalsGPIO PinSPI MOSIP4[0]I2C SCLUART RXSPI MISOP4[1]I2C SDAUART TXSCB 1SPI SCLKP4[2]SPI SS0P4[3]SPI SS1P0[0]SPI SS2P0[1]SPI SS3P0[2]SPI MOSIP0[4]I2C SCLUART RXP3[0]SPI MISOP0[5]I2C SDAUART TXP3[1]SPI SCLKP0[6]P3[2]SPI SS0P0[7]P3[3]SPI SS1P3[4]SPI SS2P3[5]SPI SS3P3[6]If your system needs a serial communication interface with a more flexible GPIO pin assignment, you can use a UDBto implement it. See the PSoC 4100/4200 Architecture TRM for details.For an overview of the pin map, refer to PSoC 4: PSoC 4100 Family datasheet and PSoC 4: PSoC 4200 Family datasheet.Port 4 GPIO PinsIn PSoC 4100/4200, Port 4 is different from the other four ports in that it has only four GPIO pins. You can use these pins asSCB pins (see Table 6), CapSense pins, Segment LCD pins, or firmware pins.To achieve a balance between cost and performance, consider the following points for Port 4 in the hardware design:1.You cannot use Port 4 GPIO pins for some analog purposes, including SAR ADC, CTBm, and low-power comparators.2.You cannot route a digital signal to Port 4 GPIO pins. For example, you cannot route digital signals of a UDB-basedComponent or TCPWM to Port 4 GPIO pins.Note If P4[2] or P4[3] is used to connect CMOD or CSH TANK, you cannot route a digital output signal to P3[6] or P3[7].www.cypress.comDocument No. 001-88619 Rev. *B10
PSoC 4100/4200 Hardware Design Considerations3.You can use Port 4 GPIO pins for firmware. However, the synchronization feature will not be available.a.If you want to use a Port 4 GPIO pin for output firmware, select Transparent in the Output M
Apr 21, 2015 · square-wave clock is recommended. PSoC 4100/4200 does not support an external crystal connection. To use the external clock, you must configure system clocks to enable external clock input (EXTCLK), enter the external clock frequency, and select it as HFCLK’s source in the Clocks tab in th
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PSoC 3 and PSoC 5LP GPIO basics and demonstrates techniques for their effective use in a design. It is assumed that you are familiar with PSoC Creator and the PSoC 3 and PSoC 5LP family device architecture. If you are new to PSoC, see the introductions in AN54181, Getting Started
PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of systems based on PSoC 3, PSoC 4, and PSoC 5LP. See Figure 1 - with PSoC Creator, you can: 1. Drag and drop Components to build your hardware system design in the main design workspace 2.
2.1 PSoC Creator PSoC Creator is a free Windows-based Integrated Development Environment (IDE). It enables concurrent hardware and firmware design of systems based on PSoC 3, PSoC 4, and PSoC 5LP. See Figure 1 - with PSoC Creator, you can: 1. Drag and drop Components to build your hardware system design in the main design workspace 2.
PSoC 4: PSoC 4100 Family Datasheet Programmable System-on-Chip (PSoC ) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-87220 Rev. *H Revised April 26, 2017 General Description
001 96819 Owner: JFMD Introduction to PSoC 4 Customer Training Workshop with PSoC 4 M- Series 5 Rev ** Tech lead: PMAD PSoC Terms PSoC PSoC is the world's only programmable embedded system-on-chip integrating an MCU core, Programmable Analog Blocks, Programmable Digital Blocks, Programmable Interconnect and Routing1 and CapSense Programmable Analog Block
