EE382V-ICS: System-on-a-Chip (SoC) Design
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8EE382V-ICS:System-on-a-Chip (SoC) DesignLecture 8 - System Design Methodologywith sources from:Christian Haubelt, Univ. of Erlangen-NurembergAndreas GerstlauerElectrical and Computer EngineeringUniversity of Texas at Austingerstl@ece.utexas.eduSoC Design FlowStartAnalyze NoPRDModifyModel?YesYesMap, Model &Simulate inSPW or Matlab or Cor C Mapping toPlatform orComponentsComplete?NoDesignConvergence andVerificationLoopYesSystemBOM CostsMet?NoYesPowerReq. Met?NoYesAnalyze resultsScheduleReq. mReq. Met?NoYesNoMRDMet?ReturnYesEE382V-ICS: SoC Design, Lecture 8 2010 A. GerstlauerDone 2010 A. Gerstlauer21
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Design ConvergenceFrontFront EndEnd DesignDesignImplementationImplementationReduced convergence time due to minimal data# Optimization SolutionsConvergence time increases due to more design dataReduced convergence time due to reduced solution spaceConvergence time increases due to transition phaseReduced convergence time due to reduced solution spaceDesign ConvergesRapid ExplorationEE382V-ICS: SoC Design, Lecture 8Rapid Traversal 2010 A. Gerstlauer3Design Challenges Complexity High degree of parallelism atvarious levelsApplications Heterogeneity Of components Of toolsProgrammingModel? Low-level communicationmechanisms Programming modelSource: C. Haubelt, Univ. of Erlangen-NurembergEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer42
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Complexity nology churnRobustness“The challenge over the next 20 years will not be speed or cost orperformance; it will be a question of complexity.”Bill Raduchel, Chief Strategy Officer, Sun MicrosystemsEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer5Multi-Processor System-on-Chip ASIPLocal RAMController BusDSPBridgeDSP RAMHardwareAcceleratorDSP BusSharedRAMHardwareAcceleratorVideoFront EndLocal BusSource: C. Haubelt, Univ. of Erlangen-NurembergEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer63
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8MPSoC Terminology Multi-processor Heterogeneous, asymmetric multi-processing (AMP) Distributed memory and operating system Multi-core Homogeneous, symmetric multi-processing (SMP) Shared memory and operating system Multi-core processors in a multi-processor system Many-core 10 cores per processor EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer7Processor Implementation OptionsSource: T. Noll, RWTH Aachen, via R. Leupers, “From ASIP to MPSoC”, Computer Engineering Colloquium, TU Delft, 2006EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer84
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Lecture 8: Outline Introduction System design methodology Electronic system-level design (ESL/SLD) ESL design Modeling Synthesis Verification ESL landscape Summary and conclusionsEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer9System DesignSystem-level ation &VerificationEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer105
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Classical System Design FlowSystem requirement specificationsystemdesignSystem architecture designModelingHardware designsoftwareSoftware on & 382V-ICS: SoC Design, Lecture 8(semi)automatic 2010 A. Gerstlauer11Hardware-Centric Design CycleTaskSpecificationHW designFixes in specificationFixes in hardwareHW verificationSW designFixes in softwareSW verificationIntegration & verificationTimeEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer126
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Hardware-Centric Design Cyclebut you want to know here and hereTask Specification and hereFixes in specificationHW designFixes in hardware HW verificationSW design Fixes in softwareSW verificationIntegration & verification Timeknown if project is successfulEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer13Electronic System-Level (ESL) Design FlowSystem requirement specificationsystemdesignHigh-level modelSystem-level designHardware designhardwaredevelopmentSoftware developmentsoftwaredevelopmentIntegration & Verificationintegration&System implementationverificationmanualEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer(semi)automatic 2010 A. Gerstlauer147
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8New ESL Design CycleTaskSpecification(high-level & arch. models) Fixes in specificationHW design Fixes in hardwareHW verificationSW designFixes in softwareSW verificationIntegration & verificationTimeFind good design options hereEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer15Double Roof askinstructionlogicarchitectureISA ArchRTLImplementationgateSource: A. Gerstlauer, C. Haubelt, A. Pimentel, et al., “Electronic System-Level Synthesis Methodologies,“ TCAD, 2009.EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer168
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Design Methodologies Set of models and design steps (transformations) Top down design Platform based designStarts with functional systemspecification Starts with architecting aprocessing platform for a givenvertical application space Enables rapid creation andverification of sophisticated SoCdesigns variantsPBD uses predictable and preverified firm and hard blocksPBD reduces overall time-tomarket– Application behavior– Models of Computation (MoC) Successive refinementConnect the hardware andsoftware design teams earlier inthe design cycle.Allows hardware and software tobe developed concurrentlyGoes through architecturalmappingThe hardware and software partsare either manually coded orobtained by refinement fromhigher modelEnds with HW-SW co-verificationand System Integration– Semiconductor, ASSP vendors – Shorten verification time Provides higher productivitythrough design reusePBD allows derivative designswith added functionalityAllows the user to focus on thepart that differentiate his designSource: Coware, Inc., 2005EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer17Top-Down ESL Design EnvironmentPrimarilyVirtualPROTOTYPING TEG.& TESTSLDesignSWDESIGNHW & SWCODESIGNPrimarilyPhysicalSWCODINGCost ModelsCopyright 1995-1999 SCRA Used with PermissionEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer189
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Platform-Based Design (PBD)Performance models:Emb. SW, Comm.and Comp. resourcesModels ofComputationSystemPlatformSystemBehaviorModel CheckingBehaviorVerificationPerformanceAnalysisand SimulationMappingHW/SW Partitioning,Scheduling & EstimationArchitectureRefinementSynthesis& CodingFlow To ImplementationSource: UC Berkeley, EECS249EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer19System Design Languages Netlists Structure only: components and connectivity Gate-level [EDIF], system-level [SPIRIT/XML] Hardware description languages (HDLs) Event-driven behavior: signals/wires, clocks Register-transfer level (RTL): boolean logic Discrete event [VHDL, Verilog] System-level design languages (SLDLs) Software behavior: sequential functionality/programs C-based [SpecC, SystemC, SystemVerilog]EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer2010
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Lecture 8: Outline Introduction System design flow ESL design Modeling Synthesis Verification ESL landscape Summary and conclusionsEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer21System Modeling Design models as abstraction of a design instance Representation for validation and analysis Specification for further implementation Documentation & specification Systematic modeling flow and methodology Set of models Set of design steps From specification to implementation Well-defined, rigorous system-level semantics Unambiguous, explicit abstractions, models– Objects and composition rules Synthesis and verificationEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer2211
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Modeling Guidelines A model should capture exactly the aspects required bythe system, and no more. There is not one model/algorithm/tool that fits all. Being formal is a prerequisite for algorithmic analysis. Formality means having a mathematical definition(semantics) for the properties of interest. Being compositional is a prerequisite for scalability. Compositionality is the ability of breaking a task about A Binto two subtasks about A and B, respectively.Source: UC Berkeley, EECS249EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer23Separation of rthogonalizingconcernsacrossmultiple ce: UC Berkeley, EECS249EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer2412
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8System Design Flow Abstraction based on level of detail & granularity Computation and communication System design flow Path from model A to model AUntimedA.B.C.D.E.F.ESystem specification modelTimed functional modelTransaction-level model (TLM)Bus cycle-accurate model (BCAM)Computation cycle-accurate model (CCAM)Cycle-accurate model (CAM)BApproximatetimedComputationCycletimedSource: L. Cai, D. Gajski. “Transaction level modeling: An overview”, ISSS 2003EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer25Computation vs. Communication Separation of concerns Flexibility in modeling IP reuseBus ModelDevice ModelCommunicationComputationMust be synchronizedget a;get b;send c;Communication can be described in awide range of fashions, from high-levelmessages, to detailed signal levelhandshakes without impacting thebehavior description.EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauerc a * b;Behavior can be describedalgorithmically, without the burden ofthe handshaking and control logicassociated with bus communication.Source: Coware, Inc., 2005 2010 A. Gerstlauer2613
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Computation Models Application model Model of Computation (MoC)Process B1(){ waitfor(15000); waitfor(25000); };– Process-/state-based [KPN, SDF, FSM, ] Back-annotated execution timingCPU– Timing granularity (basic block level)B1 Processor model Operating systemB2– Real-time multi-tasking (RTOS), drivers Hardware abstraction layer (HAL)OSHAL Drv ISR– Media accesses Processor hardware– Bus I/O & interrupts Instruction-set model Instruction-set or micro-architectureBusInterrupts– Down to cycle-accurate behaviorEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer27Communication ModelsMEMClkReqSelGrntAddrDataMEM Transaction-Level Model (TLM) Less code, no wires, fewerevents yield faster simulation Protocol is modeled as asingle bus model instead of ineach device Each device communicatesvia transaction-level API 100x-10,000x faster thanPAMCPUTLM APITLM APIBUSTLM APITransactionPeriphTransactions(Function Calls)HREQHGRANTHADDREE382V-ICS: SoC Design, Lecture rfHRESP 2010 A. GerstlauerPin-Accurate Model (PAM) Redundant RTL complexityresults in slow simulation Each device interface mustimplement the bus protocol Each device on the bus has apin-accurate interfacePin/CycleAccurateBUSPeriph CPUSource: Coware, Inc., 2005 2010 A. Gerstlauer2814
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Transaction Level ead(addr)write(addr, data)read(addr)write(addr, data)TLMAPIThe transaction level is a higher level of abstraction forcommunicationFor SoC, communication is often the bottleneckSource: Coware, Inc., 2005EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer29TLM Details Abstracted communication Detailed signal handshaking is reduced to series ofgeneric events called “transactions”. Blocks are interconnected via a bus model, andcommunicate through an API. The bus model handles all the timing, and events on thebus can be used to trigger action in the ess()Bus Model keepstrack of timing.BusModeldataEvent()Event timing cantrigger actions.TargetDatasendData()Initiator and target usean API to communicatevia transfers.Source: Coware, Inc., 2005EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer3015
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8SystemC/TLM 2.0 Pointer to transaction object is passed from module tomodule using forward and backward paths Transactions are of generic payload typeInitiatorForward pathBackward pathInterconnectInitiator/TargetForward pathTargetBackward pathCommandAddressDataByte enablesResponse statusExtensionsSource: OSCI TLM-2.0EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer31SystemC/TLM 2.0 Coding Styles Loosely-timedBEGIN Sufficient timing detail to boot OS andsimulate multi-core systemsEND Each transaction has 2 timing points:Initiatorbegin (call) and end (return) Approximately-timed Cycle-approximate or cycle-countaccurate Sufficient for architectural exploration Each transaction has at least4 timing pointsTargetBEGIN REQEND REQBEGIN RESPEND RESPInitiatorTargetSource: OSCI TLM-2.0EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer3216
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Blocking and Non-Blocking Transports Blocking transport interface Typically used with loosely-timed coding style tlm blocking transport ifvoid b transport(TRANS&, sc time&); Non-blocking transport interface Typically used with approximately-timed coding style Includes transaction phases tlm fw nonblocking transport iftlm sync enum nb transport fw(TRANS&, PHASE&, sc time&); tlm bw nonblocking transport iftlm sync enum nb transport bw(TRANS&, PHASE&, sc time&);Source: OSCI TLM-2.0EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer33Blocking TransportInitiatorTargetSimulation time0nscallb transport(t, 0ns);b transport(t, 0ns);returnSimulation time0nscallb transport(t, 0ns);Simulation time30nswait(30ns);b transport(t, 0ns);returnSource: OSCI TLM-2.0EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer3417
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Non-Blocking TransportInitiatorTargetnb transport(-, BEGIN REQ, 0ns);nb transport(TLM ACCEPTED, -, -);nb transport(-, END REQ, 0ns);nb transport(TLM ACCEPTED, -, -);nb transport(-, BEGIN RESP, 0ns);nb transport(TLM ACCEPTED, -, -);nb transport(-, END RESP, 0ns);nb transport(TLM ACCEPTED, -, -);Source: OSCI TLM-2.0EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer35Virtual Platform PrototypingComputation refinementUntimedTLM (LT/AT)PCAMVirtual PrototypeCommunication refinementEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer3618
EE382V-ICS: System-on-Chip (SoC)DesignLecture ModelingHostHost-compiledNot al temsystem-Point to point-MemoryMemory-mappedLoosely AssemblyAssemblyHardware RefinementPeripheralUntimedApproximatelyTimedTimed teTLM(Transfer Level)RTLTF(DUT) (rest)RTL VerificationSystem-level e-CompletedesigndesignatatRTLRTL-System-level ing Simulation PerformanceFunctional ValidationIncreasing Scope for Relative OptimizationAbstraction LevelsRTLSource: Coware, Inc., 2005EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer37Speed vs. AccuracyUTHost-based10MIPSLog S P E E D1MIPSIA ISSTLM BusRe-use ystemCExecutable TLMCycleAccurate-TLM100KcpsRe-use for TL10Kcps1KcpsLT3 McpsCA150 kpsPAM RTL15 kps100cpsLog A C C U R A C YEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer3819
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Lecture 8: Outline Introduction System design methodology ESL design Modeling Synthesis Verification ESL landscape Summary and conclusionsEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer39Design Automation Synthesis Decision making model elModel nModel nOptim.Optim.algorithmalgorithmDesign decisionsRefinementRefinementDBDBModelModeln 1n 1Implementation modelImplementation model Successive, stepwise model refinement Layers of implementation detailEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer4020
EE382V-ICS: System-on-Chip (SoC)DesignLecture hesisDecisionmakingStructureTransactionLevel ModelRefinementQualitynumbersLatency, Area,Throuput, etcSource: A. Gerstlauer, C. Haubelt, A. Pimentel, et al., “Electronic System-Level Synthesis Methodologies,“ TCAD, 2009.EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer41Platform-Based System SynthesisApplicationPlatformOptimal Mapping ?EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer4221
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Resource Allocation Resource allocation, i.e., select resources from aplatform for implementing the applicationEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer43Process Binding Process mapping, i.e., bind processes onto allocatedcomputational resourcesEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 2010 A. Gerstlauer4422
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Channel Routing Channel mapping, i.e., assign channels to paths overbusses and address spacesEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer45Design Space Exploration Design Space Exploration is an iterative process: How can a single design point be evaluated? How can the design space be covered during theexploration process?Evaluatingdesign pointsEE382V-ICS: SoC Design, Lecture 8 2010 A. GerstlauerCovering thedesign space 2010 A. Gerstlauer4623
EE382V-ICS: System-on-Chip (SoC)DesignLecture 8Optimization Approaches Exact methods Enumeration, (Integer) Linear Programs Heuristics Constructive– Random mapping, hierarchical clustering Iterative– Random search, simulated annealing, min-cut (Kernighan-Lin) Set-based (“intelligent” randomized search)– Evolutionary Algorithms (EA),Particle Swarm Optimization (PSO),Ant Colony Optimization (ACO) Exact, constructive & iterative methods are prohibitive Large design space, multiple objectives, dynamic behavior Set-based approaches Randomized, problem independent (black box), Pareto setEE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer47Evaluation Approaches Dynamic simulation Profiling, ISS/RTL co-simulation Long simulation times, corner cases Static analysis Component-level estimation[Worst-Case Execution Time (WCET)] System-level cost functions, real-time calculus[Modular Performance Analysis (MPA)] Inaccurate bounds, manual interference (false paths) Combinations Host-compiled simulation Trace-
EE382V-ICS: System-on-Chip (SoC) Design Lecture 8 2010 A. Gerstlauer 3 EE382V-ICS: SoC Design, Lecture 8 2010 A. Gerstlauer 5 Complexity ForcesFile Size: 701KB
For specific safety information, read the Safety Message. For specific medical information, refer to the ICS 206. 5. Site Safety Plan Required? Approved Site Safety Plan(s) Located at: 6. Incident Action Plan (the items checked below are included in this Incident Action Plan): ICS 202 ICS 203 ICS 204 ICS 205 ICS 205A ICS 207 ICS 208 ICS 220 Map .
Jan 08, 2015 · Incident Organization Chart (ICS 207) Site Safety Plan (ICS 208) Incident Summary Status (ICS 209) Check-In List (ICS 211) General Message (ICS 213) Resource Request Message (ICS 213RR) Activity Log (ICS 214) Operational Planning Worksheet (ICS 215) Incident Action Plan Safety Analysis (ICS 215a)
Jan 08, 2015 · Incident Organization Chart (ICS 207) Site Safety Plan (ICS 208) Incident Summary Status (ICS 209) Check-In List (ICS 211) General Message (ICS 213) Resource Request Message (ICS 213RR) Activity Log (ICS 214) Operational Planning Worksheet (ICS 215) Incident Action Plan Safety Analysis (ICS 215a)
Number Purpose ICS 201 (p.1)** Incident Briefing Map ICS 201 (p.2)** Summary of Current Actions ICS 201 (p.3)** Current Organization ICS 201 (p.4)** Resources Summary ICS 202 Incident Objectives ICS 203 Organization Assignment List ICS 204 Assignment List ICS205 Incident Radio Communications Plan
This unit will review the ICS features and concepts presented in ICS-100 through ICS-300. Unit 2 Fundamentals Review for Command and General Staff Page 2-2 ICS-400: Advanced ICS—Student Manual August 2006 Topic Unit Objectives Visual 2.2 Unit 2: Visual 2.2 Fundamentals Review for Command and General Staff Unit Objectives (1 of 2) Describe types of agency(ies) policies, guidelines, and .
1 MGT-347 ICS Forms February 5, 2019 Franklin County 2 ICS-300 Intermediate ICS February 5 – 7, 2019 Franklin County 3 ICS-300 Intermediate ICS February 6 – 8, 2019 Montgomery Co. 4 OH-230 Intro. to Emergency Management in Ohio February 11 - 14, 2019 Ohio EMA 5 ICS-400 Advanced ICS February 12 - 13, 2019 Wood County
Entering programming for system coordinators 134 Entering programming using other passwords 135 . (key system), AB6CAN-20706-MF-E (hybrid system), and AB6CAN-23740-PF-E (PBX system). Connection of the Norstar key telephone system to the nationwide telecommunications network is made . Nortel Networks. ISDN . ICS ICS. ICS. ICS. ICS. Compact
2nd Grade . ELA Priority Standards Grade 2 CCSS PA Core Foundational Skills RF.2.3 CC.1.1.2.D Know and apply grade level phonics and word analysis skills in decoding words. Distinguish long and short vowels when reading regularly spelled one- syllable words. Decode two-syllable words with long vowels and words with common prefixes and suffixes. Read grade level high-frequency .
