EEL3701 ASM Chart Design: States, Outputs

ASM Design14-Mar-21—1:49 PMEEL3701Menu ASM charts ASM DesignLook into my .University of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoEEL37011ASM Chart Design:States, Outputs States: Each active clock transition causes a change ofstate from the present state to the next stateName 101Out1 Use a rectangle for the symbol of a state with itssymbolic name at the upper left (or right) corner with statebit assignment in the upper right (or left) corner Outputs: Place outputs within the appropriatestate rectangleFlowchart, but not ASM Description is ok, but not part of ASM; descriptionsare part of flowcharts (often a step before ASM)––––Start Print Cycle: Actions to takeLine is to be loaded into the print bufferBUSY: Assert the signal BUSYStatus LPR5, output variable STATUS has the samevalue as bit 5 of the LPR register.– AC register is to be cleared by the end of the cycleUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoPrint LineStart print cycleLine PrintbuffBUSYStatus LPR50 AC21

ASM Design14-Mar-21—1:49 PMEEL3701ASM Chart Design: Branches,Conditional Outputs Branches: Conditional branches indicate that thenext state is determined not only by the presentstate, but also by the value of one or more testIn10 or Finputs. Indicate branches with a diamond or a1 or Tdiamond-sided rectangle. Conditional Outputs: Place the output commanddescription within an appropriate oval placed in aCMD2path to indicate its dependence on a given testinput. AKA asynchronous outputs, Mealy outputs. THIS IS THE ENTIRE ASM NOTATION!!!University of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo3EEL3701ASM ChartsState Bits Legend:Strobe S3 S2 S1 S000010State Bits(if assigned)OpeningState Outputs inside(State outputs thatMotorare not state bits)1Never start adesign until afteryou first create anASM diagramState NameX0BrakeUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoDecision an input or afunction of input(s); ex: Xor X A*B or X A B*CConditional Output(Mealy Output)42

ASM Design14-Mar-21—1:49 PMEEL3701Designing ASM Charts Many complain about lack of tools for flowcharts Microsoft has Visio (available for free from MSDNAA) A program at app.diagrams.net/ that runs in your web browserworks VERY WELL and is VERY EASY TO USE Otherwise, you can use a drawing tool that has the “snapto-grid” option Construct each of the element types and then just copy and pasteas needed– Make the decision diamond out of lines (to get grid to sity of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo5EEL3701ASM Chart Design:State Outputs In final ASMs (i.e., ready for implementation),only TRUE outputs are inside state rectangles Ex: First part of a 3-bit counterStartStartC 0, B 0, A 0S1C 0, B 1, A 0University of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoS1B63

ASM Design14-Mar-21—1:49 PMEEL3701Moore/Mealy Comparison[Example] Design a Sequence Detector/Acceptor to accept X 010*1where 0* { (nil), 0, 00, 000, 0000, . } STEP 1: Draw the State Diagram.Mealy 110BushS50/01/1111ReaganS3011FordS2000S0/Z 0ClintonX 1001CarterS11/00/0X 10/00/0010S4/Z 1Nixon1/10/0MooreStart001S1/Z 0CarterX 1X 1X 0110S5/Z 1BushX 0X 1X 0X 0X 0X 1111S3/Z 0ReaganX 0011S2/Z 0FordUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo7ASM Example: MealySeq. DetectorEEL3701START Let us repeat thedesign usingASM notation(either Z or, forZMealy & S00000 X1CARTERS10010XFORD 1011S210ZXS3NIXON 010REAG.S401University of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo1ZXS5BUSH111X0Z1101X084

ASM Design14-Mar-21—1:49 PMEEL3701ASM Example: MooreSeq. DetectorSTART Let us repeat thedesign usingASM notation(either Z or, forZMealy & Moore,respectively)(Moore)StateOutputCLINTONS00000 XCARTERS1FORD 1S21NIXON 010S4Z0X1University of Florida, EEL 3701 – File 18 Drs. Schwartz & 1Outputs: Conditional on State Q: Should you use conditional or state outputs? A: Dealer’s Choice. You can mix them; just be careful withconditional outputs.Note: S0ZORZState (Moore) OutputConditional (Mealy) outputLook at S2. Suppose X changes between clock pulses. What happensto Z for the Mealy machine?X?But X is notusuallyZsynchronizedClockUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo105

ASM Design14-Mar-21—1:49 PMEEL3701Conditional (Mealy) Outputs In state S2 (Ford), if X changes between clock pulses, Z changes alsoif you use conditional outputs. These changes that occur betweenclock pulses are called spurious pulses.The synchronous circuit that is attached to Z does not care about thisif it is also clocked! Note that this f(Z) will come out one clock laterthan if Z was a State (Moore) output.XZComb3DQf (Z)Q33-FFCLKUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoNote: f (Z) does not care about spuriouspulses because when clock comes in, bothX, Z, and f (Z) are “stable.”EEL370111Why Use an ASM? We can attach semantic meaning to the state labels e.g., letClinton be Start, let X be Sig, let Z be Valid, let Reagan beAccept-1, let Bush be Accept-2, etc. To realize the Comb (the Combinational Network), wechoose one of the following: 1. Gate approach - K-Maps, AND/OR, NAND, NOR, .We know 2. PLD, CPLD 1k x 8 8 functions of 10 variables5 ways000 3. MUXalready!f7 f6 f5 f4 f3 f2 f1 f0 4. ROM3FF 5. Other LSI circuits fi is a function of 10 inputs labeled A9 A0, and i is0,1,2,3,4,5,6,7. We store the truth table for fi in each 6. P or Ccolumn of ROMUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo 8 bits 1 byte, 4 bits 1 nibble, 1k 210 1024, M 220 (mega-), G 230 (giga-), T 240 (tera-) 1k x 8bits 1KB 1 kilobyte 2 10 bytesUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo126

ASM Design14-Mar-21—1:49 PMEEL3701Digital Design for Controllers In the typical digital design application we are askedto design circuits to control existing systems.n-inputsCircuitsControllerto beCarsASMm-outputs controlled Traffic LightsJet EnginesPower PlantsPrinters Given m-outputs with n-inputs, the problem is to develop theASM to control a system. As in the case of controlling aprinter, the “controlled” circuits themselves could be anASM.University of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoEEL370113ASM Design Example:Washing Machine ControllernControllerWasherSTRTASMTimerSHOT When the controller receives a STRT (start)signal (from the user), it fills the washer witheither cold or hot water SHOT is true for hot water, false for cold Agitation starts until a timer runs out Dirty/soapy water is then pumped out Cold rinse water is pumped in until filled;agitation starts until a timer runs out Dirty/soapy water is then pumped out Spinning starts until a timer runs out. STRT button is reset. After starting, if the STRT button is ever “OFF,” the washer“HOLDS”(hold its state) until the STRT button is “ON” again.University of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo147

ASM Design14-Mar-21—1:49 PMEEL3701Washing Machine I/O STEP 1 List the inputs and outputsInputsSTRT (Start from User)SHOT (Select Hot from User)FULL (Tub Full Indicator)EMP (Tub Empty Indicator)TO (Timer Out Indicator)5-inputs would require 25 32arrows going out of the bubblesif we used a state diagram(which is why we instead use anASM chart)OutputsOHOT (Turn On Hot water valve)PUMP (Turn On Pump)FILL (True: water-in, False: water-out)AG (Agitate)STIME (Clear & Start Timer)SPIN (Spin Dry)STRTOFF (Go to Idle State)University of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo15EEL3701Wash Mach: ASM Chart STEP 2 Draw ASM chartFAIdleSTRT1SHOT0FULL0If an output isn’t written,it is assumed to be false.AgitateSTIME0B Empty waterDrainAgitate1OHOT1APUMPFILLUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoSTRT1AGTO1B0STRT10PUMP0EMP1(go to Rinse 1) C0168

ASM Design14-Mar-21—1:49 PMEEL3701More Wash Mach ASMRinse 1CRinse2Rinse1STRT1FULL0PUMPFILLE Spin DryD Rinse 2011PUMPSpinItSTRT 01TO0STIMESTRT11AGEMPTO0SPIN0STRTOFF1D0ESTIMEF (go to Idle)University of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo17EEL3701Wash Mach ROM Realization STEP 3 ROM CLKUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & 7256 x rsity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoPUMPFILLAGOHOTSTIMESPINSTRTOFFInputsSTRT (Start from User)SHOT (Select Hot from User)FULL (Tub Full Indicator)EMP (Tub Empty Indicator)TO (Timer Out Indicator)OutputsOHOT (Turn On Hot water valve)PUMP (Turn On Pump)FILL (True: water-in, False: water-out)AG (Agitate)STIME (Clear & Start Timer)SPIN (Spin Dry)STRTOFF (Go to Idle State)189

ASM Design14-Mar-21—1:49 PMEEL3701Reducing Number of Inputs We need 10 data lines (tough to find ROM/RAM with 10data lines). So in order to reduce the number of data lines,try to find outputs that are functions of other outputs (or pickoutputs to determine directly outside the ROM/RAM) STRTOFF and SPIN are such outputs (both in state SpinIt withQ2Q1Q0 101) Simple to get these outputs as function of known )Q2(H)STRT(H)TO(L)SPINNow we can use 256 x 8 ROM!!!University of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo19EEL3701 Moore and Mealy ASMCharts versus State GraphsSee Lam Fig 7.12University of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo2010

ASM Design14-Mar-21—1:49 PMEEL3701 Moore and Mealy ASMCharts versus State GraphsSee Lam Fig 7.13University of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo21EEL3701ASM to Timing DiagramA00Count.EnReg.LD DEFINITION: State A “stable”condition of the controller over aclock cycle (a fixed period oftime) Skill 1: From ASM to TimingDiagramShown also inLam Fig 7.2 (a)B 01In.BitC01 10Reg.LD0Buf.Full1Count.EnUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoD11Out.Flag2211

ASM Design14-Mar-21—1:49 PMEEL3701A00Count.EnReg.LDASM To Timing DiagramB 01In.Bit DEFINITION: State A “stable”condition of the controller over a clockcycle (a fixed period of time) Skill 1: From ASM to Timing Diagram0C 1 10Reg.LD0Buf.Full1Count.En(a) Start at state A. In state A:D11Out.FlagInputs: In.Bit {0,1}, Buf.Full *Outputs: Count.En T, Reg.LD T [Out.Flag F]Note: Buf.Full does not affect state A.(b) From state A, if In.Bit 0, go to state B. In state B:Inputs: In.Bit *, Buf.Full *Outputs: None [Count.En F, Reg.LD F, Out.Flag F]Note: {In.Bit,Buf.Full} do not affect state B; always go to state AUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & Arroyo23EEL3701ASM To Timing Diagram(c) From state A, if In.Bit 1, go to state C. In state C:Inputs:In.Bit *, Buf.Full {0,1}Outputs: Reg.LD T, Count.En {T,F},[Out.Flag F]0NOTE: In.Bit does not affect state C(d) From state C, if Buf.Full 0, stay at state C[& Count.En F](e) From state C, if Buf.Full 1, Count.En T & go to D.state D:Inputs: None [In.Bit *, Buf.Full *]Outputs: Out.Flag T, [Count.En F, Reg.LD F](f) From state D, go to state A (Inputs: None, Outputs: Out.Flag T)This can be summarizedin a Timing Diagram:See Lam Fig 7.2(b)University of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoUniversity of Florida, EEL 3701 – File 18 Drs. Schwartz & ArroyoA00Count.EnReg.LDB 01In.Bit0C 1 10Reg.LDBuf.Full1Count.EnIn 11DOut.FlagCurrent State A B A C C DStep #1 2 3 4 5 6In.Bit0 * 1 * * *Buf.Full* * * 0 1 *Count.En1 0 1 0 1 0Reg.Ld1 0 1 1 1 0Next StateB A C C D AA7112412