An Open Source Digital Servo For Atomic, Molecular, And .
REVIEW OF SCIENTIFIC INSTRUMENTS 86, 123115 (2015)An open source digital servo for atomic, molecular, and optical physicsexperimentsD. R. Leibrandta) and J. HeideckerNational Institute of Standards and Technology, Boulder, Colorado 80305, USA(Received 26 August 2015; accepted 8 December 2015; published online 30 December 2015)We describe a general purpose digital servo optimized for feedback control of lasers in atomic,molecular, and optical physics experiments. The servo is capable of feedback bandwidths up toroughly 1 MHz (limited by the 320 ns total latency); loop filter shapes up to fifth order; multiple-input,multiple-output control; and automatic lock acquisition. The configuration of the servo is controlledvia a graphical user interface, which also provides a rudimentary software oscilloscope and toolsfor measurement of system transfer functions. We illustrate the functionality of the digital servo bydescribing its use in two example scenarios: frequency control of the laser used to probe the narrowclock transition of 27Al in an optical atomic clock, and length control of a cavity used for resonantfrequency doubling of a laser. [http://dx.doi.org/10.1063/1.4938282]I. INTRODUCTIONControl is ubiquitous in atomic, molecular, and optical(AMO) physics. A typical experiment might include a dozenor more feedback controllers for tasks such as laser frequency,power, and phase stabilization;1,2 temperature stabilization;3and vibration isolation.4 Yet the control repertoire practicedby an average AMO physicist is often limited to simpleproportional-integral-derivative (PID) feedback, unable toleverage the developments of the field of control theoryover the past several decades.5,6With the rapid development of hardware suitable forlow-latency digital signal processing (DSP), such as fieldprogrammable gate arrays (FPGAs) and digital signalprocessors, high-speed digital feedback controllers havebecome increasingly practical and increasingly common overthe past decade. The advantages of a digital approach includefast and easy (no soldering) reconfiguration of the feedbacktransfer function; implementation of multiple-input, multipleoutput (MIMO) transfer functions with shapes that go beyondPID,3,4,7–9 the ability to detect whether the system is currentlylocked and to perform automatic lock acquisition,10–12 theintegration of signal pre-processing such as digital lockin amplifiers for generation of the error signal,13 and theintegration of diagnostics for easy analysis of open- andclosed-loop system performance.2 While for many yearsdigital controllers were limited to low bandwidth applicationssuch as temperature controllers, modern hardware is capableof MHz bandwidth feedback control. However, there istypically a tradeoff between ease of use and performance,with microcontrollers being easier to program and lessexpensive but limited to feedback bandwidths below about100 kHz,9,10,12 and digital signal processors and FPGAsbeing capable of several MHz feedback bandwidths but moreexpensive and usually requiring knowledge of specialized,low-level programming languages.7,8,13a)Electronic mail: david.leibrandt@nist.govWe have developed a general purpose digital servooptimized for feedback control of lasers in AMO physicsexperiments. The servo is based on a custom-built hardwarebox that includes a FPGA for computation of feedback transferfunctions, two channels of low-noise and high-speed analogto-digital conversion (ADC), and three channels of lownoise and high-speed digital-to-analog conversion (DAC).The hardware latency is suitable for feedback to acoustooptic modulators (AOMs) with bandwidths of several hundredkHz, and one of the analog output channels includes a highvoltage amplifier for driving piezoelectric transducers (PZTs).Configuration of the feedback transfer function and diagnostictools is controlled via a graphical user interface (GUI) thatruns on a standard personal computer (PC). The hardware andsoftware design is public domain and available for downloadonline.14 Others are encouraged to use the digital servo as itis (which does not require knowledge of any programminglanguages), or to modify the design to suit their own purposesand to contribute their modifications to the project website.The goal of this project is to lower the entry barrier for the useof high-performance digital control tools, enabling physiciststo go beyond simple PID.This paper proceeds as follows. Section II describes thehardware, firmware, and software design of the digital servo.Section III describes the use of the digital servo in twoexample applications: frequency control of the clock laserused in an 27Al optical atomic clock, and length controlof a cavity used for resonant frequency doubling of a laser.Some of the advantages of the digital servo relative to analogservos are highlighted. Section IV summarizes and concludes.Finally, the Appendix presents a detailed description of thedigital filter design used in the digital servo.II. DESIGNThe digital servo is comprised of a custom-built hardwarebox that implements the desired feedback transfer functionusing infinite impulse response (IIR) filters in a FPGA,0034-6748/2015/86(12)/123115/11/ 30.0086, 123115-1This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitationnew.aip.org/termsconditions. Downloaded to IP:132.163.136.61 On: Tue, 12 Jan 2016 18:58:25
123115-2D. R. Leibrandt and J. Heideckerfirmware that describes the DSP in the FPGA, and a softwareGUI that runs on a PC for setting the feedback transfer functionand controlling diagnostic tools. These three components willbe described in Subsections II A–II C.A. HardwareThe digital servo hardware consists of two printed circuitboards (PCBs) packaged in a 56 200 205 mm3 box.The first is a commercial FPGA integration module (OpalKelly XEM6010-LX150,15) which contains a Xilinx Spartan6 XC6SLX150-2 FPGA,15 a 32 Mb flash memory, a 128Mb SDRAM, and a universal serial bus (USB) 2.0 interface.This FPGA was selected for its combination of high DSPperformance and relatively low cost. Specifically, it contains180 DSP48A1 slices that are each capable of performing18 18 bit signed integer multiplication in a single clockcycle. The 35 35 bit signed integer multiplications used tocompute the IIR filters in the digital servo are performedusing four DSP48A1 slices combined to form a singlemultiplier. Although the maximum clock rate for these 35 35multipliers is specified to be 39 MHz in the timing reportgenerated by the Xilinx ISE Design Suite,15 we overclockthem at 100 MHz without any pipeline stages and have notseen any resulting multiplication errors. Note, however, thatall testing and operation of the digital servos reported heretook place in well temperature controlled laboratories, and thattemperatures or supply voltages closer to the specified limitsof the FPGA may cause multiplication errors at this clock rate.The flash memory is used to store both the FPGA firmwareand the servo feedback configuration while the power is off.The SDRAM is used to store the values of the digitized signalsat sample rates up to 6 MHz; these data are read back to thePC at a slower rate for off-line analysis of noise spectra andtransfer functions. The digital servo hardware communicateswith the PC over the USB interface.The second PCB is a custom-built daughterboard thatprovides two channels of high-speed analog input, twochannels of high-speed analog output, and one channel oflow-speed analog output. The high-speed inputs and outputsare implemented by a two channel, 16 bit ADC (LinearTechnology LTC219515) and a two channel, 16 bit DAC(Analog Devices AD978315), both of which operate withupdate rates of 100 MHz. These chips were selected fortheir low pipeline delays, their low noise, and their use oflow voltage differential signal (LVDS) interfaces. Input andoutput range scaling of the high-speed channels is provided byvariable gain amplifiers (VGAs, Analog Devices AD825115),so that the high-speed inputs have a software selectable rangeof 0.5 V, 1 V, 2 V, or 4 V and the high-speed outputshave a software selectable range of 1 V, 2 V, 4 V, or 8 V. The analog bandwidth of the high speed inputs andoutputs is limited by the VGAs to between 3 MHz and10 MHz depending on the gain setting. The low-speed outputis implemented by a single channel, 20 bit DAC (AnalogDevices AD579115) that operates with a 1 MHz update rate.Two output amplifiers are included so that the output range0 V to 10 V is available on one output connector and theRev. Sci. Instrum. 86, 123115 (2015)output range 0 V to 65 V is available on a second outputconnector. The daughterboard also provides several channelsof digital input, which can be used for integrator hold orautomatic lock acquisition functionality, and digital output,which can be used to tell other parts of a complex experimentwhether the servo is currently locked.The input noise of the analog inputs when set to the 0.5 V input range and shorted to ground is 50 nV/ Hz at1 kHz, and the long-time stability is 2 µV for averaging timesbetween 10 3 s and 103 s (in a well temperature controlledlaboratory). Note that this stability is smaller than one bit of the16 bit ADC, which is possible because we are oversamplingin the regime where the analog noise at the input of the ADCis slightly larger than one bit.16 This dithering is important asit suppresses limit cycle oscillations. The output noise of thehigh-speed analog outputs when set to the 1 V output rangeis 40 nV/ Hz at 1 kHz. The output noise of the low-speedanalog output is 20 nV/ Hz at the 0 V to 10 V output rangeconnector and 300 nV/ Hz at the 0 V to 65 V output rangeconnector at 1 kHz.B. FirmwareThe digital servo firmware is written in the Veriloghardware description language17 using the Xilinx ISE DesignSuite.15 Figure 1 shows a block diagram depicting the DSPmodules and signal paths. Most of the calculations areclocked at 100 MHz. The discretized analog signals arepassed between DSP modules in the FPGA as 24 bit signedinteger signals, and the IIR filters internally use 35 bit signedinteger signals to represent both the data and the coefficientsto prevent rounding errors.8 The settings of each module andall of the signal connections not pictured in Fig. 1 are softwareconfigurable in the GUI, and many of the IIR filters can beoptionally bypassed when they are not needed to minimizethe latency.Each of the analog inputs is immediately followed bya first-order IIR filter. This filter can be either enabled ordisabled (bypassed) and is typically configured as a lowpass filter to remove input noise above the desired feedbackbandwidth.Each analog output signal is generated as the sum ofa loop filter module (i.e., feedback controller), a sweepmodule that generates a triangle wave, and a relock modulethat performs automatic lock acquisition. The loop filtermodule can take any of the analog signals as its inputand consists of up to four sequentially applied first- orsecond-order IIR filters. For example, a proportional-integralintegral-derivative (PIID) filter, which is third order, can beconfigured by enabling three sequential first order IIR filters(PI, PI, PD where PI is a proportional-integral filter andPD is a proportional-derivative filter). For a comprehensivedescription of the IIR filters implemented in the digital servoas well as Bode diagrams of the built-in IIR filter transferfunctions, see the Appendix. The relock module can acceptany of the analog signals or digital inputs as its input. If theinput signal is within the software defined “locked” range, therelock module output is zero. If the input signal falls outsideThis article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitationnew.aip.org/termsconditions. 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123115-3D. R. Leibrandt and J. HeideckerRev. Sci. Instrum. 86, 123115 (2015)FIG. 1. Block diagram depicting the digital servo DSP modules and signal paths. Green blocks are analog components and blue blocks are DSP modulesimplemented in the FPGA. Note that this FPGA configuration uses 164 out of 180 available DSP48A1 slices. Utilization of all other types of FPGA resourcesis below 50%. FPGA: field-programmable gate array; VGA: variable gain amplifier; ADC: analog-to-digital converter; DAC: digital-to-analog converter; IIR:infinite impulse response filter; LP: low-pass filter; LO: lock-in local oscillator; MOD: modulation signal used for transfer function measurement; AINx: analoginput channel x; AOUTx: analog output channel x; DINx: digital input channel x; DOUTx: digital output channel x.the “locked” range, the relock module holds the output (andinternal state) of the loop filter module constant and outputsa triangle wave sweep with an amplitude that doubles everycycle and a constant slew rate. Once the input signal returnsto the “locked” range, the loop filter module is re-enabled andthe relock module output ramps back to zero.In addition to the input and output signals discussedabove, there are digital lock-in amplifier and digital phasedetector modules implemented in the FPGA (see Fig. 2). Thelock-in module takes either of the analog inputs, optionallyapplies a pre-filter (typically a high-pass filter), multipliesit by an internally generated local oscillator, and optionallyapplies a post-filter (typically a low-pass filter). The lock-inlocal oscillator (LO) signal can be summed onto any of theanalog outputs. The phase detector module takes either of theanalog inputs, multiplies it by both quadratures of a secondinternally generated LO, low-pass filters the products, andthen takes the arctangent of the ratio of the results. Thephase detector LO can optionally be clocked from an external10 MHz reference. The phase detector output is unwrappedsuch that it can track phase noise with an amplitude up to 216π rad. Undetected cycle slips are avoided as long as theabsolute value of the input phase minus the LO phase changesby less than π rad in each 10 ns FPGA clock cycle.The minimum latency of the servo, measured as the timedelay for a signal to propagate from an analog input to oneof the fast analog outputs, is τ 320 ns including a singlefirst-order IIR filter. This limits the feedback bandwidth toroughly 1 MHz (more precisely there is a π phase shiftat f 1/(2τ) 1.6 MHz). Additional IIR filters and otherfunctionality can be enabled at the cost of increased latencyand hence reduced feedback bandwidth. Table I lists thelatency of several of the DSP modules used in the digitalservo. The latency of each module should be kept in mindwhen selecting a loop filter configuration for high-bandwidthapplications.This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitationnew.aip.org/termsconditions. Downloaded to IP:132.163.136.61 On: Tue, 12 Jan 2016 18:58:25
123115-4D. R. Leibrandt and J. HeideckerRev. Sci. Instrum. 86, 123115 (2015)Internally, the GUI controls the configuration and theconnectivity of the DSP modules described in Sec. II B.Additionally, the GUI includes a rudimentary softwareoscilloscope that can be used to monitor the performanceof the system and controls for recording the values of thedigital servo signals to files on the PC. Finally, the GUI canimplement slow feedback to control the temperature of lasersvia a recommended standard 232 (RS-232) serial port.The digital servo hardware and firmware are capable ofrunning autonomously, without being connected to a PC. Ofcourse, most of the configuration settings cannot be changedin this mode, but we have found that for some applications therelock module is able to keep the system locked without anyhuman intervention for weeks at a time. This capability alsoallows the digital servo to run continuously while the controlPC is restarted.III. EXPERIMENTAL APPLICATIONSFIG. 2. Block diagram showing details of the lock-in amplifier and phasedetector modules. AINx: analog input channel x; HP2: second-order highpass IIR filter; LP2: second-order low-pass IIR filter; φ: phase shifter; LO:local-oscillator; LP: first-order low-pass IIR filter; LOCKIN: lock-in amplifier module output signal; PHASEDET: phase detector module output signal.C. SoftwareThe digital servo software is written in the C programming language and uses the Qt application developmentframework18 for creation of the GUI. Qt enables easyportability between different operating systems, and we havecompiled and run the digital servo GUI on both MicrosoftWindows15 and Linux.The primary functionality of the GUI is to provide(virtual) knobs for setting the feedback transfer functions.This section presents two example applications of thedigital servo, which serve to illustrate some of the advantagesover an analog servo. The first is a frequency servo for alaser that is used to drive the narrow 1S0 3P0 transition of27 Al in an optical atomic clock.19 This example illustratesMIMO feedback and the automatic relocking feature ofthe digital servo. The second is a length servo for a laserfrequency doubling cavity.20 This example illustrates use ofthe digital servo for system transfer function measurementand implementation of a feedback transfer function whichincludes a notch filter.A. Clock laser frequency servoWe have used the digital servo to lock the frequency of a1070 nm fiber laser to a Fabry-Pérot cavity, as describedby Leibrandt, Bergquist, and Rosenband21 and shownschematically in Fig. 3. The cavity length is thermally shiftedTABLE I. Computational cost of DSP modules and hardware used in the digital servo. Note that the latency andthroughput values assume a 100 MHz FPGA clock. Communication with both the ADC and the high-speed DAC isa combination of parallel and serial, and the firmware latencies are dominated by serialization and deserializationof the data.ModuleADC totalHardwareFirmwareHigh-speed DAC totalHardwareFirmwareLow-speed DAC totalHardwareFirmwareFirst order low-pass IIR filterFirst order generic IIR filterSecond order generic IIR filter (time multiplexed)Lock-in amplifier (not including pre and post-filters)Phase detector (including post-filters)Transfer function measurementLatency (ns)Throughput (MHz)DSP48A1 1.100100100/271001001000.0.0.81246255This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitationnew.aip.org/termsconditions. Downloaded to IP:132.163.136.61 On: Tue, 12 Jan 2016 18:58:25
123115-5D. R. Leibrandt and J. HeideckerRev. Sci. Instrum. 86, 123115 (2015)FIG. 3. Block diagram depicting feedback control of the laser frequency of a laser used for interrogation of the clock transition of 27Al . Gray paths denoteelectrical signal propagation, and red paths denote laser propagation. RS-232: recommended standard 232 serial port; USB: universal serial bus; I: integralIIR filter; PI: proportional-integral IIR filter; PD: (gain limited) proportional-derivative IIR filter; LP: low-pass IIR filter; FREQ: frequency tuning port; AMP:amplitude tuning port; VCO: voltage-controlled oscillator; LP: low-pass filter; LO: local oscillator; DBM: double-balanced mixer; PD: photodiode; TEMP:temperature tuning port; PZT: piezoelectric transducer tuning port; AOM: acousto-optic modulator; EOM: electro-optic phase modulator; PBS: polarizing beamsplitter; λ/4: quarter-wave plate.by the circulating laser power in the cavity, so we must alsostabilize the circulating power. The actuators in this exampleare the temperature of the laser (for slow laser frequencycorrections), a PZT in the laser (for intermediate speed laserfrequency corrections), the frequency of a voltage-controlledoscillator (VCO) that drives a fiber-coupled acousto-opticmodulator (AOM, for fast laser frequency corrections), andthe amplitude of the VCO (for laser power corrections).The laser frequency error signal is derived from the cavityreflection by the Pound-Drever-Hall (PDH) method,22 and thecirculating power error signal is generated by a photodiodewhich monitors the laser power transmitted through the cavity.The transfer function for fast laser frequency feedback viathe VCO frequency is PIID. The derivative gain is used toincrease the achievable feedback bandwidth, which is limitedto 500 kHz by the acoustic-wave propagation time in the AOM(i.e., a time delay). Since the frequency tuning range of theAOM is limited to a few MHz, we also feed-back to the laserPZT with a bandwidth of the order of 10 Hz and a frequencytuning range of a few tens of MHz, and we feed-back to thelaser temperature with a bandwidth of the order of 10 mHz andan unlimited frequency tuning range. All of these feedbackpaths are implemented using a single digital servo hardwarebox. The AOM frequency feedback bandwidth is sufficientto significantly reduce the laser linewidth from its unlockedvalue of roughly 5 kHz. The fractional frequency stability ofthis laser when locked to the Fabry-Pérot cavity is 2 10 15for averaging times between 0.5 s and 10 s,21 limited bythermomechanical length fluctuations of the cavity23 ratherthan servo noise.The digital servo automatically acquires lock to the cavityupon turning the power on, and automatically relocks when aThis article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitationnew.aip.org/termsconditions. Downloaded to IP:132.163.136.61 On: Tue, 12 Jan 2016 18:58:25
123115-6D. R. Leibrandt and J. HeideckerFIG. 4. Automatic relocking of the clock laser. The digital servo analog inputand output signals are plotted as a function of time; the cavity transmissiontrace is scaled and offset by 1 V for clarity. The laser power is switchedoff between t 1 0.1 s and t 2 0.3 s. The digital servo enables the servo att 3 0.349 s when the cavity transmission crosses the threshold Vth 2 V.disturbance causes the laser to fall out of lock. Figure 4 showsthe behavior of the digital servo relock module when thelaser power is briefly switched off using an AOM. The servodetermines if the laser is locked to the cavity by checking ifthe transmitted power is greater than a threshold set in theGUI. When the laser power is switched off at t 1 0.1 s, theoutputs of the laser temperature and PZT loop filters are heldconstant and the PZT is swept with a constant slew rate and agradually increasing amplitude. The laser power is switchedback on at t 2 0.3 s. Note that the threshold is set suchthat when the 10 MHz PDH phase modulation sideband ofthe laser sweeps over the cavity resonance at 0.316 s, theservos are not engaged. Finally, at t 3 0.349 s the laser phasemodulation carrier sweeps over the cavity resonance and theloop filters are turned back on. Since the relock functionalityof the digital servo is implemented in the FPGA, it can bemuch faster than is shown here, limited only by the bandwidthand latency of the analog inputs and outputs.B. Laser frequency doubling cavity servoWe have also used the digital servo to lock the resonanceof a laser frequency doubling cavity to a laser, as shownschematically in Fig. 5. The doubling cavity implementsnonlinear frequency conversion from 534 nm to 267 nm in aBBO ( β-BaB2O2) nonlinear crystal, and is based on the oneused by Wilson et al.20 The actuator is a PZT that tunes thelength of the cavity, and the error signal is derived from thecavity reflection using the Hänsch-Couillaud (HC) method.24The 534 nm buildup light which leaks through one of thecavity mirrors is monitored by a photodiode and used forautomatic relocking, similar to that described in Sec. III A.We measure the transfer function of the doubling cavityPZT by adding a swept sine wave to the digital servo outputand recording the resulting error signal at the digital servoinput. This functionality is only partially automated: thedigital servo GUI automatically collects the data but the dataRev. Sci. Instrum. 86, 123115 (2015)FIG. 5. Block diagram depicting feedback control used to lock a laserfrequency doubling cavity to a laser. Gray paths denote electrical signal propagation, green paths denote visible laser light, and purple paths denote ultraviolet laser light. Note that the Zener diode is used to protect the piezoelectrictransducer. NOTCH: notch IIR filter; PI: proportional-integral IIR filter; LP:low-pass IIR filter; ZD: Zener diode; PZT: piezoelectric transducer; λ/4:quarter-wave plate; WP: Wollaston prism; PD: photodiode; BBO: β-BaB2O2nonlinear crystal.processing happens manually off-line. An alternative approachhas been demonstrated by Sparkes et al.2 in which the transferfunction is measured at all frequencies simultaneously usingwhite noise.Since the HC method produces an error signal which isonly linear for small deviations from the cavity resonance,we measure the transfer function while the cavity length islocked to the laser. The block diagram of the digital servocontrolling a generic single-input, single-output (SISO) plantis shown in Fig. 6(a). This can be translated into an equationfor the digitized output z as a function of the modulation m,ADGm.(1)1 ADGKIn order to determine the transfer function of the plant G(i.e., the laser frequency doubling cavity), we measure thetransfer function z/m for two different configurations of thesignal path summarized in Table II. In the first measurement(Table II, line 1), the output of the digital servo is connecteddirectly to the input of the digital servo, bypassing theplant altogether (G 1), and the loop filter is turned off(K 0). This measurement gives us the product AD, whichis the combined transfer function of the analog-to-digitalconverter and the digital-to-analog converter. In the secondmeasurement (Table II, line 3), the digital servo is connectedto the plant (G G) and the loop filter is turned on (K K).This measurement, combined with the previous measurementand a priori knowledge of the transfer function of the loopfilter K, gives us the transfer function of the plant G. Notethat if the transfer function of the loop filter were not knowna priori, it could be determined by a third measurement(Table II, line 2). The measured transfer function of thedoubling cavity PZT is shown in Fig. 6(b). Note that the1 kHz low-pass component of the PZT transfer function isdue to an electrical low-pass filter composed of the 220 Ωresistor shown in Fig. 5 and the 0.75 µF capacitance of thez This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitationnew.aip.org/termsconditions. Downloaded to IP:132.163.136.61 On: Tue, 12 Jan 2016 18:58:25
123115-7D. R. Leibrandt and J. HeideckerRev. Sci. Instrum. 86, 123115 (2015)IV. CONCLUSIONFIG. 6. (a) Block diagram illustrating use of the digital servo for measurement of the transfer function of a laser frequency doubling cavity. K:controller (IIR filter implemented in the FPGA); m: modulation (added tothe controller output for transfer function measurement); D: digital-to-analogconverter; G: plant (laser frequency doubling cavity); y: plant output; A:analog-to-digital-converter; z: discretized plant output. (b) Measured transferfunctions of the digital servo DAC and ADC (AD, blue dashed line) and thedoubling cavity PZT (G, yellow line, scaled by 26 dB for clarity), as wellas calculated transfer functions of the digital servo (K, red dash dotted line,scaled by 26 dB for clarity) and the product of all of the above transferfunctions (ADKG, thick purple line). The corner frequency of the PI filterused in the feedback transfer function is 6500 Hz.PZT, which is used to reduce the voltage noise of the digitalservo analog output at high frequencies.The doubling cavity PZT has several mechanicalresonances, with the lowest being at 25 kHz. We use a notchfilter in the feedback transfer function to suppress oscillationsat this frequency, which allows for an improved feedbackbandwidth. The transfer function ADKG shown in Fig. 6(b)has a gain margin of 2.0 and a phase margin of 45 , with afeedback bandwidth of 10 kHz. In comparison, an analog PIDfilter can only achieve a 6 kHz feedback bandwidth with thesame gain and phase margin for this doubling cavity, limitedby the requirement that the loop gain be below unity at thePZT resonance frequencies.TABLE II. Summary of measurements used to determine the transfer function of a SISO plant while feedback is applied to keep the plant near nsfer functionInferredtransfer function X AD AD X K 1 ADAD K X G 1 ADGADG KAD X AD1K X1K ADXGG AD(1 K X )GWe have described a digital servo with two analoginput channels and three analog output channels, capableof MIMO control with bandwidths up to roughly 1 MHz.Computation of the feedback transfer function takes placein a FPGA for high-speed and deterministic timing, and theservo configuration is controlled via a GUI that runs on a PC.The digital servo can implement feedback transfer functionsconsisting of up to four cascaded first- and second-order IIRfilters, which allows for loop shapes such as PIID or PIwith a notch filter, as well as automatic relocking. Diagnosticfunctionality includes a rudimentary software oscilloscopeand measurement of system transfer functions. We presentedtwo example applications of the digital servo that illustratethe above capabilities. The hardware and software design ispublic domain and available for download online,14 and othersare encouraged to try it out in their own laboratories.While the design is optimized for feedback control oflasers in AMO physics experiments, it is intended to begeneral purpose and it should be applicable to other controlapplications with similar bandwidth, noise, and loop shapere
Some of the advantages of the digital servo relative to analog servos are highlighted. SectionIVsummarizes and concludes. Finally, theAppendixpresents a detailed description of the digital filter design used in the digital servo. II. DESIGN The digital servo is comprised of a custom-built hardware box
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The PWM input wire (orange) and the feedback wire (white) for each servo will be attached to the Arduino pins as follows: Servo One - PWM - Digital 8, Feedback - Analog 1 Servo Two - PWM - Digital 9, Feedback - Analog 2 Servo Three - PWM - Digital 10, Feedback - Analog 3 Servo Four - PWM - Digital 11,
Raspberry Pi Hook up the Raspberry Pi to the servo controller, and the servos to the servo controller. Follow this servo controller tutorial (https://adafru.it/cFP) if you are unsure of the exact steps. You will want to hook up the top servo (up/down movement) to channel 0, and the bottom servo (left/right movement) to channel 1 of the servo .
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