VLSI Design Lecture PPTs
INSTITUTE OF AERONAUTICAL ENGINEERINGDundigal, Hyderabad -500 043VLSI Design Lecture PPTsDepartment:ELECTRONICS AND COMMUNICATION ENGINEERINGCourse Code:57035Course Title:VLSI DESIGNCourse Coordinator:VR. Sheshagiri Rao, ProfessorB. Kiran Kumar, Assistant ProfessorTeam of InstructorsCourse s41-4:1
Unit IIntroduction to IC technologyTopics MOS, PMOS, NMOS, CMOS and BiCMOSTechnologies: Oxidation Lithography Diffusion Ion implantation Metallization Encapsulation Probe testing Integrated Resistors and Capacitors6/3/20152
Acronym of VLSI VLSI6/3/2015- Very- Large- Scale- Integration3
Types of Field Effect Transistors(The Classification)n-Channel JFETFETp-Channel JFET» JFETMOSFET FETMOSFET (Metal-Oxide Semiconductor Field-Effect Transistor)Primary component in high-density VLSI chips such as memories and microprocessorsJFET (Junction Field-Effect Transistor)Finds application especially in analog and RF circuit design6/3/20154
Metal Oxide Semiconductor(MOS) Advantages of FET over conventional Transistors Unipolar device i. e. operation depends on only one type of charge carriers (h or e) Voltage controlled Device (gate voltage controls drain current) Very high input impedance ( 109-1012 ) Source and drain are interchangeable in most Low-frequency applications Low Voltage Low Current Operation is possible (Low-power consumption) Less Noisy as Compared to BJT No minority carrier storage (Turn off is faster) Very small in size, occupies very small space in ICs6/3/20155
Switch Model of NMOS Transistor VGS Source(of carriers)Open (off) (Gate GateDrain(of carriers)Closed (on) (Gate )Ron VGS VT 6/3/2015 VGS VT 6
Switch Model of PMOS TransistorGate VGS Source(of carriers)Open (off) (Gate Drain(of carriers))Closed (on) (Gate )Ron VGS VDD – VT 6/3/2015 VGS VDD – VT 7
MOS transistors SymbolsDDGGSNMOS EnhancementSNMOS DepletionDGPMOS Enhancement6/3/2015DGSChannelBSNMOS withBulk Contact8
MOSFET Circuit Symbols (g) and (i) are the mostcommonly used symbolsin VLSI logic design. MOS devices aresymmetric. In NMOS, n region athigher voltage is thedrain. In PMOS p region atlower voltage is the drain6/3/20159
The NMOS Transistor Cross Sectionn areas have been doped with donor ions(arsenic) of concentration ND - electrons arethe majority carriersGate oxidePolysiliconWGateSourceDrainn n Lp substrateField-Oxide(SiO2)p stopperBulk (Body)6/3/2015p areas have been doped with acceptor ions(boron) of concentration NA - holes are themajority carriers11
Carriers and Current Carriers always flow from the Source to Drain NMOS: Free electrons move from Source toDrain.– Current direction is from Drain to Source. PMOS: Free holes move from Source to Drain.– Current direction is from Source to Drain.–6/3/201512
The MOSFET Channel Under certain conditions, a thin channel canbe formed right underneath the SiliconDioxide insulating layer, electrically connectingthe Drain to the Source. The depth of thechannel (and hence its resistance) can beo t olled the Gate s oltage. The le gth ofthe channel (shown in the figures above as L)a d the ha el s idth W, a e i po ta tdesign parameters.6/3/201514
REGION OF OPERATIONCASE-1 (No Gate Voltage) Two diodes back to back exist in series. One diode is formed by the pn junctionbetween the n drain region and the p-typesubstrate Second is formed by the pn junction betweenthe n source region and the p-type substrate These diodes prevent any flow of the current. There exist a very high resistance.6/3/201515
NMos Cut View6/3/201516
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REGION OF OPERATIONCreating a channel Apply some positive voltage on the gateterminal. This positive voltage pushes the holesdownward in the substrate region. This causes the electrons to accumulate underthe gate terminal. At the same time the positive voltage on thegate also attracts the electrons from the n region to accumulate under the gate terminal.6/3/201518
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REGION OF OPERATIONCreating a channel When sufficient electrons are accumulated under thegate an n-region is created, connecting the drain andthe source This causes the current to flow from the drain tosource The channel is formed by inverting the substratesurface from p to n, thus induced channel is also calledas the inversion layer. The voltage between gate and source called vgs atwhich there are sufficient electron under the gate toform a conducting channel is called threshold voltageVth.6/3/201522
Formation of Channel First, the holes arerepelled by thepositive gate voltage,leaving behindnegative ions andforming a depletionregion. Next,electrons are attractedto the interface,creating a channeli e sio la e .6/3/201523
MOS Transistor Current direction The source terminal of an n-channel(p-channel)transistor is defined as whichever of the two terminalshas a lower(higher) voltage. When a transistor is turned ON, current flows from thedrain to source in an n-channel device and from sourceto drain in a p-channel transistor. In both cases, the actual carriers travel from the sourceto drain. The current directions are different because n-channelcarriers are negative, whereas p-channel carriers arepositive.6/3/201524
MOS I/VFor a NMOS, a necessarycondition for the channel to exist is:VGS VTH6/3/201525
REGION OF OPERATIONApplying small Vds Now we applying some small voltage betweensource and drain The voltage Vds causes a current to flow fromdrain to gate. Now as we increase the gate voltage, morecurrent will flow. Increasing the gate voltage above the thresholdvoltage enhances the channel, hence this mode iscalled as enhancement mode operation.6/3/201526
Operation – nMOS Transistor Accumulation Mode - If Vgs 0, then anelectric field is established across thesubstrate. Depletion Mode -If 0 Vgs Vtn, the regionunder gate will be depleted of charges. Inversion Mode – If Vgs Vtn, the regionbelow the gate will be inverted.6/3/201527
Operation – nMOS Transistor6/3/201528
Operation – nMOS TransistorV 06/3/201529
Operation – nMOS Transistor6/3/201530
Operation – nMOS Transistor6/3/201531
Operation – nMOS Transistor6/3/201532
Operation – nMOS Transistor6/3/201533
Voltage-Dependent Resistor The inversion channelof a MOSFET can beseen as a resistor. Since the chargedensity inside thechannel depends onthe gate voltage, thisresistance is alsovoltage-dependent.6/3/201534
Channel Potential Variation “i e the e s achannel resistancebetween drain andsource, and if drain isbiased higher thanthe source, then thepotential betweengate and channel willdecrease fromsource to drain.6/3/201535
Channel Pinch-Off As the potentialdifference between drainand gate becomes morepositive, the inversionlayer beneath theinterface starts to pinchoff around drain. When VD s VGs - Vth,the channel at draintotally pinches off, andwhen VD s VGs - Vth,the channel length startsto decrease.6/3/201536
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Transistor in Saturation ModeAssuming VGS VTVGSSGDn VDS VGS - VTVDSIDn - V -V GSTPinch-offBThe current remains constant (saturates).6/3/201540
Du i g pi hoff Does this mean that the current i 0 ? Actually, it does not. A MOSFETthat is pinched off at the drain end of the channel still conducts current: The large E in the depletion region surrounding the drain will sweepelectrons across the end of the pinched off channel to the drain. This is very similar to the operation of the BJT. For an npn BJT, the electricfield of the reversed biased CBJ swept electrons from the base to thecollector regions.6/3/201541
N-Channel MOSFET characteristics6/3/201542
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Enhancement-Mode PMOSTransistors: Structure p-type source and drainregions in n-type substrate. vGS 0 required to create ptype inversion layer in channelregion For current flow, vGS vTP To maintain reverse bias onsource-substrate and drainsubstrate junctions, vSB 0and vDB 0 Positive bulk-source potentialcauses VTP to become morenegative6/3/201545
P-channel MOSFET characteristicssaturationlinearp transistor6/3/201546
Depletion-Mode MOSFETS NMOS transistors with Ion implantation processis used to form a built-inn-type channel in thedevice to connect sourceand drain by a resistivechannel Non-zero drain current VTN 0for vGS 0; negative vGS required to turn deviceoff.6/3/201547
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pMOS are 2.5 time slower thannMOS due to electron and holemobilities6/3/201550
Basic processes involved in fabricatingMonolithic ICs1.2.3.4.5.6.7.8.9.Silicon wafer (substrate) preparationEpitaxial growthOxidationPhotolithographyDiffusionIon implantationMetallizationTestingAssembly processing & packaging6/3/201551
Oxidation Formation of silicon dioxide layer on the surface of Si wafer1. protects surface from contaminants2. forms insulating layer between conductors3. form barrier to dopants during diffusion or ion implantation4. grows above and into silicon surface Dry oxidation: lower rate and higher quality Wet oxidation: higher rate and lower quality1. SiO2 is an extremely hard protective coating & is unaffectedby almost all reagents except by hydrochloric acid. Thus itstands against any contamination.2. By selective etching of SiO2, diffusion of impurities throughcarefully defined through windows in the SiO2 can beaccomplished to fabricate various components.6/3/201552
OxidationThe silicon wafers are stacked up in a quartz boat & theninserted into quartz furnace tube. The Si wafers are raisedto a high temperature in the range of 950 to 1150oC & atthe same time, exposed to a gas containing O2 or H2O orboth. The chemical action isSi 2H2O----------- Si O2 2H2 (Wet )Si O2 ------------- SiO2(Dry )6/3/201553
Photolithography Coat wafer with photoresist(PR) Shine UV light through maskto selectively expose PR Use acid to dissolve exposedPR Now use exposed areas forUV LightMaskPhotoresistWafer– Selective doping– Selective removal of materialunder exposed PR6/3/201554
Adding Materials Add materials on top ofsilicon– Polysilicon– Metal– Oxide (SiO2) - Insulator MethodsAdded Material(e.g. Polysilicon)Silicon– Chemical deposition– Sputtering (Metal ions)– Oxidation6/3/201555
Oxide (Si02) - The Key Insulator Thin Oxide– Add using chemical deposition– Used to form gate insulator & block active areas Field Oxide (FOX) - formed by oxidation– Wet (H20 at 900oC - 1000oC) or Dry (O2 at 1200oC)– Used to insulate non-active areasSiO2 Thin OxideSilicon Wafer6/3/2015FOXSiN / SiO2 FOXSilicon Wafer56
Patterning Materials usingPhotolithography Add material to wafer Coat with photoresist Selectively removephotoresist Remove exposed material Remove remaining PR6/3/2015Added Material(e.g. Polysilicon)Silicon57
Diffusion Introduce dopant via epitaxy orion implant e.g. Arsenic (N),Boron (P) Allow dopants to diffuse at hightemperature Block diffusion in selective areasusing oxide or PR Diffusion spreads both vertically,horizontally6/3/2015Blocking Material(Oxide)DiffusionSilicon58
Ion ImplantationProcess ConditionsFlow Rate: 5 sccmPressure: 10-5 TorrAccelerating Voltage: 5to 200 keVGasesArAsH3B11F3 *HeN2PH3SiH4SiF6/3/20154Slide 59SolidsGaInSbLiquidsAl(CH3)3Neutral beamandbeam pathgatedFocus Beam trap andgate plateNeutral beam trap Y - axis X - axis Wafer in waferand beam gatescanner scanner process chamberEquipment GroundResolvingAperture180 kVAcceleration Tube90 Analyzing MagnetTerminal GroundIon Source20 kV
Metallization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wiresMetalMetalThick field oxidep n n p p n wellp substrate6/3/2015Slide 60n
nMOS fabrication steps1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which therequired p-impurities are introduced as the crystal is grown.2. A layer of silicon dioxide (Si02) is grown all over the surface of the wafer to protect the surface, act as abarrier to dopants during processing, and provide a generally insulating substrate on to which other layersmay be deposited and patterned.3. The surface is now covered with a photoresist which is deposited onto the wafer and spun to achieve aneven distribution of the required thickness.4. The photoresist layer is then exposed to ultraviolet light through a mask which defines those regions intowhich diffusion is to take place together with transistor channels.5. These areas are subsequently readily etched away together with the underlying silicon dioxide so that thewafer surface is exposed in the window defined by the mask.6. The remaining photoresist is removed and a thin layer of Si02 is grown over the entire chip surface andthen polysilicon is deposited on top of this to form the gate structure.7. Further photoresist coating and masking allows the polysilicon to be patterned (as shown in Step 6) andthen the thin oxide is removed to expose areas into which8. Thick oxide (Si02) is grown over all again and is then masked with photoresist and etched to exposeselected areas of the polysilicon gate and the drain and source areas where connections (i.e. contact cuts)are to be made.9. The whole chip then has metal (aluminium) deposited over its surface. This metal layer is then maskedand etched to form the required interconnection pattern.6/3/201561
1.Substratep2. Thick oxide(1 m)p3. Photoresistp6/3/201562
UV lightMask4. p5. Window inoxidep6/3/201563
6. PatternedPoly. (1-2 m)On thin oxidep( 800-1000A0 ) 7.n diffusion(1 m deep)p6/3/201564
. 8.Contact holes(cuts)p . p6/3/2015 9.PatternedMetallization(aluminum1 m)65
CMOS FABRICATION There are a number of approaches to CMOSfabrication, including the p-well, the n-well,the twin-tub, and the silicon-on-insulatorprocesses.6/3/201566
The p-well ProcessIn primitive terms, the structure consists of an ntype substrate in which p-devices maybe formed by suitable masking and diffusionand, in order to accommodate n-type devices,a deep p-well is diffused into the n-typesubstrate as shown.6/3/201567
The p-well CMOS fabricationIn all other respects-masking, patterning, and diffusion-the process is similar tonMOS fabrication. In summary, typical processing steps are: Mask 1 - defines the areas in which the deep p-well diffusions are to take place. Mask 2 - defines the thinox regions, namely those areas where the thick oxide isto be stripped and thin oxide grown to accommodate p- and n-transistors and wires. Mask 3 - used to pattern the polysilicon layer which is deposited after the thinoxide. Mask 4 - A p-plus mask is now used (to be in effect "Anded" with Mask 2) to defineall areas where p-diffusion is to take place. Mask 5 - This is usually performed using the negative form of the p-plus mask anddefines those areas where n-type diffusion is to take place. Mask 6 - Contact cuts are now defined. Mask 7 - The metal layer pattern is defined by this mask.Mask 8 - An overall passivation (overglass) layer is now applied and Mask 8 tsneeded to define the openings for access to bonding pads.6/3/201568
SiO21. pp-well(4-5 m)nPolysilicon2. pn6/3/2015Thin oxideandpolysilicon69
p-diffusionP mask 3. (positive)pnP maskn-diffusion(negative)4. pn6/3/201570
SpnCMOS p-well inverter showing VDD and VSS substrate connections6/3/201571
SnpCMOS n-well inverter showing VDD and VSS substrate connections6/3/201572
The n-well Process As indicated earlier, although the p-well process is widely used, n-well fabricationhas also gained wide acceptance, initially as a retrofit to nMOS lines.6/3/201573
The twin-tub-Tub ProcessA logical extension of the p-well and n-well approaches isthe twin-tub fabrication process.Here we start with a substrate of high resistivity n-typematerial and then create both . n-well and p-wellregions. Through this process it is possible to preserve theperformance of n-transistors without compromising thep-transistors. Doping control is more readily achievedand some relaxation in manufacturing tolerances results.This is particularly important as faras latch-up is concerned.6/3/201574
SEpitaxialnpwellnwelllayersubstrateTwin-tub structure( A logical extension of the p-well and n-well)6/3/201575
Bi-CMOSBipolar compatible CMOS(Bi-CMOS) technology:Introduced in early 1980sCombines Bipolar and CMOS logicLow power dissipationHigh packing densityHigh speedHigh outputdriveHigh Noise MarginHigh transconductance(gm)High input impedance6/3/201576
FeaturesThe objective of the Bi-CMOS is to combine bipolar and CMOS so as toexploit the advantages of both the technologies.Today Bi-CMOS has become one of the dominant technologies used forhigh speed, low power and highly functional VLSI circuits.The process step required for both CMOS and bipolar are almost similarThe primary approach to realize high performance Bi-CMOS devices is theaddition of bipolar process steps to a baseline CMOS process.The Bi-CMOS gates could be used as an effective way of speeding up theVLSI circuits.The applications of Bi-CMOS are vast.Advantages of bipolar and CMOS circuits can be retained in Bi-CMOSchips.Bi-CMOStechnology enables high performance integrated circuits IC’s but6/3/201577increases process complexity.
Characteristics of Bipolar TechnologyHigher switching speedHigher current drive per unit area, higher gainGenerally better noise performance and better high frequencycharacteristicsImproved I/O speed (particularly significant with the growing importanceof package limitations in high speed systems).high power dissipationlower input impedance (high drive current)low packing densitylow delay sensitivity to loadIt6/3/2015is essentially unidirectional.78
Characteristics of CMOSLower static power dissipationHigher noise marginsHigher packing densityHigh yield with large integrated complex functionsHigh input impedance (low drive current)Scalable threshold voltageHigh delay load sensitivityLow output drive current (issue when driving large capacitive loads)Bi-directional capability (drain & source are interchangeable)A near ideal switching device,Low gain6/3/201579
Bi-CMOS FABRICATION PROCESSCMOS processprocess1 . N-wellBI-POLAR1. n sub-collector2. P base doping(extrastep)3. PMOS source and drain4. NMOS source and drain6/3/20153. p base contact4. n emitter80
npn-BJT Fabrication6/3/201581
BJT Processing1. Implantation of the buried n layer2. Growth of the epitaxial layer3. p isolation diffusion4. Base p-type diffusion5. Emitter n diffusionn layerp layern layerp-base layern buried layer6. p ohmic contactp-substrate7. Contact etching8. Metal deposition and etching9. Passivation and bond pad opening6/3/201582
BJT Processing1. Implantation of the buried n layer2. Growth of the epitaxial layer3. p isolation diffusion4. Base p-type diffusion5. Emitter n diffusion6. p ohmic contact7. Contact etching8. Metal deposition and etching9. Passivation and bond pad opening6/3/2015p-substrate83
BJT Processing1. Implantation of the buried n layer2. Growth of the epitaxial layer3. p is
VLSI Design Lecture PPTs INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad -500 043 6/3/2015 1 Department : ELECTRONICS AND COMMUNICATION ENGINEERING Course Code : 57035 Course Title : VLSI DESIGN Course Coordinator : VR. Sheshagiri Rao, Professor Team of Instructors B. Kiran Kumar , Assistant Professor Course Structure :
Introduction of Chemical Reaction Engineering Introduction about Chemical Engineering 0:31:15 0:31:09. Lecture 14 Lecture 15 Lecture 16 Lecture 17 Lecture 18 Lecture 19 Lecture 20 Lecture 21 Lecture 22 Lecture 23 Lecture 24 Lecture 25 Lecture 26 Lecture 27 Lecture 28 Lecture
VL2114 RF VLSI Design 3 0 0 3 VL2115 High Speed VLSI 3 0 0 3 VL2116 Magneto-electronics 3 0 0 3 VL2117 VLSI interconnects and its design techniques 3 0 0 3 VL2118 Digital HDL Design and Verification 3 0 0 3 VL2119* Computational Aspects of VLSI 3 0 0 3 VL2120* Computational Intelligence 3 0 0 3
VLSI Design 2 Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.
VLSI IC would imply digital VLSI ICs only and whenever we want to discuss about analog or mixed signal ICs it will be mentioned explicitly. Also, in this course the terms ICs and chips would mean VLSI ICs and chips. This course is concerned with algorithms required to automate the three steps “DESIGN-VERIFICATION-TEST” for Digital VLSI ICs.
Dr. Ahmed H. Madian-VLSI 3 What is VLSI? VLSI stands for (Very Large Scale Integrated circuits) Craver Mead of Caltech pioneered the filed of VLSI in the 1970’s. Digital electronic integrated circuits could be viewed as a set
15A04604 VLSI DESIGN Course Objectives: To understand VLSI circuit design processes. To understand basic circuit concepts and designing Arithmetic Building Blocks. To have an overview of Low power VLSI. Course Outcomes: Complete Knowledge about Fabrication process of ICs Able to design VLSIcircuits as per specifications given.
55:131 Introduction to VLSI Design 10 . Simplified Sea of Gates Floorplan 55:131 Introduction to VLSI Design 11 . SoG and Gate Array Cell Layouts 55:131 Introduction to VLSI Design 12 . SoG and Gate Array 3-in NAND 55:131 Introdu
AS 8 PROTEIN SYNTHESIS QUESTIONSHEET 10 (b) (i) genetic code on DNA is copied into mRNA; double helix of DNA unwinds (in region to be copied); complementary nucleotides line up along coding strand of DNA; A to U and C to G; assemble together to make a complementary strand of mRNA; under influence of RNA polymerase; mRNA unzips from DNA template and passes to ribosomes; max 5 (ii) ATP provides .
