Digital Design With Synthesizable VHDL
Digital Design withSynthesizable VHDLProf. Stephen A. Edwardssedwards@cs.columbia.eduColumbia UniversitySpring 2008Digital Design with Synthesizable VHDL – p.
Why HDLs?1970s: SPICE transistor-level netlistsVddAn XOR built from four NAND gates.MODEL P PMOS.MODEL N NMOS.SUBCKT NAND AM1 Y A Vdd VddM2 Y B Vdd VddM3 Y A XVssM4 X B Vss Vss.ENDSX1X2X3X4AABI2BI1I1I3I1I2I3YYB Y Vdd ital Design with Synthesizable VHDL – p.
Why HDLs?1980s: Graphical schematic capture programsDigital Design with Synthesizable VHDL – p.
Why HDLs?1990s: HDLs and Logic Synthesislibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity ALU isport(A:in unsigned(1 downto 0);B:in unsigned(1 downto 0);Sel:in unsigned(1 downto 0);Res:out unsigned(1 downto 0));end ALU;architecture behv of ALU is beginprocess (A,B,Sel) begincase Sel iswhen "00" Res A B;when "01" Res A (not B) 1;when "10" Res A and B;when "11" Res A or B;when others Res "XX";end case;end process;end behv;Digital Design with Synthesizable VHDL – p.
Two Separate but Equal LanguagesVerilog and VHDLVerilog: More succinct, less flexible, really messyVHDL: Verbose, very (too?) flexible, fairly messyPart of languages people actually use identical.Every synthesis system supports both.Digital Design with Synthesizable VHDL – p.
Basic Lexical Rules of VHDLFree-form: space only separates tokens.Case-insensitive: “VHDL,” “vHdL,” and “vhdl”are equivalent.Comments: from “--” to the end of the line.Identifiers: [a-zA-Z]( ?[a-zA-Z0-9])*Examples: X X or Y ADDR addrIllegal: 14M CLK 4 FOODigital Design with Synthesizable VHDL – p.
Literals in VHDLDecimal integers : 1 42 153 1203Based integers : 2#1 0010# 16#F001D#Characters: ’0’ ’1’ ’X’Strings: "101011" "XXXXXX"Bit string literals : B"1001 0101" X"95"mean "10010101" Underscoresadded for readability are ignoredDigital Design with Synthesizable VHDL – p.
Combinational Logic in aDataflow StyleDigital Design with Synthesizable VHDL – p.
BitsLogicalTrueFalseBinary10VoltageTiming DiagramVHDL1.65–3.3V 0–1.65VHHH’1’LLL’0’In VHDL, zeros and ones on wires are membersof an enumerated type. They are not Boolean.Digital Design with Synthesizable VHDL – p.
The std logic 1164 packagepackage std logic 1164 istype std ulogic is( ’U’, -- Uninitialized’X’,’0’,-- Forcing-- ForcingUnknown0’1’,’Z’,’W’,-- Forcing 1-- High Impedance-- WeakUnknown’L’,’H’,’-’-- Weak0-- Weak1-- Don’t care);-- The std logic type allows tri-state drivers (preferred)subtype std logic is resolved std ulogic;-- Lots more.Digital Design with Synthesizable VHDL – p. 1
Boolean OperatorsThe basic ones in VHDL:aba and ba or bnot ��0’’1’’1’’1’’1’’0’aba nand ba nor ba xor ��1’’1’’1’’0’’0’’0’Digital Design with Synthesizable VHDL – p. 1
Rules of Boolean Algebra (1)-- Precedencenot a or b and c (not a) or (b and c)-- Basic relationshipsnot not a aa and ’1’ aa and ’0’ ’0’a or ’1’ ’1’a or ’0’ aa and a aa and not a ’0’a or a aa or not a ’1’a nand b not (a and b)a nor b not (a or b)a xor ’0’ aa xor ’1’ not aa xor b (not a and b) or (a and not b)Digital Design with Synthesizable VHDL – p. 1
Rules of Boolean Algebra (2)-- Commutativitya and b b and aa or b b or a-- Associativitya and (b and c) (a and b) and ca or (b or c) (a or b) or c-- Distributivitya and (b or c) a and b or a and ca or (b and c) (a or b) and (a or c)-- De Morgan’s Lawnot (a and b) not a or not bnot (a or b) not a and not bDigital Design with Synthesizable VHDL – p. 1
A Full Adder: Truth 011111carry (not a andb and(a and not b and((a anda andc) orc) orb and not c) orb andc);sum (not a and not b andc) or(not a andb and not c) or((a and not b and not c) ora andb andc);Each row represents a mintermSum-of-products form: sum of each minterm inwhich output is trueDigital Design with Synthesizable VHDL – p. 1
Simplifying Using Boolean Rulescarry (not a and b and c) or (a and not b and c) or(a and b and not c) or (a and b and c); (a and b and not c) or (a and b and c) or(not a and b and c) or (a and b and c) or(a and not b and c) or (a and b and c); (a and b) or (b and c) or (a and c);sum (not a and not b and c) or (not a and b and not c) or(a and not b and not c) or (a and b and c); (not a) and ((not b and c) or (b and not c)) ora and ((not b and not c) or (b and c)); a xor b xor c;Digital Design with Synthesizable VHDL – p. 1
Structure of a VHDL ModuleProcessPortsprocess (clk)inComponentbeginif rising edge(clk) thenincount count 1;end if;end process;ComponentoutoutinoutSignalX ’1’ when Y ’1’ and X "110" else ’0’Dataflow ExpressionDigital Design with Synthesizable VHDL – p. 1
A Full Adder in VHDLlibrary ieee; -- always neededuse ieee.std logic 1164.all; -- std logic, et al.entity full adder is -- the interfaceport(a, b, c: in std logic;sum, carry : out std logic);end full adder;abcsumcarryarchitecture imp of full adder is -- the implementationbeginsum (a xor b) xor c;-- combinational logiccarry (a and b) or (a and c) or (b and c);end imp;Digital Design with Synthesizable VHDL – p. 1
.After Logic Synthesiscarry 3bccarry 0carry 4acarrycarry 1sum 1sumDigital Design with Synthesizable VHDL – p. 1
Vectors of BitsThree standard synthesizable bit vector types:Typestd logic vectorunsignedsignedLibraryArith.ieee std 1164Logic numeric std numeric std Neg. library ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity vectors isport(vect : in std logic vector(1 downto 0);unsi : in unsigned(7 downto 0);sign : out unsigned(15 downto 0));end entity;Digital Design with Synthesizable VHDL – p. 1
EndiannessThe perpetual battle: Is “0” most or leastsignificant?Little Endian 3 2 1 0 unsigned(3 downto 0)Big Endian0 1 2 3 unsigned(0 to 3)Arguments on both sides will continue forever.I suggest using Little Endian for vectors.Digital Design with Synthesizable VHDL – p. 2
Binary and Hexadecimal in VHDLDecimal "x"D"x"E"x"F"x"10"x"11"x"12"x"13"Vector types are arrays ofstd logicLiterals are therefore stringsof 0’s and 1’s-- from std logic 1164type std logic vector isarray (natural range ) of std logic;--- from numeric stdtype unsigned isarray (natural range ) of std logic;type signed isarray (natural range ) of std logic;Digital Design with Synthesizable VHDL – p. 2
Two’s ComplementDecimal "D"x"E"x"F"x"0"x"1"x"2"x"3"x"4"x"5"x"6"x"7"How do you represent negativenumbers?Two’s complement producessimpler logic than sign bit alone.Idea: Add constant 2n tonegative numbers. Simplydiscard overflow after additionor subtraction.An n-bit number represents 2n 1 to 2n 1 1.The signed type innumeric std uses thisDigital Design with Synthesizable VHDL – p. 2
A Hex-to-seven-segment DecoderabfgecdDigital Design with Synthesizable VHDL – p. 2
VHDL: Hex-to-7-segment Decoderlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all; -- Provides the unsigned typeentity hex7seg isport ( input : in unsigned(3 downto 0); -- A numberoutput : out std logic vector(6 downto 0)); -- Just bitsend hex7seg;architecture combinational of hex7seg isbeginwith input select output "0111111" when x"0", "0000110" when x"1", -- Bad style"1011011" when x"2","1100110" when x"4","1111101" when x"6","1001111" when x"3", -- one case"1101101" when x"5", -- per line"0000111" when x"7", -- preferred"1111111" when x"8","1110111" when x"A","0111001" when x"C","1101111" when x"9","1111100" when x"B","1011110" when x"D","1111001" when x"E", "1110001" when x"F","XXXXXXX" when others;end combinational;Digital Design with Synthesizable VHDL – p. 2
Four-to-one mux: when . elselibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity multiplexer 4 1 isport(in0, in1, in2, in3 : inszend multiplexer 4 1;unsigned(15 downto 0);: in unsigned(1 downto 0);: out unsigned(15 downto 0));architecture comb of multiplexer 4 1 isbeginz in0 when s "00" elsein1 when s "01" elsein2 when s "10" elsein3 when s "11" else(others ’X’); -- Shorthand for "all X’s"end comb;Digital Design with Synthesizable VHDL – p. 2
Four-to-one mux: with.selectlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity multiplexer 4 1 isport(in0, in1, in2, in3 : ins0, s1zend multiplexer 4 1;unsigned(15 downto 0);: in std logic;: out unsigned(15 downto 0));architecture comb of multiplexer 4 1 issignal sels : unsigned(1 downto 0);beginsels s1 & s0; -- "&" is vector concatenationwith sels select -- would not resolve type if "s1 & s0" herez in0when "00",in1when "01",in2in3when "10",when "11",(others ’X’) when others;end comb;Digital Design with Synthesizable VHDL – p. 2
Three-to-eight Decoderlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity dec1 8 isport (sel : inunsigned(2 downto 0);res : out unsigned(7 downto 0));end dec1 8;architecture comb of dec1 8 isbeginres "00000001" when sel "000" else"00000010" when sel "001" else"00000100" when sel "010" else"00001000" when sel "011" else"00010000" when sel "100" else"00100000" when sel "101" else"01000000" when sel "110" else"10000000";end comb;Digital Design with Synthesizable VHDL – p. 2
Priority Encoderlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity priority isport (sel : in std logic vector(7 downto 0);code : out unsigned(2 downto 0));end priority;architecture imp of priority isbegincode "000" when sel(0) ’1’ else"001" when sel(1) ’1’ else"010" when sel(2) ’1’ else"011" when sel(3) ’1’ else"100" when sel(4) ’1’ else"101" when sel(5) ’1’ else"110" when sel(6) ’1’ else"111";end imp;Digital Design with Synthesizable VHDL – p. 2
Integer Arithmeticlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity adder isport (A, B : in unsigned(7 downto 0);CISUM: in std logic;: out unsigned(7 downto 0);CO: out std logic);end adder;architecture imp of adder issignal tmp : unsigned(8 downto 0);begintmp A B ("0" & ci); -- trick to promote ci to unsignedSUM tmp(7 downto 0);CO tmp(8);end imp;Digital Design with Synthesizable VHDL – p. 2
A Very Simple ALUlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity alu isport (A, B : in unsigned(7 downto 0);ADD : in std logic;RES : out unsigned(7 downto 0));end alu;architecture imp of alu isbeginRES A B when ADD ’1’ elseA - B;end imp;Digital Design with Synthesizable VHDL – p. 3
Arithmetic Comparisonlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity comparator isport (A, B : in unsigned(7 downto 0);GE: out std logic);end comparator;architecture imp of comparator isbeginGE ’1’ when A B else ’0’;end imp;Digital Design with Synthesizable VHDL – p. 3
Tri-state driversHow to use a pin as both an input and output.Not for internal FPGA signals.library ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity tri demo isport(addr : out unsigned(15 downto 0);-- output onlydata : inout unsigned(7 downto 0)); -- bidirectionalend tri demo;architecture rtl of tri demo issignal oe : std logic; -- output enable: control direction of datasignal d out : unsigned(7 downto 0);begindata d out when oe ’1’ else -- Drive data to chip(others ’Z’); -- Read data from external chipDigital Design with Synthesizable VHDL – p. 3end rtl;
Syntax of ExpressionsLogical operators: and or xor nand norRelational operators: / Additive operators: - & (concatenation)Multiplicative operators: * / mod remOthers: abs not ** (exponentiation)Primaries: identifierliteralname(expr to expr )name(expr downto expr )( choice ( choice ) expr )Digital Design with Synthesizable VHDL – p. 3
Summary of Dataflow ModelingConditional signal assignment (when.else)target (expr when expr else) expr ;Selected signal assignment (with.select)with expr selecttarget (expr when choice ( choice) ,) expr when choice ( choice) ;A choice is a simple expression (i.e., notlogical or comparison) or others.Note: when does not nest (i.e., it’s not an expr ).Digital Design with Synthesizable VHDL – p. 3
Hierarchy: Instantiatingcomponents (entities)Digital Design with Synthesizable VHDL – p. 3
Hierarchy: port map positional stylelibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity add2 isport (A, B : in unsigned(1 downto 0);C: out unsigned(2 downto 0));end add2;architecture imp of add2 iscomponent full adderport (a, b, c: instd logic;sum, carry : out std logic);end component;signal carry : std C(2)sumC(1)carrysumC(0)bit0 : full adder port map ( A(0), B(0), ’0’, C(0), carry );bit1 : full adder port map ( A(1), B(1), carry, C(1), C(2) );Digital Design with Synthesizable VHDL – p. 3end imp;
Hierarchy: port map by-name stylelibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity add2n isport (A, B : in unsigned(1 downto 0);C: out unsigned(2 downto 0));end add2n;architecture imp of add2n iscomponent full adderport (a, b, c: in std logic;sum, carry : out std logic);end component;signal carry : std logic;beginbit0 : full adder port map (a A(0), b B(0), c ’0’,sum C(0), carry carry);bit1 : full adder port map (a A(1), b B(1), c carry,sum C(1), carry C(2));end imp;Digital Design with Synthesizable VHDL – p. 3
Direct Instantiation (no component)library ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity add2 isport (A, B : inCend add2;unsigned(1 downto 0);: out unsigned(2 downto 0));architecture imp of add2 issignal carry : std logic;beginbit0 : entity work.full adder -- everything in "work" projectport map ( A(0), B(0), ’0’, C(0), carry );bit1 : entity work.full adderport map ( A(1), B(1), carry, C(1), C(2) );end imp;Must be compiled after full adder.vhd!Digital Design with Synthesizable VHDL – p. 3
Generate: Ripple-carry adderlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity rippleadder isport (a, b : in unsigned(3 downto 0);cin : in std logic;sum : out unsigned(3 downto 0);cout : out std logic);end rippleadder;architecture imp of rippleadder issignal c : unsigned(4 downto 0);beginc(0) cin;G1: for m in 0 to 3 generate -- expanded at compile timesum(m) a(m) xor b(m) xor c(m);c(m 1) (a(m) and b(m)) or (b(m) and c(m)) or(a(m) and c(m));end generate G1;cout c(4);end imp;Digital Design with Synthesizable VHDL – p. 3
Combinational Logic in aProcedural StyleDigital Design with Synthesizable VHDL – p. 4
ProcessesProcess: sequential code fragment invoked whensignal in sensitivity list changes.A correct, but dumb way to model an inverter:library ieee;use ieee.std logic 1164.all;entity dumb inv isport( a: in std logic; y : out std logic );end dumb inv;architecture comb of dumb inv isbeginprocess (a) -- invoked when signal a changesbeginif a ’1’ then y ’0’; else y ’1’; end if;end process;end comb;Digital Design with Synthesizable VHDL – p. 4
A 4-to-1 mux in the procedural stylelibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity pmultiplexer 4 1 isport(in0, in1, in2, in3 : ins: inzend pmultiplexer 4 1;unsigned(15 downto 0);unsigned(1 downto 0);: out unsigned(15 downto 0));architecture comb of pmultiplexer 4 1 isbeginprocess (in0, in1, in2, in3, s)beginz (others ’X’); -- defaultifs "00" then z in0; -- assignment overrides defaultelsif s "01" then z in1;elsif s "10" then z in2;elsif s "11" then z in3;end if;end process;end comb;Digital Design with Synthesizable VHDL – p. 4
A 4-to-1 mux using caselibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity cmultiplexer 4 1 isport(in0, in1, in2, in3 : ins: inunsigned(15 downto 0);unsigned(1 downto 0);z: out unsigned(15 downto 0));end cmultiplexer 4 1;architecture comb of cmultiplexer 4 1 isbeginprocess (in0, in1, in2, in3, s)begincase s iswhen "00" z in0;when "01"when "10"when "11" z in1; z in2; z in3;when others z (others ’X’);end case;end process;end comb;Digital Design with Synthesizable VHDL – p. 4
An Address Decoderlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity adecoder isport(a : in unsigned(15 downto 0);ram, rom, video, io : out std logic);end adecoder;architecture proc of adecoder isbeginprocess (a)beginram ’0’; rom ’0’; video ’0’; io ’0’;-- 0000-7FFFif a(15) ’0’ then ram ’1’;elsif a(14 downto 13) "00" then video ’1’; -- 8000-9FFFelsif a(14 downto 12) "101" then io ’1’; -- D000-DFFFelsif a(14 downto 13) "11" then rom ’1’; -- E000-FFFFend if;end process;end proc;Digital Design with Synthesizable VHDL – p. 4
Summary of Procedural Modelingnullsignal expr ;variable : expr ;if expr then stmts(elsif expr then stmts) (else stmts)?end if;case expr is(when choices stmts) end case;Note: when.else and with.select not allowedDigital Design with Synthesizable VHDL – p. 4
Sequential LogicDigital Design with Synthesizable VHDL – p. 4
Basic D Flip-Floplibrary ieee;use ieee.std logic 1164.all;entity flipflop isport (Clk, D : in std logic;Q: out std logic);end flipflop;architecture imp of flipflop isDQClkbeginprocess (Clk)-- Sensitive only to Clkbeginif rising edge(Clk) then -- Only on the rising edge of ClkQ D;end if;end process;end imp;Digital Design with Synthesizable VHDL – p. 4
Flip-Flop with Latch Enablelibrary ieee;use ieee.std logic 1164.all;entity flipflop enable isport (Clk, Reset, D, EN : inQend flipflop enable;std logic;: out std logic);architecture imp of flipflop enable isbeginprocess (Clk)beginif rising edge(Clk) thenif EN ’1’ thenQ D;end if;end if;end process;Q0D1ENClkend imp;Digital Design with Synthesizable VHDL – p. 4
Flip-Flop with Synchronous Resetlibrary ieee;use ieee.std logic 1164.all;entity flipflop reset isport (Clk, Reset, D : in std logic;Qend flipflop reset;: out std logic);architecture imp of flipflop reset isbeginprocess (Clk)beginif rising edge(Clk) thenif Reset ’1’ thenQ ’0’;elseQ D;end if;end if;end process;end imp;Digital Design with Synthesizable VHDL – p. 4
Four-bit binary counterlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity counter isport(Clk, Reset : in std logic;Q: out unsigned(3 downto 0));end counter;architecture imp of counter issignal count : unsigned(3 downto 0);beginprocess (Clk)beginif rising edge(Clk) thenif Reset ’1’ then count (others ’0’);else count count 1;end if;end if;end process;Q count;end imp;-- copy count to outputDigital Design with Synthesizable VHDL – p. 5
Eight-bit serial in/out shift registerlibrary ieee;use ieee.std logic 1164.all;entity shifter isport ( Clk, SI : in std logic;SO : out std logic);end shifter;architecture impl of shifter issignal tmp : std logic vector(7 downto 0);beginprocess (Clk)beginif rising edge(Clk) thentmp tmp(6 downto 0) & SI; -- & is concatenationend if;end process;SO tmp(7); -- Copy to outputend impl;Digital Design with Synthesizable VHDL – p. 5
Synchronous RAMlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity ram 32 4 isport (Clk, WE : inaddr: indi: instd logic; -- Clock and write enableunsigned(4 downto 0);unsigned(3 downto 0); -- Data indo: out unsigned(3 downto 0)); -- Data outend ram 32 4;architecture imp of ram 32 4 istype ram type is array(0 to 31) of unsigned(3 downto 0);signal RAM : ram type;beginprocess (Clk) beginif rising edge(Clk) thenif we ’1’ then RAM(TO INTEGER(addr)) di;do di; -- write-throughelse do RAM(TO INTEGER(addr));end if; end if;end process;Digital Design with Synthesizable VHDL – p. 5
A small ROMlibrary ieee;use ieee.std logic 1164.all;use ieee.numeric std.all;entity rom 32 4 isport (Clk, enaddrdata: in std logic;: in unsigned(3 downto 0);: out unsigned(3 downto 0));end rom 32 4;architecture imp of rom 32 4 istype rom type is array (0 to 15) of unsigned(3 downto 0);constant ROM : rom type : (X"1", X"2", X"3", X"4", X"5", X"6", X"7", X"8",X"9", X"A", X"B", X"C", X"D", X"E", X"F", X"1");beginprocess (Clk)beginif rising edge(Clk) thenif en ’1’ then data ROM(TO INTEGER(addr)); end if;end if;end process;Digital Design with Synthesizable VHDL – p. 5end imp;
Variables and Signalslibrary ieee; use ieee.std logic 1164.all;entity twoshiftreg isport(clk, si1, si2 : in std logic; so1, so2 : out std logic);end twoshiftreg;architecture imp of twoshiftreg issignal sr1 : std logic vector(1 downto 0); -- visible globallybeginprocess (clk)variable sr2 : std logic vector(1 downto 0); -- process-onlybeginif rising edge(clk) thensr1(1) si1;-- Effect seen only after next clksr1(0) sr1(1); -- Any order worksso1 sr1(0);so2 sr2(0);sr2(0) : sr2(1); -- Effect seen immediatelysr2(1) : si2;end if;end process;end imp;-- Must be in this orderDigital Design with Synthesizable VHDL – p. 5
Variables vs. SignalsPropertyScopeVariablesLocal to processSignalsVisible throughoutarchitectureAssignment Felt immediately Only visible after(e.g., in nextclock rises (i.e., prostatement)cess terminates)Lesson: use variables to hold temporary resultsand state to be hidden within a process.Otherwise, use signals.Digital Design with Synthesizable VHDL – p. 5
Constants: A VGA sync generatorlibrary ieee; use ieee.std logic 1164.all; use ieee.numeric std.all;entity sync gen isport (clk : in std logic; hs, vs : out std logic);end sync gen;architecture rtl of sync gen isconstant HTOTAL : integer : 800; constant HSYNC : integer : 96;constant VTOTAL : integer : 525; constant VSYNC : integer : 2;signal hcount, vcount : unsigned(9 downto 0);beginprocess (clk)beginif rising edge(clk) thenif hcount HTOTAL - 1 thenhcount (others ’0’); hs ’1’;if vcount VTOTAL - 1 thenvcount (others ’0’); vs ’1’;elseif vcount VSYNC then vs ’0’; end if;vcount vcount 1;end if;elseif hcount HSYNC then hs ’0’; end if;hcount hcount 1;end if;end if;Digital Design with Synthesizable VHDL – p. 5end process;end rtl;
Rocket Science: FSMsInputsOutputsCombinationalLogicPresent StateNext StateStateClockThis is a Mealy FSM: outputs may dependdirectly on inputs.Digital Design with Synthesizable VHDL – p. 5
Moore FSMsInputsCombinationalLogicPresent StateNext StateStateClockOutputsThis is a Moore FSM: outputs come from statebits.Digital Design with Synthesizable VHDL – p. 5
Coding Moore State Machineslibrary ieee; use ieee.std logic 1164.all;entity threecount isport(clk, reset, count : in std logic; at0 : out std logic);end threecount;architecture moore of threecount istype states is (ZERO, ONE, TWO); -- States encoded automaticallybeginprocess (clk)variable state : states;beginif rising edge(clk) thenif reset ’1’ then state : ZERO;else case state iswhen ZERO if count ’1’ then state : ONE; end if;when ONE if count ’1’ then state : TWO; end if;when TWO if count ’1’ then state : ZERO; end if;end case;end if;if state ZERO then at0 ’1’; else at0 ’0’; end if;end if;Digital Design with Synthesizable VHDL – p. 5end process; end moore;
Coding Mealy State Machinesarchitecture mealy of . istype states is (IDLE, STATE1, .);signal state, next state : states;beginprocess (clk) -- Sequential processbeginif rising edge(clk) then state next state; end if;end process;process (reset, state, i1, i2, . ) -- Combinational processbeginnext state state; -- Default: holdif reset ’1’ thennext state IDLE;elsecase state iswhen IDLE if i1 ’1’ thennext state STATE1;end if;when STATE1 Digital Design with Synthesizable VHDL – p. 6
The Traffic Light ControllercarscarsThis controls a traffic light atthe intersection of a busy highwayand a farm road. Normally,the highway light is green but ifa sensor detects a car on the farmroad, the highway light turns yellow then red. Thefarm road light then turns green until there are nocars or after a long timeout. Then, the farm road lightturns yellow then red, and the highway light returns togreen. The inputs to the machine are the car sensor,a short timeout signal, and a long timeout signal. Theoutputs are a timer start signal and the colors of thehighway and farm road lights.Source: Mead and Conway, Introduction to VLSI Systems, 1980, p. 85.Digital Design with Synthesizable VHDL – p. 6
FSM for the Traffic Light ControllerSC LHGCL/THYS/TS/TC: Car sensorS: Short timeoutL: Long timeoutT: Start timerFYFGC L/TSCLStHGHYFGFYHwyGYRRFarmRRGYDigital Design with Synthesizable VHDL – p. 6
Traffic Light Controller in VHDLlibrary ieee;use ieee.std logic 1164.all;entity tlc isport (clk, reset: instd logic;cars, short, long: in std logic;highway yellow, highway red : out std logic;farm yellow, farm redstart timerend tlc;: out std logic;: out std logic);architecture imp of tlc istype states is (HG, HY, FY, FG);signal state, next state : states;begin-- Sequential processprocess (clk)beginif rising edge(clk) thenstate next state;end if;end process;Digital Design with Synthesizable VHDL – p. 6
TLC in VHDL, continuedprocess (state, reset, cars, short, long)beginif reset ’1’ thenstart timer ’1’; next state HG;elsecase state iswhen HG highway yellow ’0’; highway redfarm yellow ’0’; farm redif cars ’1’ and long ’1’ thenstart timer ’1’; next stateelse start timer ’0’; next stateend if;when HY highway yellow ’1’; highway redfarm yellow ’0’; farm redif short ’1’ thenstart timer ’1’; next stateelse start timer ’0’; next stateend if; ’0’; ’1’; HY; HG; ’0’; ’1’; FG; HY;Digital Design with Synthesizable VHDL – p. 6
TLC in VHDL, concludedwhen FG highway yellow ’0’; highway redfarm yellow ’0’; farm redif cars ’0’ or long ’1’ thenstart timer ’1’; next stateelse start timer ’0’; next stateend if;when FY highway yellow ’0’; highway redfarm yellow ’1’; farm redif short ’1’ thenstart timer ’1’; next stateelse start timer ’0’; next stateend if; ’1’; ’0’; FY; FG; ’1’; ’0’; HG; FY;end case;end if;end process;end imp;Digital Design with Synthesizable VHDL – p. 6
Summary of the ThreeModeling StylesDigital Design with Synthesizable VHDL – p. 6
Three Modeling Styles: Dataflow (1)Combinational logic described by expressions-- Simple casea x and y;-- When.else selectorb ’1’ when x y else’0’;--- With.select selectorwith x selectc ’1’ when ’0’,’0’ when ’1’,’X’ when others;Digital Design with Synthesizable VHDL – p. 6
Procedural Combinational (2)Combinational logic described by statements andexpressionsprocess (x, y) -- Should be sensitive to every signal it readsbegina x and y;if x y thenb ’1’;elseb ’0’;end if;case x of’0’ c ’1’;’1’ c ’0’;others c ’X’;end case;end process;Digital Design with Synthesizable VHDL – p. 6
Three Styles: Procedural SequentialCombinational logic driving flip-flops described bystatements and expressions.process (clk) -- Sensitive only to the clockbeginif rising edge(clk) thena x and y;-- Always check for rising edgeif x y thenb ’1’;elseb ’0’;end if;case x of’0’ c ’1’;’1’ c ’0’;others c ’X’;end case;end if;end process;Digital Design with Synthesizable VHDL – p. 6
Ten Commandments of VHDLDigital Design with Synthesizable VHDL – p. 7
I: Thou Shalt Design Before CodingKnow the structure of what you aredesigning first.Draw a block diagram of the datapathUnderstand the timing (draw diagrams)Draw bubble-and-arc diagrams for FSMsOnly once you have a design should youstart coding in VHDLVHDL is only a way to ask for componentDigital Design with Synthesizable VHDL – p. 7
Block Diagram of a Character tRAM1.5KControllerVSYNCVideoShift RegisterDigital Design with Synthesizable VHDL – p. 7
Pixel-Level Load/ShiftBit VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV VVVVVVLLLL HH LLLLLLLLLLLLLLLLLLLLLLLLLL HH LL VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV VVLLLLLLLL HH LLLLLLLLLLLLLLLLLLLLLLLLLL HH LLLL HH LLLLLLLLLLLLLLLLLLLLLLLLLLVV VV VV VV VV VV VV VV VV VV VVi 1ii 1i 1ii 132i107654321Digital Design with Synthesizable VHDL – p. 7
Start-of-line DataLoad/ShiftHBLANK VV VV VV VV VV VV VV VV VV VV VVUUUU VVVVVVVVVVVVVVVVVVVVVVVVVVVVVV VVVVVVLLLL HH LLLLLLLLLLLLLLLLLLLLLLLLLL HH LLUUUUUUUU VVVVVVVVVVVVVVVVVVVVVVVVVVVVVV VVLLLLLLLL HH LLLLLLLLLLLLLLLLLLLLLLLLLL HHUUUUUUUUUUUU VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVLLLLLLLLLLLL HH LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 0148149150100Digital Design with Synthesizable VHDL – p. 7
End-of-line DataLoad/ShiftHBLANK VV VV VV VV VV VV VV VV VV VV VVVVVV VVVVVVVVVVVVVVVVVVVVVVVVVVVVVV UUUUUULLLL HH LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLVVVVVVVV VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVLLLLLLLL HH LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLVVVVVVVVVVVV VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVLLLLLLLLLLLL HH 817827978797879Digital Design with Synthesizable VHDL – p. 7
II: Thou Shalt be SynchronousOne global clockFlip-flops generate
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exposed to VHDL modeling of digital circuits, they learn the concepts and non-VHDL design of the digital circuits. Additionally, they spend two hours (or more) per week in the lab to go over the lab assignments and do the lab assignments in which VHDL and FPGAs are used from week 3 through week 10.
I CIRCUIT DESIGN 1 Introduction 1.1 About VHDL 1.2 Design Flow 1.3 EDA Tools 1.4 Translation of VHDL Code into a Circuit 1.5 Design Examples 2 Code Structure 2.1 Fundamental VHDL Units 2.2 LIBRARY Declarations 2.3 ENTITY 2.4 ARCHITECTURE 2.5 Introductory Examples 2.6 Problems 3 Data Types 3.1 Pre-Defined Data Types
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VHDL Retrospective zVHDL is an IEEE and ANSI standard for describing digital systems zCreated in 1981 for the DoD VHSIC program - First version developed by IBM, TI, and Intermetric - First release in 1985 - Standardized in 1987 and revised several times thereafter zStandard 1076, 1076.1 (VHDL-AMS), 1076.2, 1076.3 zStandard 1164, VHDL-2006 - Inherits many characteristics of ADA: Strong .
Language Reference Manual Cosponsors Design Automation Standards Committee (DASC) of the IEEE Computer Society and Automatic Test Program Generation Subcommittee of the IEEE Standards Coordinating Committee 20 (SCC 20) Approved 30 January 2000 IEEE-SA Standards Board Abstract: VHSIC Hardware Description Language (VHDL) is defined. VHDL is a .
Certifications: American Board of Radiology Academic Rank: Professor of Radiology Interests: Virtual Colonoscopy (CT Colonography), CT Enterography, Crohn’s, GI Radiology, (CT/MRI), Reduced Radiation Dose CT, Radiology Informatics Abdominal Imaging Kumaresan Sandrasegaran, M.B., Ch.B. (Division Chair) Medical School: Godfrey Huggins School of Medicine, University of Zimbabwe Residency: Leeds .
