FSQ0465RS/RB Green-Mode Fairchild Power Switch (FPS )

1.2NormalizedNormalizedThese characteristic graphs are normalized at TA 25 0.81250.80.40.40.20.2751000.0-25125Temperature [ C]0255075100125Temperature [ C]Figure 14. Burst-Mode Low Threshold Voltage(Vburl) vs. TA Figure 15. Peak Current Limit (ILIM) vs. TA 2008 Fairchild Semiconductor CorporationFSQ0465RS/RB Rev. 1.0.11001.00.650751.20.62550Figure 13. Burst-Mode High Threshold Voltage(Vburh) vs. TANormalizedNormalizedFigure 12. Shutdown Delay Current (IDELAY) vs. TA025Temperature [ C]Temperature [ C]0.0-251250.80.4501001.00.625751.20.6050Figure 11. Feedback Source Current (IFB) vs. TANormalizedNormalizedFigure 10. Blanking Time (tB) vs. TA0.0-2525Temperature [ C]Temperature [ C]www.fairchildsemi.com10FSQ0465RS/RB — Green-Mode Farichild Power Switch (FPS ) for Quasi-Resonant OperationTypical Performance Characteristics (Continued)

1.2NormalizedNormalizedThese characteristic graphs are normalized at TA 25 0.81250.80.40.40.20.2751000.0-25125Temperature [ C]0255075100125Temperature [ C]Figure 20. Sync High Threshold Voltage 2(VSH2) vs. TAFigure 21. Sync Low Threshold Voltage 2(VSL2) vs. TA 2008 Fairchild Semiconductor CorporationFSQ0465RS/RB Rev. 1.0.11001.00.650751.20.62550Figure 19. Over-Voltage Protection (VOV) vs. TANormalizedNormalizedFigure 18. Shutdown Feedback Voltage (VSD) vs. TA025Temperature [ C]Temperature [ C]0.0-251250.80.4501001.00.625751.20.6050Figure 17. Sync Low Threshold Voltage 1(VSL1) vs. TANormalizedNormalizedFigure 16. Sync High Threshold Voltage 1(VSH1) vs. TA0.0-2525Temperature [ C]Temperature [ C]www.fairchildsemi.com11FSQ0465RS/RB — Green-Mode Farichild Power Switch (FPS ) for Quasi-Resonant OperationTypical Performance Characteristics (Continued)

2.1 Pulse-by-Pulse Current Limit: Because currentmode control is employed, the peak current through theSenseFET is limited by the inverting input of PWMcomparator (VFB*), as shown in Figure 23. Assumingthat the 0.9mA current source flows only through theinternal resistor (3R R 2.8k), the cathode voltage ofdiode D2 is about 2.5V. Since D1 is blocked when thefeedback voltage (VFB) exceeds 2.5V, the maximumvoltage of the cathode of D2 is clamped at this voltage,clamping VFB*. Therefore, the peak value of the currentthrough the SenseFET is limited.1. Startup: At startup, an internal high-voltage currentsource supplies the internal bias and charges theexternal capacitor (Ca) connected to the VCC pin, asillustrated in Figure 22. When VCC reaches 12V, theFPS begins switching and the internal high-voltagecurrent source is disabled. The FPS continues its normalswitching operation and the power is supplied from theauxiliary transformer winding unless VCC goes below thestop voltage of 8V.VDC2.2 Leading-Edge Blanking (LEB): At the instant theinternal SenseFET is turned on, a high-current spikeusually occurs through the SenseFET, caused byprimary-side capacitance and secondary-side rectifierreverse recovery. Excessive voltage across the Rsenseresistor would lead to incorrect feedback operation in thecurrent-mode PWM control. To counter this effect, theFPS employs a leading-edge blanking (LEB) circuit. Thiscircuit inhibits the PWM comparator for a short time(tLEB) after the SenseFET is turned on Pulse-WidthModulation (PWM) CircuitCVCCVCC3VSTR6IstartVREF8V/12VVcc goodInternalBias3. Synchronization: The FSQ-series employs a quasiresonant switching technique to minimize the switchingnoise and loss. The basic waveforms of the quasiresonant converter are shown in Figure 25. To minimizethe MOSFET's switching loss, the MOSFET should beturned on when the drain voltage reaches its minimumvalue, which is indirectly detected by monitoring the VCCwinding voltage, as shown in Figure 24.FSQ0465 Rev.00Figure 22. Startup Circuit2. Feedback Control: FPS employs current-modecontrol, as shown in Figure 23. An opto-coupler (such asthe FOD817A) and shunt regulator (such as the KA431)are typically used to implement the feedback network.Comparing the feedback voltage with the voltage acrossthe Rsense resistor makes it possible to control theswitching duty cycle. When the reference pin voltage ofthe shunt regulator exceeds the internal referencevoltage of 2.5V, the opto-coupler LED current increases,pulling down the feedback voltage and reducing the dutycycle. This typically happens when the input voltage isincreased or the output load is decreased.VdsV ROVROV DCTFVsyncV ovp (8V)VCCVREFIdelayVFBVOIFB4H11A817AD2 VFB*KA4311.2VSenseFETOSCD1CB1.0V3R230ns DelayGatedriverRMOSFET Gate-VSDOLPONRsenseONFSQ0465 Rev.00FSQ0465 Rev.00Figure 24. Quasi-Resonant Switching WaveformsFigure 23. Pulse-Width-Modulation (PWM) Circuit 2008 Fairchild Semiconductor CorporationFSQ0465RS/RB Rev. 1.0.1www.fairchildsemi.com12FSQ0465RS/RB — Green-Mode Farichild Power Switch (FPS ) for Quasi-Resonant OperationFunctional Description

ID SI DSingnore4.4VV syncFS Q 0465 R ev.00Figure 27. After Vsync Finds First Valley4. Protection Circuits: The FSQ-series has severalself-protective functions, such as Overload Protection(OLP), Abnormal Over-Current Protection (AOCP),Over-Voltage Protection (OVP), and Thermal Shutdown(TSD). All the protections are implemented as autorestart mode. Once the fault condition is detected,switching is terminated and the SenseFET remains off.This causes VCC to fall. When VCC falls down to theUnder-Voltage Lockout (UVLO) stop voltage of 8V, theprotection is reset and the startup circuit charges theVCC capacitor. When the VCC reaches the start voltageof 12V, normal operation resumes. If the fault condition isnot removed, the SenseFET remains off and VCC dropsto stop voltage again. In this manner, the auto-restart canalternately enable and disable the switching of the powerSenseFET until the fault condition is eliminated.Because these protection circuits are fully integrated intothe IC without external components, reliability isimproved without increasing cost.V DS4.4VV sync1.2V1.0VFSQ 0465 Rev.00internal delayFigure 25. Vsync 4.4V at tXtXIDS1.2V1.0Vinternal delayI DStB 15µsI DSV DStXt B 15µstXt B 15µsIDSV DSPoweronFaultoccursFaultrem ovedVDSVsync4.4VV CC1.2V1.0V12V8VFSQ0465 Rev.00internal delaytFigure 26. Vsync 4.4V at tXFSQ0465 Rev.00Norm aloperationFaultsituationNorm aloperationFigure 28. Auto Restart Protection Waveforms 2008 Fairchild Semiconductor CorporationFSQ0465RS/RB Rev. 1.0.1www.fairchildsemi.com13FSQ0465RS/RB — Green-Mode Farichild Power Switch (FPS ) for Quasi-Resonant OperationThe switching frequency is the combination of blank time(tB) and detection time window (tW). In case of a heavyload, the sync voltage remains flat after tB and waits forvalley detection during tW. This leads to a low switchingfrequency not suitable for heavy loads. To correct thisdrawback, additional timing is used. The timingconditions are described in Figures 25, 26, and 27. Whenthe Vsync remains flat higher than 4.4V at the end of tBwhich is instant tX, the next switching cycle starts afterinternal delay time from tX. In the second case, the nextswitching occurs on the valley when the Vsync goes below4.4V within tB. Once Vsync detects the first valley in tB, theother switching cycle follows classical QRC operation.

3RLEB200nsSQRQGatedriverRRsense2GND AOCP-FSQ0465 Rev.00VOCPFigure 30. Abnormal Over-Current Protection4.3 Output-Short Protection (OSP): If the output isshorted, steep current with extremely high di/dt can flowthrough the SenseFET during the LEB time. Such asteep current brings high voltage stress on the drain ofSenseFET when turned off. To protect the device fromsuch an abnormal condition, OSP is included in the FSQseries. It is comprised of detecting VFB and SenseFETturn-on time. When the VFB is higher than 2V and theSenseFET turn-on time is lower than 1.2µs, the FPSrecognizes this condition as an abnormal error and shutsdown PWM switching until VCC reaches Vstart again. Anabnormal condition output short is shown in Figure 31.RectifierDiodeCurrentMOSFETDrainCurrentF S Q 0 4 6 5 R e v .0 0V FBOSCPWMTurn-off delayILIMO ve rlo a d p ro te c tio nVFB6 .0 V0Minimum turn-on timeVo2 .5 VD1.2µsoutput short occurst 1 2 C fb *(6 .0 -2 .5 )/I d e la yT10T2IotFSQ0465 Rev. 00Figure 29. Overload Protection0Figure 31. Output Short Waveforms4.2 Abnormal Over-Current Protection (AOCP): Whenthe secondary rectifier diodes or the transformer pins areshorted, a steep current with extremely high di/dt canflow through the SenseFET during the LEB time. Eventhough the FSQ-series has overload protection, it is notenough to protect the FSQ-series in that abnormal case,since severe current stress is imposed on the SenseFETuntil OLP triggers. The FSQ-series has an internalAOCP circuit shown in Figure 30. When the gate turn-onsignal is applied to the power SenseFET, the AOCPblock is enabled and monitors the current through thesensing resistor. The voltage across the resistor iscompared with a preset AOCP level. If the sensingresistor voltage is greater than the AOCP level, the setsignal is applied to the latch, resulting in the shutdown ofthe SMPS.4.4 Over-Voltage Protection (OVP): If the secondaryside feedback circuit malfunctions or a solder defectcauses an opening in the feedback path, the currentthrough the opto-coupler transistor becomes almostzero. Then, Vfb climbs up in a similar manner to theoverload situation, forcing the preset maximum currentto be supplied to the SMPS until overload protection isactivated. Because more energy than required isprovided to the output, the output voltage may exceedthe rated voltage before overload protection is activated,resulting in the breakdown of the devices in thesecondary side. To prevent this situation, an over-voltageprotection (OVP) circuit is employed. In general, VCC isproportional to the output voltage and the FSQ-seriesuses VCC instead of directly monitoring the outputvoltage. If VCC exceeds 19V, an OVP circuit is activated, 2008 Fairchild Semiconductor CorporationFSQ0465RS/RB Rev. 1.0.1www.fairchildsemi.com14FSQ0465RS/RB — Green-Mode Farichild Power Switch (FPS ) for Quasi-Resonant Operation4.1 Overload Protection (OLP): Overload is defined asthe load current exceeding its normal level due to anunexpected abnormal event. In this situation, theprotection circuit should trigger to protect the SMPS.However, even when the SMPS is in the normaloperation, the overload protection circuit can betriggered during the load transition. To avoid thisundesired operation, the overload protection circuit isdesigned to trigger only after a specified time todetermine whether it is a transient situation or a trueoverload situation. Because of the pulse-by-pulsecurrent limit capability, the maximum peak currentthrough the SenseFET is limited, and therefore themaximum input power is restricted with a given inputvoltage. If the output consumes more than this maximumpower, the output voltage (VO) decreases below the setvoltage. This reduces the current through the optocoupler LED, which also reduces the opto-couplertransistor current, thus increasing the feedback voltage(VFB). If VFB exceeds 2.5V, D1 is blocked and the 5µAcurrent source starts to charge CB slowly up to VCC. Inthis condition, VFB continues increasing until it reaches6V, when the switching operation is terminated, asshown in Figure 29. The delay time for shutdown is thetime required to charge CFB from 2.5V to 6V with 5µA. A20 50ms delay time is typical for most applications.

VOVosetVFB4.5 Thermal Shutdown with Hysteresis (TSD): TheSenseFET and the control IC are built in one package.This enables the control IC to detect the abnormally hightemperature of the SenseFET. If the temperatureexceeds approximately 140 C, the thermal shutdowntriggers IC shutdown. The IC recovers its operation whenthe junction temperature decreases 60 C from TSDtemperature and VCC reaches startup voltage (Vstart).0.55V0.35VIDS5. Soft-Start: The FPS has an internal soft-start circuitthat increases PWM comparator inverting input voltagewith the SenseFET current slowly after it starts up. Thetypical soft-start time is 17.5ms. The pulse width to thepower switching device is progressively increased toestablish the correct working conditions for transformers,inductors, and capacitors. The voltage on the outputcapacitors is progressively increased with the intention ofsmoothly establishing the required output voltage. Thismode helps prevent transformer saturation and reducesstress on the secondary diode during dt4Figure 32. Waveforms of Burst Operation7. Switching Frequency Limit: To minimize switchingloss and Electromagnetic Interference (EMI), theMOSFET turns on when the drain voltage reaches itsminimum value in quasi-resonant operation. However,this causes switching frequency to increases at light loadconditions. As the load decreases or input voltageincreases, the peak drain current diminishes and theswitching frequency increases. This results in severeswitching losses at light-load condition, as well asintermittent switching and audible noise. These problemscreate limitations for the quasi-resonant convertertopology in a wide range of applications.6. Burst Operation: To minimize power dissipation instandby mode, the FPS enters burst-mode operation. Asthe load decreases, the feedback voltage decreases. Asshown in Figure 32, the device automatically entersburst-mode when the feedback voltage drops belowVBURL (350mV). At this point, switching stops and theoutput voltages start to drop at a rate dependent onstandby current load. This causes the feedback voltageto rise. Once it passes VBURH (550mV), switchingresumes. The feedback voltage then falls and theprocess repeats. Burst-mode operation alternatelyenables and disables switching of the power SenseFET,thereby reducing switching loss in standby mode.To overcome these problems, FSQ-series employs afrequency-limit function, as shown in Figures 33 andFigure 34. Once the SenseFET is turned on, the nextturn-on is prohibited during the blanking time (tB). Afterthe blanking time, the controller finds the valley withinthe detection time window (tW) and turns on theMOSFET, as shown in Figures 33 and Figure 34 (CasesA, B, and C). If no valley is found during tW, the internalSenseFET is forced to turn on at the end of tW (Case D).Therefore, the devices have a minimum switchingfrequency of 48kHz and a maximum switching frequencyof 67kHz. 2008 Fairchild Semiconductor CorporationFSQ0465RS/RB Rev. 1.0.1timeFSQ0465 Rev. 00www.fairchildsemi.com15FSQ0465RS/RB — Green-Mode Farichild Power Switch (FPS ) for Quasi-Resonant Operationresulting in the termination of the switching operation. Toavoid undesired activation of OVP during normaloperation, VCC should be designed below 19V.

IDSIDSAVDStB 15μstsIDSInternally, quasi-resonant operation is divided into twocategories; one is first-valley switching and the other issecond-valley switching after blanking time. In AVS, twosuccessive occurrences of first-valley switching and theother two successive occurrences of second-valleyswitching is alternatively selected to maximize frequencymodulation. As depicted in Figure 34, the switchingfrequency hops when the input voltage is high. Theinternal timing diagram of AVS is described in Figure 35.IDSBtB 15μsVDStsIDSIDSfsCVDS115μs117 μsAssume the resonant period is 2 μ s67kHz59kHztB 15μs53kHz48kHzts119 μsAVS trigger pointConstantfrequencyCCMIDSIDS121μsVariable frequency within limited rangeDCMAVS regionVDStB 15μstW 6μsDDCBAVINFSQ0465 Rev.00tsmax 21μsFSQ0465 Rev. 00Figure 34. Switching Frequency RangeFigure 33. QRC Operation with Limited eX2triggering1st or 2nd is depend on GateX2tBVgate continued 2 pulsesVgate continued another 2 pulses1st valley switching2nd valley switchingfixedfixedfixedVDSVgate continued 2 pulsesfixedde-triggering triggeringtB1st valley switchingtBGateX2: Counting Vgate every 2 pulses independent on other signals .fixedfixed1st or 2nd is dependent on GateX2tBtBtB1st valley- 2nd valley frequency modulation.Modulation frequency is approximately 17kHz.FSQ0465 Rev. 00Figure 35. Alternating Valley Switching (AVS) 2008 Fairchild Semiconductor CorporationFSQ0465RS/RB Rev. 1.0.1www.fairchildsemi.com16FSQ0465RS/RB — Green-Mode Farichild Power Switch (FPS ) for Quasi-Resonant Operation8. AVS (Alternating Valley Switching): Due to thequasi-resonant operation with limited frequency, theswitching frequency varies depending on input voltage,load transition, and so on. At high input voltage, theswitching on time is relatively small compared to lowinput voltage. The input voltage variance is small and theswitching frequency modulation width becomes small. Toimprove the EMI performance, AVS is enabled wheninput voltage is high and the switching on time is small.tsmax 21μs

Due to the combined scheme, FPS shows better noiseimmunity than conventional PWM controller andMOSFET discrete solutions. Furthermore, internal draincurrent sense eliminates noise generation caused by asensing resistor. There are some recommendations forPCB layout to enhance noise immunity and suppress thenoise inevitable in power-handling components.There are typically two grounds in the conventionalSMPS: power ground and signal ground. The powerground is the ground for primary input voltage andpower, while the

FSQ0465RS/RB Š Green-Mode Fa richild Power Switch (FPSŽ) for Quasi-Resonant Operation FSQ0465RS/RB Rev. 1.0.1 December 2009 FSQ0465RS/RB Green-Mode Fairchild Power Switch (FPSŽ) for Quasi-Resonant Operation - Low EMI and High Efficiency Features! Optimized for Quasi-Resonant Converters (QRC)! Low EMI through Variable Frequency Control and AVS