Semiconductor Roadmap And Bioelectronics
Semiconductor Roadmapand BioelectronicsDr. Ralph CavinSemiconductor Research CorporationBioelectronics Roundtable * November 4, 2008
Outline International Technology Roadmap for Semiconductors (ITRS) ITRS Emerging Research Devices (ERD) Chapter– Lessons from Nanoelectronics roadmap ERD chapter Roadmapping for Bioelectronics?– Can we use some ITRS methodology?Bioelectronics Roundtable * November 4, 2008
International Technology Roadmapfor Semiconductors (ITRS) A very detailed industrial perspective on the future requirementsfor micro/nano electronic technologies– Goal is to continue exponential gains in performance & price for the nextfifteen years Built on worldwide consensus of leading industrial, government,and academic technologists Provides guidance for the semiconductor industry and foracademic research worldwideBioelectronics Roundtable * November 4, 2008
International Technology Roadmapfor Semiconductors (ITRS) Contains critical requirements and judgment of status Projects that by 2020, half-pitch spacing of metal lines will be 14nanometers and device gate lengths will be 5 nanometers vs.today’s commercially produced 45-nm lines and 25-nm gatelengths. Major update every two yearsBioelectronics Roundtable * November 4, 2008
ITRS Origins 1983-1994: SRC announces ten year research goals 1990: SRC leads in establishing NACS resulting in MICRO TECH2000 expert meeting; precursor to ITRS 1992: National Technology Roadmap for Semiconductors (NTRS)effort led by SRC and SIA defines industry five-yeargoals 1994: NTRS updated and horizon extended to 15 years 1998: Roadmap is internationalized and becomes theInternational Roadmap for Semiconductors (ITRS)Bioelectronics Roundtable * November 4, 2008
Chapters of ITRS 2007http://public.itrs.netGlossaryChapters on: Interconnect, Design, ESH, Front-EndProcesses, Process Integration and Device Structures,Metrology, Modeling, Factory Integration, yieldEnhancement, Assembly, Test, Emerging ResearchDevices, Emerging Research MaterialsSystem DriversDifficult ChallengesGrand ChallengesIntroductionBioelectronics Roundtable * November 4, 2008
Table Color SchemeSolutions ExistWhiteSolutions Being PursuedYellowNo Known SolutionsRedBioelectronics Roundtable * November 4, 2008
CMOS Scaling Challenges (2001)Table 2a High Performance Logic Technology Requirements—2001 ITRSCALENDAR NM22NMTECHNOLOGY NODE130NMMPU GATE e Dielectric Equivalent OxideThickness (EOT) (nm) [1]Electrical Thickness AdjustmentFactor(Gate Depletion andQuantum Effects) (nm) [2]Tox Electrical Equivalent (nm) [3]Vdd (V) [4]Sub-Threshold I-off @25 C(uA/um) [5]926Id-NMOS @Vdd (uA/um) [6]0%Required "TechnologyImprovement" (SOI/LowTemp/High-mobility) [7]16%Rsd Percent of Ideal ChannelResistance (Vdd/IdNMOS with noRSD) [8]Parasitic Capacitance Percent of 19%Cgate [9]Intrinsic Frequency (1/Tau) (GHz) 624[10]1.0Relative Device Performance[11]Relative Device Switching Energy 1.0[12]90NM2007Bioelectronics Roundtable * November 4, 2008
History of ERD RoadmapDevelopment Began in 2000– Initial list of candidates – 3 pages Challenge:–––––Huge constellation of ideas, concept, prototypes etcDifferent maturity levelsDifferent application time scalesDifferent operating principlesLittle quantization initially Approach:– Taxonomy building– Quantitative assessments– Progress monitoringBioelectronics Roundtable * November 4, 2008Forms the basis for comprehensiveselection and evaluation
2001 Emerging Research LogicDevicesDeviceResonantSingle ElectronTunneling DiodeTransistor- Rapid SingleQuantum FluxLogicDemonstratedHigh TcSilicon, MetalLow TcislandsSuperconductorsAdvantagesDensity,Density, Power,Performance, RFFunctionNew device &system. Roomtemp operationChallengesmatching ofquestionable.deviceNoise (offsetproperties across charge), lack ofwaferdrive currentBallistic DevicesNanotubeDevicesMolecular ronic QCAMagnetic QCA3-terminalFETQuantum CellularAutomataIdentity ofindividual switches(e.g. size,properties) on subTHz operation,nm level. Potentialmight allowsolution toanalog and digitalinterconnectoperationDensity, PowerproblemHigh Speed(GHz),High functionalPotentiallydensity, norobustinterconnectsLowtemperaturesNew device andThermal andrequired (evensystem, difficult environmentalwith high Tc),Impedanceroute forstability; twofabrication ofLimited fan out,matching,fabricatingterminal devices;complex, dense low temperature, operation at roomcomplexneed for ecturesThe time horizon for entries increases from left to right in this tableBioelectronics Roundtable * November 4, 2008Work in progress, not for publication
2003 Emerging Research icesRSFQCell Size100 nm0.3 µm100 nm100 nm40 nmNotknown60 nm100 nmDensity(cm-2)3E91E63E93E96E101E123E103E9700 GHz1.2 THzNotknown1 THz1 GHzNotknownCircuit Speed 30 GHz250–800 GHz30 GHz30 GHz1 GHz 1 MHz2 10–18 2 10–18 1.5 10–17868610Switch SpeedSwitching2 10–18 1.4 10–17Energy, JBinary0.4Throughput, 862GBit/ns/cmBioelectronics Roundtable * November 4, 2008SETMolecular QCASpintransistorFET30 MHz 700 GHz1 MHz1.3 10–16 1 10–18N/A0.0630 GHz2 10–1886
2005 Emerging Research LogicDevicesDeviceMin. requiredFET [B]1D structuresResonantTunneling DevicesSETMolecularFerromagneticSpin transistorlogicCNT FETBest projectedCrossbar latchNW FETSi CMOSTypesNW lecular QCACrossbarnanostructureDemonstratedSupported ArchitecturesConventionalConventionaland Cross-barConventionaland CNNCNNCross-bar andQCAMoving domainwallSpin transistorM: QCACNNReconfigurelogic andQCAConventionalCell Size(spatial pitch)Projected100 nm100 nm [C]100 nm [C]40 nm [L]10 nm [Q]140 nm [U]100 nm [C]Demonstrated590 nm 1.5 m [D]3µm [H] 700 nm [M] 2 m [R]250 nm [V, W]100 m [X]Density2(device/cm ed2.8E84E71E72E82E71.6E91E4Projected12 THz6.3 THz [E]16 THz [I]10 THz [M]1 THz [S]1 GHz [U]40 GHz [Y]Demonstrated1 THz200 MHz [F]700 GHz [J]2 THz [N]100 Hz [R]30 Hz [V, W]Not knownProjected61 GHz61 GHz [C]61 GHz [C]1 GHz [L]1 GHz [Q]10 MHz [U]Not knownDemonstrated5.6 GHz220 Hz [G]10 GHz [Z]1 MHz [F]100 Hz [R]30 Hz [V]Not known5E-17 [T] 1E-17 [V]3E-183E-7 [R]6E-18 [W]Not knownSwitch SpeedCircuit SpeedSwitchingEnergy, JBinaryThroughput,2GBit/ns/cm1 10–18[L]Projected3E-183E-18 3E-18Demonstrated1E-161E-11 [G]1E-13 [K]Projected238238 [C]238 [C]1010005E-2Not knownDemonstrated1.61E-80.12E-42E-95E-8Not knownRTRT4.2 – 300 K20 K [L]RTRTRTSiCNT,Si, Ge, III-V,In2O3, ZnO, neticalloysSi, III-V,complexmetals oxidesOperational TemperatureMaterials SystemBioelectronics Roundtable * November 4, 2008–17] [O][ 1.5 108 10–17[P]–14[ 1.3 10] [O]
Bioelectronics Roundtable * November 4, 2008
Bioelectronics Roadmap? Can we develop a process for a Bioelectronics Roadmap?– ITRS methodology might be helpful Procedure:– Selection– Categorization/Taxonomy– Assessment Need to be as quantitative as possible Initial Selection/Categorization exercise– Based on the input from BERT participantsBioelectronics Roundtable * November 4, 2008Minimum RequiredBest ProjectedDemonstrated
Proteinproduced incellsNon-selectiveconcentrationmeasurementsLive or deadcells?MEMSSingle biomolecule detectione.g. in Lab-on-ChipEnvironmentbioFETPD ArraysICAction potentialin live cellsBioelectronics Roundtable * November 4, 2008Cross-cut Research
Selected Cross-Cut Research Needs Immune system reaction to bio-electronic implants Stimulated adhesion of cells to the sensing surface Mechanical stimulation/response of cells Bioelectromagnetics What else?Bioelectronics Roundtable * November 4, 2008
Proteinproduced incellsNon-selectiveconcentrationmeasurementsLive or deadcells?MEMSSingle biomolecule detectione.g. in Lab-on-ChipEnvironmentbioFETPD ArraysICAction potentialin live cellsBioelectronics Roundtable * November 4, 2008
Semiconductor Roadmap and Bioelectronics Dr. Ralph Cavin Semiconductor Research Corporation. Bioelectronics Roundtable * November 4, 2008 International Technology Roadmap for Semiconductors (ITRS) ITRS Emerging Research Devices (ERD) Chapter –Lessons from Nanoelectronics roadmap
ADEKA SUPER TEOS PRODUCT NAME Si(OC 2H5)4 CHEMICAL FORMULA APPLICATION Dielectric film/Semiconductor ADEKA HIGH-PURITY TEOP PO(OC 2H5)3 Dopant/Semiconductor ADEKA HIGH-PURITY TEB B(OC 2H5)3 Dopant/Semiconductor ADEKA HIGH-PURITY TiCl4 TiCl4 Electrode/Semiconductor ADEKA SUPER TMA Al(CH 3)3 High-k material/Semiconductor ADEKA ORCERA TDMAH Hf[N(CH 3)2]4 High-k material/Semiconductor
AUK Semiconductor Corp. Aura Vision Aureal Aurora Systems Austin Semiconductor Austria Mikro Systeme International Avance Logic Avantek Averlogic . Performance Semiconductor Pericom Semiconductor PhaseLink Laboratories Philips Photobit PLX Technology PMC-Sierra Power A
However, the semiconductor body can alternatively be of Si or of a high-bandgap com-pound semiconductor material like Ga 2O3 or GaN. [0019] According to atl east one embodiment, the pow-er semiconductor device is a field-effect transistor or an insulated gate bipolar transistor, IGBT for short. For ex-ample, the power semiconductor device .
5. Biological pathways for semiconductor fabrication and integration. To develop a comprehensive Technology Roadmap for SemiSynBio, joint efforts of experts from different disciplines have been employed: biology, chemistry, computer science, electrical engineering, materials science, medicine, physics, and semiconductor technology.
What is the Semiconductor Roadmap? Something you need to read ! Enabling mechanism for Moore's Law Synchronizes many industries to "clock" of technology nodes A Very Big Picture ! Lithography, Interconnect, Assembly and Packaging, Test, Design, Technology roadmap (not business roadmap) Structured as requirements potential
Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous
The Roadmap will evolve to meet the HIT Modernization Program needs. The Roadmap is a launching point for IHS HIT modernization. The Roadmap is to be referenced and updated on a regular basis as information is gained and funding is acquired. To facilitate growth and evolution of the Roadmap
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