Lecture 15: RTL Design CSE 140: Components And Design .
Lecture 15:RTL DesignCSE 140: Components and Design Techniques forDigital SystemsDiba MirzaDept. of Computer Science and EngineeringUniversity of California, San DiegoDigital Design 2eCopyright 2010Frank Vahid1
Design the datapth (2A)sInputs: c (bit), a (8 bits), s (8 bits)Outputs: d (bit) // '1' dispenses sodaLocal storage: tot (8 bits)cInitd: '0'tot: 0WaitAddldclr8c'*(tot s)c’*(tot s)’tot lt sd: '1'tot8tot: tot aDispSodaDispensertot ldtot clra8-bit Datapath88-bitadder8Step 2ADigital Design 2eCopyright 2010Frank VahidQ: According to the current design, under which of the following conditionsdoes the register output ‘tot’ change?A.Whenever the value of the coin inserted (‘a’) changesB.Whenever the cost of the soda (‘s’) changesC.When the signal tot ld becomes highD.When the signal tot clr becomes highE.Both C and D2
Connect data path to controller(2B)s8as8tot ldtot clrcldclra8tot clrtot lt sControllertot lt sStep 2Btot8tot lddaDatapath8-bit Datapath88-bitadder8Step 2AaDigital Design 2eCopyright 2010Frank Vahid3
Design control path FSMsInputs: c (bit), a (8 bits), s (8 bits)Outputs: d (bit) // '1' dispenses sodaLocal storage: tot (8 bits)d: '0'tot: 08tot lddtot clrAddWaitaccInit8Controllertot: tot ac'*(tot s)tot lt sDatapathStep 2Bc’*(tot s)’DispSodaDispenserInputs: c, tot lt s (bit)Outputs: d, tot ld, tot clr (bit)d: '1'Step 1ctot ldcdInitd 0tot clr 1WaitAddtot clrtot ld 1tot lt sc' *c *tot lt stot lt s’DispControllerDigital Design 2eCopyright 2010Frank Vahidd 1Step 2C4
Implement controller FSMInputs: c, tot lt s (bit)Outputs: d, tot ld, tot clr 0001000000110101Add101Disp0d000c0011Inittot clr1n0111s0000Waittot ldtot lt s0n1000s100001000tot ldcdInitWaitd 0tot clr 1c *tot lt s ControllerAddtot clrtot ld 1tot lt sc *tot lt sDispd 1Step 2CUse controller (FSM) designprocess from previous lectures tocomplete the designaDigital Design 2eCopyright 2010Frank Vahid5
RTL Design Process—Step 2A: Create a datapath Need component library from which to chooseclr Ild regQABaddSABcmplt eq gtclk and clr 1: Q 0clk and ld 1: Q Ielse Q stays sameS A B(unsigned)A B: lt 1A B: eq 1A B: gt 1Digital Design 2eCopyright 2010Frank VahidIshift L/R QshiftL1: 1shiftL2: 2shiftR1: 1.I1 I0mux2x1s0 Qs0 0: Q I0s0 1: Q I16
Step 2A: Create a Datapath—Simple ExamplesXYZXXYZXk 0: Preg Y Zk 1: Preg X YkPreg X Y ZPreg Preg XPregPregPregregQPregPPPQP(a)XY(b)ZDPDPclr Ild PregQPDigital Design 2eCopyright 2010Frank VahidYZABadd1SABadd2S0 clr I1 ld PregQ0 clr I1 ld regQQPQXABadd1S01(d)YZABadd1SABadd2SXDPX Y01(c)XABadd1SABadd2SX Y ZPreg X Y; regQ Y ZZYclr Ild PregQPI1 I0mux2x1s0 QkaDP0 clr I1 ld PregQP7
5.4More RTL Design Additional datapath components(signed)ABsubSS A-B(signed)Digital Design 2eCopyright 2010Frank VahidABmulPAabsQP A*BQ A (unsigned) (unsigned)clrinc upcntQclk and clr 1: Q 0clk and inc 1: Q Q 1else Q stays sameW dW aclk and W e 1:W eRF[W a] W dRF R e 1:R aR eR d RF[R a]R d8
Summary– Modern digital design involves creating processor-level components– High-level state machines– RTL design process 1. Capture behavior: Use HLSM 2. Convert to circuit– A. Create datapath B. Connect DP to controller C. Derive controller FSMDigital Design 2eCopyright 2010Frank Vahid9
Design Process Describe system in programs Data subsystem– List data operations– Map operations to functional blocks– Add interconnect for data transport– Input control signals and output conditions Control Subsystem– Derive the sequence according to the hardware program– Create the sequential machine– Input conditions and output control signalsDigital Design 2eCopyright 2010Frank Vahid10
Example: MultiplicationArithmeticZ X Y M 0 For i n-1 to 0– If Yi 1, M M X* 2i Z MDigital Design 2eCopyright 2010Frank VahidInput X, YOutput ZVariable M, i M 0 For i n-1 to 0– If Yn-1 1, M M X– Shift Y left by one bit– If i ! 0, shift M left by onebit Z M11Source: CK Cheng
Implementation: ExampleMultiply(X, Y, Z, start, done){ Input X[15:0], Y[15:0] type bit-vector,start type boolean;Local-Object A[15:0], B[15:0] ,M[31:0], i[4:0] type bit-vector;Output Z[31:0] type bit-vector,done type boolean;S0: If start’ goto S0 done 1;S1: A X B Y i 0 M 0 done 0;S2: If B15 0 goto S4 i i 1;S3: M M A;S4: if i 16, goto S6S5: M Shift(M,L,1) B Shift(B,L,1) goto S2;S6: Z: M done 1 goto S0;}Digital Design 2eCopyright 2010Frank Vahid12Source: CK Cheng
Step 0: SyntaxS1: A X B Y i 0 M 0 done 0;S2: If B15 0 goto S4 i i 1;S3: M M A;S5: M Shift(M,L,1) B Shift(B,L,1) goto S2;S6: Z: M done 1 goto S0;Digital Design 2eCopyright 2010Frank Vahid13Source: CK Cheng
Step 1: Identify Input and Output of data and control subsystemsZ XYMultiply(X, Y, Z, start, done){ Input: X[15:0], Y[15:0] type bit-vector,start type boolean;Local-Object : A[15:0], B[15:0] ,M[31:0],i[4:0] type bit-vector;Output Z[31:0] type bit-vector,done type boolean;S0: If start’ goto S0 done 1;S1: A X B Y i 0 M 0 done 0;S2: If B15 0 goto S4 i i 1;S3: M M A;S4: if i 16, goto S6S5: M Shift(M,L,1) B Shift(B,L,1) goto S2;S6: Z: M done 1 goto ne}Digital Design 2eCopyright 2010Frank Vahid14Source: CK Cheng
Step 2a: Identify Data Subsystem OperationsZ XYMultiply(X, Y, Z, start, done){ Input: X[15:0], Y[15:0] type bit-vector,start type boolean;Local-Object : A[15:0], B[15:0] ,M[31:0],i[4:0] type bit-vector;Output Z[31:0] type bit-vector,done type boolean;S0: If start’ goto S0 done 1;S1: A X B Y i 0 M 0 done 0;S2: If B15 0 goto S4 i i 1;S3: M M A;S4: if i 16, goto S6S5: M Shift(M,L,1) B Shift(B,L,1) goto S2;S6: Z: M done 1 goto S0;16XData16YSubsystem?start32Z?ControlSubsystem done}Digital Design 2eCopyright 2010Frank Vahid15Source: CK Cheng
Step 2b: Map Data Operations to functional modules in data libraryoperationMultiply(X, Y, Z, start, done){ Input: X[15:0], Y[15:0] type bit-vector,start type boolean;Local-Object : A[15:0], B[15:0] ,M[31:0],i[4:0] type bit-vector;Output Z[31:0] type bit-vector,done type boolean;S0: If start’ goto S0 done 1;S1: A X B Y i 0 M 0 done 0;S2: If B15 0 goto S4 i i 1;S3: M M A;S4: if i 16, goto S6S5: M Shift(M,L,1) B Shift(B,L,1) goto S2;S6: Z: M done 1 goto S0;A XB YM 0i 0i i 1M M AM Shift(M,L,1)B Shift(B,L,1)Z: MA Load (X)B Load (Y)M Clear(M)i Clear(i)i INC(i)M Add(M,A)M SHL(M)B SHL(B)Wires}Digital Design 2eCopyright 2010Frank Vahid16Source: CK Cheng
Step 2c: Implement the data subsystemDRegisters: If C then R DCLDRoperationA Load (X)B Load (Y)B SHL(B)M Clear(M)M Add(M,A)M SHL(M)i Clear(i)i INC(i)Digital Design 2eCopyright 2010Frank Vahid17Source: CK Cheng
Function Modules: Registers to store data (A, B, M)Register AoperationA Load (X)B Load (Y)B SHL(B)M Clear(M)M Add(M,A)M SHL(M)i Clear(i)i INC(i)RDX16LDRegister MAC0D16RLD CLRMC1 C2Register B16YRDLDBB[15]C3Digital Design 2eCopyright 2010Frank Vahid18Source: CK Cheng
Function Modules: Adder, Shifter (updates to M)Register AoperationA Load (X)B Load (Y)B SHL(B)M Clear(M)M Add(M,A)M SHL(M)i Clear(i)i INC(i)RDX16LDSelectorARegister MAdderABS0161 SHLC0DC4RLD CLRMC1 C2Register B16YRDLDBB[15]C3Digital Design 2eCopyright 2010Frank Vahid19Source: CK Cheng
Function Modules: Adder, Shifter (updates to B)operationA Load (X)B Load (Y)B SHL(B)M Clear(M)M Add(M,A)M SHL(M)i Clear(i)i INC(i)YRDX16LDAdderABSSelectorC00Register M0D16116 Selector SHLARegister A SHLC4RLD CLRMC1 C2Register BD1LDC5C3R BB[15]20Digital Design 2eCopyright 2010Frank VahidSource: CK Cheng
Function Modules: Counter (updates to i)operationA Load (X)B Load (Y)B SHL(B)M Clear(M)M Add(M,A)M SHL(M)i Clear(i)i INC(i)YRDX16LDSelectorAdderABS0D16C00 SHLRLD CLRMC1 C2C4Register BD1LDC5C3R BB[15]Counter iDRCLR IncC6 C7Digital Design 2eCopyright 2010Frank VahidRegister M116 Selector SHLARegister Ai[4]21Source: CK Cheng
Step 2d: Map Control Signals to OperationsoperationA Load (X) C0 1B Load (Y) C5 0 and C3 1B SHL(B)C5 1 and C3 1Register AM Clear(M) C2 1M Add(M,A) C4 0 and C1 1XD RAM SHL(M)C4 1 and C1 1 16LDi Clear(i)C6 1i INC(i)C7 1C0Y16 Selector SHL0ASelectorAdderBS0D161 SHLRLD CLRMC1 C2C4Register BD1LDC5C3R BB[15]Counter iDRCLR IncC6 C7Digital Design 2eCopyright 2010Frank VahidRegister Mi[4]22Source: CK Cheng
16XData16YSubsystemB[15], i[4]startDigital Design 2eCopyright 2010Frank Vahid32ZC0:7ControlSubsystem done23Source: CK Cheng
Design the Control SubsystemMultiply(X, Y, Z, start, done){S0: If start’ goto S0 done 1;S1: A X B Y i 0 M 0 done 0;S2: If B15 0 goto S4 i i 1;S3: M M A;S4: if i 16, goto S6S5: M Shift(M,L,1) B Shift(B,L,1) goto S2;S6: Z: M done 1 goto S0} Multiply(X, Y, Z, start, done)operationA Load (X) C0 1B Load (Y) C5 0 and C3 1B SHL(B)C5 1 and C3 1M Clear(M) C2 1M Add(M,A) C4 0 and C1 1M SHL(M)C4 1 and C1 1i Clear(i)C6 1i INC(i)C7 1{S0: If start’ goto S0 done 1;S1: C0 1 C5 0 and C3 1 C6 1 C2 1 done 0;S2: If B15 0 goto S4 C7 1;S3: C4 0 and C1 1;S4: if i[4], goto S6S5: C4 1 and C1 1 C5 1 and C3 1 goto S2;S6: Z: M done 1 goto S0Digital }Design 2eCopyright 2010Frank Vahid24Source: CK Cheng
Control Subsystemstart’Multiply(X, Y, Z, start, done){S0startS1S0: If start’ goto S0 done 1;S1: C0 1 C5 0 and C3 1 C6 1 C2 1 done 0;S2: If B15 0 goto S4 C7 1;S3: C4 0 and C1 1;S2S4: if i[4], goto S6S5: C4 1 and C1 1 C5 1 and C3 1 goto S2;B[15]S6: Z: M done 1 goto S0}S3Digital Design 2eCopyright 2010Frank VahidS6S5i[4]i[4]’B[15]’S425Source: CK Cheng
One-Hot State [15]S3Digital Design 2eCopyright 2010Frank VahidS426Source: CK Cheng
One-Hot 3S4i[4]’Digital Design 2eCopyright 2010Frank Vahid27Source: CK Cheng
Control Subsystem: One-Hot StateMachine DesignInput: State Diagram1.Use a flip flop to replace each state.2.Set the flip flop which corresponds to the initialstate and reset the rest flip flops.3.Use an OR gate to collect all inward edges.4.Use a Demux to distribute the outward edges.Digital Design 2eCopyright 2010Frank Vahid28Source: CK Cheng
Data SubsystemRegister ARDX16LDAASelectorAdderBSRegister M0D161C0Y16 Selector SHL0 SHLLD CLRMC1 C2C4Register BD1LDC5C3R BB[15]Counter iDRCLR IncC6 C7Digital Design 2eCopyright 2010Frank VahidRi[4]29Source: CK Cheng
Multiply(X, Y, Z, start, done){S0: If start’ goto S0 done 1;S1: C0 1 C5 0 and C3 1 C6 1 C2 1 done 0;S2: If B15 0 goto S4 C7 1;S3: C4 0 and C1 1;S4: if i[4], goto S6S5: C4 1 and C1 1 C5 1 and C3 1 goto S2;S6: Z: M done 1 goto S0}C0 C1 C2 C3 C4C5C6(mux) 0X000S40000XX000S5010111000S60000XX001Digital Design 2eCopyright 2010Frank Vahid30Source: CK Cheng
C0C1 001Digital Design 2eCopyright 2010Frank Vahid31Source: CK Cheng
One-Hot 3S4i[4]’Digital Design 2eCopyright 2010Frank Vahid32Source: CK Cheng
Lecture 15: RTL Design CSE 140: Components and Design . . Digital Design
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