Chapter 5: RTL Design – Memories And Hierarchy RTL Design - Free Download PDF

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ECE 274 Digital LogicDigital DesignRTL Design – Memories and HierarchyChapter 5:RTL DesignDigital Design 5.6 – 5.8Slides to accompany the textbook Digital Design, First Edition,by Frank Vahid, John Wiley and Sons Publishers, 2007.http://www.ddvahid.comCopyright 2007 Frank VahidInstructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites. PowerPoint source (or pdfwith animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means.Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructorsmay obtain PowerPoint source or obtain special use permissions from Wiley – see for information.RTL Design5.6RTL DesignMemory Components Register-transfer level designinstantiates datapath componentsto create datapath, controlled by acontroller MxN memory A few more components are oftenused outside the controller anddatapathM wordsRTL Design MethodM words, N bits wide eachSeveral varieties of memory, whichwe now introduceN-bitswide eachM N memory341

RTL DesignRTL DesignRandom Access Memory (RAM) RAM Internal StructureRAM – Readable and writable memory 32W data4W addrStrange name – Created several decades ago tocontrast with sequentially-accessed storage liketape drivesW enLogically same as register file – Memory withaddress inputs, data inputs/outputs, and control 32“Random access memory” R addr16 32register filedata104addrrwenR end0addr0addr1addr(A-1)RAM usually just one port; register file usually twoor moreclk32data10RAM typically larger than roughly 512 or 1024wordsRAM typically stores bits using a bit storageapproach that is more efficient than a flip flopRAM typically implemented on a chip in a squarerather than rectangular shape – keeps longest wires(hence delay) shortaddrrwwdata(N-1) wdata(N-2) wdata0Let A log2M1024x32RAMRegister file from Chpt. 4RAM vs. register file 32R dataenrw1024 32RAMbit storageblock(aka “cell”)wordenablea0a1 AxMd1decodera(A-1)eworddata cellword wordenable enablerw datad(M-1)to all cellsRAM cellrdata(N-1) rdata(N-2) rdata0enSimilar internal structure as register file RAM block symbol Decoder enables appropriate word based on address inputsrw controls whether cell is written or readLet’s see what’s inside each RAM cell56RTL DesignRTL DesignStatic RAM (SRAM)Static RAM (SRAM)SRAM “Static” RAM cell When 1, the data bit value enters the loop “Static” RAM cell data’0 a10 That loop is where a bit stays stored1wordenable1wordenabledata is the bit to be stored in this celldata’ enters on other sidedataExample shows a “1” being written into celld0 data’celld’0 a7data1Reading this cell d data1word enable input comes from decoderWhen 0, value d loops around inverters SRAM cellSRAM cell6 transistors (recall inverter is 2 transistors)Writing this cell1024x32RAMen0wordenable addrrwaen dataSomewhat trickierWhen rw set to read, the RAM logic setsboth data and data’ to 1The stored bit d will pull either the left lineor the right bit down slightly below 1“Sense amplifiers” detect which side isslightly pulled downdata’1d10awordenable11 1To sense amplifiersThe electrical description of SRAM is reallybeyond our scope – just general idea here,mainly to contrast with DRAM.82

RTL DesignRTL DesignDynamic RAM (DRAM)3210Comparing Memory Types dataaddrrw 1024x32RAM en DRAM cell “Dynamic” RAM cell cell1 transistor (rather than 6)Relies on large capacitor to store bit wordenableWrite: Transistor conducts, data voltage levelgets stored on top plate of capacitorRead: Just look at value of dProblem: Capacitor discharges over time Must “refresh” regularly, by reading d and thenwriting it right backd data(b)registerfileSRAMDRAMDRAM Slowest But very compactAnd refreshing takes timeUse register file for small items,SRAM for large items, and DRAM forhuge items enableMxN Memoryimplemented as a:FastMore compact than register file capacitorslowlydischarging(a)dFastestBut biggest sizeSRAM data Register filedischargesSize comparison for samenumber of bits (not to scale)Note: DRAM’s big capacitor requiresa special chip design process, soDRAM is often a separate chip9RTL DesignRTL DesignRAM Example: Digital Sound RecorderReading and Writing a RAMclk21addr913data500999rwclk39Zaddr5001 means writeen Writing datarwvalid setuptimevalidholdtimesetuptimeRAM[9]RAM[13]now equals 500 now equals 999Z500accesstime Put address on addr lines, data on data lines, set rw 1, en 1Record: Digitize sound, store as series of 4096 12-bit digital values in RAM Set addr and en lines, but put nothing (Z) on data lines, set rw 0Data will appear on data lines Don’t forget to obey setup and hold times Behavior (b)Reading 10To record, processor should read a-to-d, store read values intosuccessive RAM words In short – keep inputs stable before and after a clock edge11We’ll use a 4096x16 RAM (12-bit wide RAM not common)Play back laterCommon behavior in telephone answering machine, toys, voice recordersTo play, processor should read successive RAM words and enable d-to-a123

RTL DesignRTL DesignRAM Example: Digital Sound Recorder RAM Example: Digital Sound RecorderRTL design of processor Create high-level statemachineBegin with the record behaviorKeep local register a Stores current address, rangesfrom 0 to 4095 (thus need 12bits)Create state machine thatcounts from 0 to 4095 using a analog-todigitalconverter 16ad bufad ld12Now create play behaviorUse local register a again, createstate machine that counts from0 to 4095 againdigital-toanalogconverterRa Rw Ren Read analog-to-digital conv. ad ld 1, ad buf 1Write to RAM at address a Ra a, Rrw 1, Ren 1Local register: a (12 bits)a 4095STa 0ad ld 1ad buf 1Ra aRrw 1Ren 1For each a da ldprocessorRecord behaviorFor each a 4096x16RAM aUa a 1Read RAMWrite to digital-to-analog conv.Note: Must write d-to-a onecycle after reading RAM, whenthe read data is available on thedata busThe record and play statemachines would be parts of alarger state machine controlledby signals that determine whento record or play4096x16RAManalog-todigitalconverterdata bus1612ad bufad lddigital-toanalogconverterRa Rw Renprocessorda ldPlay behaviorLocal register: a (12 bits)a 4095VWa 0ad buf 0Ra aRrw 0Ren 1a 4095aXda ld 1a a 1a 409513RTL DesignRTL DesignRead-Only Memory – ROM 3210Data lines are output onlyNo need for rw input Compact: May be smallerNonvolatile: Saves bits even if power supplyis turned offSpeed: May be faster (especially than DRAM)Low power: Doesn’t need power supply tosave bits, so can extend battery lifeChoose ROM over RAM if stored data won’tchange (or won’t change often) For example, a table of Celsius to Fahrenheitconversions in a digital thermometer32dataaddrrw10dataaddr1024x32ROMLet A log2Men1024 32RAMenAdvantages over RAM Read-Only Memory – ROMMemory that can only be read from, notwritten to 14d0ROM block symboladdr0addr1RAM block lea0a1 AxMd1decodera(A-1)eworddataword wordenable enabledatad(M-1)enrdata(N-1) rdata(N-2) rdata0ROM block symbol 15bit storageblock(aka “cell”)ROM cellInternal logical structure similar to RAM, without the data input lines164

RTL DesignRTL DesignROM Types If a ROM can only be read, how are thestored bits stored in the first place? ROM Types Fuse-Based Programmable ROM Storing bits in a ROM known asprogrammingSeveral methods Mask-programmed ROM Bits are hardwired as 0s or 1s duringchip manufacturing 2-bit word on right stores “10”word enable (from decoder) simplypasses the hardwired value throughtransistorEach cell has a fuseA special device, known as a programmer,blows certain fuses (using higher-thannormal voltage)1data line0data line cellcell wordenableThose cells will be read as 0s (involvingsome special electronics)Cells with unblown fuses will be read as 1s2-bit word on right stores “10”Also known as One-TimeProgrammable (OTP) ROM1data line1celldata linecellawordenableNotice how compact, and fast, thismemory would befuseblown fuse17RTL DesignRTL DesignROM TypesROM TypesErasable Programmable ROM(EPROM) Uses “floating-gate transistor” in each cellSpecial programmer device uses higherthan-normal voltage to cause electrons totunnel into the gate Electrons become trapped in the gateOnly done for cells that should store 0Other cells (without electrons trapped ingate) will be 1 2-bit word on right stores “10”Details beyond our scope – just generalidea is necessary here Similar to EPROM wordenabledata linedata linecellcell1 trapped electronsLike EEPROM, but all words (or large blocks of words)can be erased simultaneouslyBecome common relatively recently (late 1990s)Both types are in-system programmable Gives trapped electrons energy to escapeRequires chip package to have windowCan be programmed with new stored bits while in thesystem in which the ROM operates 19Uses floating-gate transistor, electronic programming totrap electrons in certain cellsBut erasing done electronically, not using UV lightErasing done one word at a timeFlash memory 0eÐeÐTo erase, shine ultraviolet light onto chip Electronically-Erasable Programmable ROM(EEPROM) floating-gatetransistor 18Requires bi-directional data lines, and write control inputAlso need busy output to indicate that erasing is inprogress – erasing takes some time3210dataaddrenwrite1024x32EEPROMbusy205

RTL DesignRTL DesignHierarchy and AbstractionBlurring of Distinction Between ROM and RAM We said that RAM is readable and writableROM is read-onlyNVRAM Also, number of writes may be limited (perhaps a few million times) And, some RAMs act almost like ROMs One type: Built-in battery, may work for up to 10 yearsAnother type: Includes ROM backup for RAM – controller writes RAM contents toROM before turning offa7. a0Hierarchy often involves not just grouping itemsinto a new item, but also associating higher-levelbehavior with the new item, known as abstraction New memory technologies evolving that merge RAM and ROM benefits To go from transistors to gates, muxes,decoders, registers, ALUs, controllers, datapaths,memories, queues, etc.Imagine trying to comprehend a controller anddatapath at the level of gatesAbstraction Non-volatile RAMs: Can save their data without the power supply Hierarchy helps us manage complexity aEssentially means that writes are slow EEPROM RAMEEPROM and Flash are in-system programmable FlashBut some ROMs act almost like RAMs ROM e.g., MRAMb7. b08-bit addercoe.g., an 8-bit adder has an understandable highlevel behavior – it adds two 8-bit binary numbersFrees designer from having to remember, or evenfrom having to understand, the lower-level detailsBottom line Lot of choices available to designer, must find best fit with design goals21RTL DesignHierarchy and Composing Larger Components from Smaller VersionsA common task is to compose smaller componentsinto a larger one Gates: Suppose you have plenty of 3-input AND gates,but need a 9-input AND gate a Composing memory very commonMaking memory words wider Can simple compose the 9-input gate from several 3-inputgates Muxes: Suppose you have 4x1 and 2x1 muxes, butneed an 8x1 mux 22RTL DesignHierarchy and Composing Larger Components from Smaller Versions cis7. s0 Easy – just place memories side-by-side until desired width obtainedShare address/control lines, concatenate data linesExample: Compose 1024x8 ROMs into 1024x32 ROM10s2 selects either top or bottom 4x1s1s0 select particular 4x1 inputImplements 8x1 mux – 8 data inputs, 3 selects, oneoutputaddrenProvince 4x32ROMendata3223246

RTL DesignHierarchy and Composing Larger Components from Smaller Versions 11Creating memory with more words a9.a0Put memories on top of one another until thenumber of desired words is achievedUse decoder to select among the memoriesa10Can use highest order address input(s) asdecoder inputAlthough actually, any address line could beusedExample: Compose 1024x8 memories into2048x8 memoryaa10 a9a8a00 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 1 0a10 just chooses 0 1 1 1 1 1 1 1 1 1 00 1 1 1 1 1 1 1 1 1 1which memory to1 0 0 0 0 0 0 0 0 0 0access1 0 0 0 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0 1 01 1 1 1 1 1 1 1 1 1 01 1 1 1 1 1 1 1 1 1 11x2 d0i0 dcde d11024x8ROMen drdata1024x8ROMen dataaddrendata88aTo create memory with morewords and wider words, can firstcompose to enough words, thenwiden.257

RTL Design – Memories and Hierarchy Digital Design 5.6 – 5.8 Digital Design Chapter 5: RTL Design Slides to accompany the textbook Digital Design, First Edition, by Frank Vahid, John Wiley and Sons Publishers, 2007. ... 2 5 RTL Design Random Access Memory (RAM)