Comparative Study Of Approximate Multipliers - Concordia University
Comparative Study of Approximate MultipliersMahmoud Masadeh1 , Osman Hasan1,2 , and Sofiène Tahar1arXiv:1803.06587v1 [cs.ET] 18 Mar 20181Department of Electrical and Computer Engineering,Concordia University, Montréal, Canada{m masa,o hasan,tahar}@ece.concordia.ca2School of Electrical Engineering and Computer Science,National University of Science and Technology, Islamabad, PakistanTECHNICAL REPORTMarch 20181
AbstractApproximate multipliers are widely being advocated for energy-efficient computing in applications that exhibit an inherent tolerance to inaccuracy. However,the inclusion of accuracy as a key design parameter, besides the performance,area and power, makes the identification of the most suitable approximate multiplier quite challenging. In this paper, we identify three major decision makingfactors for the selection of an approximate multipliers circuit: (1) the type ofapproximate full adder (FA) used to construct the multiplier, (2) the architecture, i.e., array or tree, of the multiplier and (3) the placement of sub-modulesof approximate and exact multipliers in the main multiplier module. Basedon these factors, we explored the design space for circuit level implementationsof approximate multipliers. We used circuit level implementations of some ofthe most widely used approximate full adders, i.e., approximate mirror adders,XOR/XNOR based approximate full adders and Inexact adder cell. These FAcells are then used to develop circuits for the approximate high order compressorsas building blocks for 8x8 array and tree multipliers. We then develop variousimplementations of higher bit multipliers by using a combination of exact andinaccurate 8x8 multiplier cells. All these implementations have been done usingthe Cadence’s Spectre tool with the TSMC65nm technology. The design space ofthese multipliers is explored based on their power, area, delay and error and thebest approximate multiplier designs are identified. The report also presents thevalidation of our results using an image blending application. An open sourcelibrary of implemented cells and multiplier circuits are available online.Keywords— Approximate Computing, Approximate Multiplier, Power-Efficiency,Error Metrics, Circuit Characteristics, Comparative Study2
Contents1 Introduction42 Proposed Methodology53 Approximate FAs and Compressors74 Multiplier Basic Blocks4.1 8x8 Array Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . .4.2 8x8 Tree Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . .101013514151717Higher-Order Multiplier Configuration5.1 16x16 Array Multiplier . . . . . . . . . . . . . . . . . . . . . . . . .5.2 16x16 Tree Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . .5.3 Discussion and Comparison . . . . . . . . . . . . . . . . . . . . . .6 Application197 Conclusions203
1IntroductionThe pervasive, portable, embedded and mobile nature of present age computing systemshas led to an increasing demand for ultra low power consumption, small footprint, andhigh performance. Approximate computing [1] is a nascent computing paradigm thatallows us to achieve these objectives by compromising the arithmetic accuracy. Manysystems used in domains, like multimedia and big data analysis, exhibit an inherenttolerance to a certain level of inaccuracies in computation, and thus can benefit fromapproximate computing.Functional approximation [2], in hardware, mostly deals with the design of approximate arithmetic units, such as adders and multipliers, at different abstraction levels,i.e., transistor, gate, RTL (Register Transfer Level) and application. Some notableapproximate adders include speculative adders [3], segmented adders [4], carry selectadders [5] and approximate full adders [6]. The transistor level approximation providesthe highest flexibility due to the ability to tweak most of the design parameters at thislevel. Various approximate full adders (FA) at the transistor level have been proposedincluding the mirror adders [7], the XOR/XNOR based FA [8] and the inexact FA [9].On the other hand, most of approximate multipliers have been designed at higher levelsof abstraction, i.e., gate, RTL and application.Approximate multipliers have been mainly designed using three techniques, i) Approximation in partial products generation: e.g., Kulkarni et al. [2] proposed an approximate 2x2 binary multiplier at the gate level by changing a single entry in theKarnaugh-map with an error rate of 1/16. ii) Approximation in partial product tree:e.g., Error Tolerant Multipliers (ETM) [10] divide the input operands in two parts, i.e.,the multiplication part for the MSBs and the non-multiplication part for the LSBs, andthus omitting the generation of some partial products [11]. iii) Approximation in partialproducts summation: Approximate FA cells are used to form an array multiplier, e.g.,in [12] the approximate mirror adder has been used to develop a multiplier. Similarly,Momeni et al. [13] proposed an approximate compressor for building approximate multipliers, but this multiplier is known to give a non-zero result for zero inputs. Jiang etal. [14] compared the characteristics of different approximate multipliers, implementedin VHDL based on the three different techniques mentioned previously. In this work, wetarget approximate multipliers based on approximation in partial products summation.In this report, we compare the accuracy and circuit characteristics of differentapproximate multipliers. These multipliers are designed based on three identified decisions: (1) the type of approximate FA used to construct the multiplier, (2) thearchitecture of the multiplier, and (3) the placement of sub-modules of approximateand exact multipliers in the target multiplier module. We were able to design approximate multipliers, which are suitable to applications with intrinsic error resiliency. Weused these designs in an image processing application and obtained promising results,thus we believe they are applicable in other domains. The rest of the report is organized as follows: The proposed methodology of designing and evaluating approximatemultipliers is explained in Section 2. Section 3 explains the design characteristics ofapproximate FAs and compressors. Section 4 describes different configurations of approximate sub-modules, with different architectures. Target approximate multiplies4
are designed and evaluated in Section 5. The application of image processing is givenin Section 6. Finally, conclusions are drawn in Section 7.2Proposed MethodologyThe design space for approximate multipliers based on different approximate FAs andcompressors is quite huge. However, it is difficult to select the most suitable design fora specific application. Figure 1 presents an overview of our proposed methodology tobuild different approximate multipliers and compare their design metrics to select themost suitable design. It consists of the following steps:1. Building a library of elementary approximate FAs using the TSMC65nm technology in Cadence Spectre: We use the default transistors of this technology to build11 approximate FA designs comprising of 5 mirror FAs, 3 XOR/XNOR gate FAsand 3 inexact FAs. To the best of our knowledge, these 11 designs are the onlyones that exist in the literature at the transistor level.2. Characterization and early space reduction: We perform area, power, latency andquality characterizations of different approximate FAs to filter out non-Paretodesigns.Figure 1: Methodology Overview5
3. Building a library of approximate compressors: We build a Cadence library ofapproximate compressors using the optimal approximate FA, as recommendedby [7].4. Building approximate multipliers basic blocks: Based on approximate FAs andcompressors, we design various approximate 8x8 array and tree multipliers, respectively. These proposed designs are related to the ripple-carry array multiplierarchitecture, which is the most power efficient amonge conventional architectures [15].5. Design target approximate multipliers: Based on different configurations of 8x8approximate multipliers, the target multiplier modules are designed and characterized.6. Selection of design points: Considering the required quality constrains of a specific application, a subset of power-efficient design points is selected.In order to evaluate the efficiency of the proposed approximate designs, powerconsumption and area, represented by the number of transistors used, are measured,and the circuit performance is measured by the maximum delay between changing theinputs and observing the output(s). Besides these basic design metrics, accuracy is alsoan important design constraint in approximate computing. There exist several errormetrics used in approximate computing to quantify errors and measure accuracy [9],including: Error Rate (ER): The percentage of erroneous outputs among all outputs. Error Distance (ED): The arithmetic difference between the exact and approximate result. Mean Error Distance (MED): The average of EDs for a set of outputs obtainedby applying a set of inputs. Relative Error Distance (RED): The ratio of ED to exact result. Mean Relative Error Distance (MRED): The average value of all possible relativeerror distances (RED). Normalized Mean Error Distance (NMED): The normalization of mean errordistance (MED) by the maximum output of the accurate design. This metric isused for comparing circuits (adders and multipliers) of different sizes.For the evaluation of the accuracy of the approximate FAs, we use the number oferroneous outputs. In the proposed methodology, we evaluate ER, MED, NMED andMRED for the proposed designs. As shown in Figure 1, the characterization and selection process is applied at multiple steps to different components, during the designflow. Characterization aims to find the design characteristics of the circuits including area, power consumption, performance, error metrics, and other derived metrics6
such as Power-Delay-Product (PDP). The design selection process for the evaluatedapproximate designs also depends on the application domain of the given circuit. Asthe design requirements vary from one application to another, our designs are uniquebecause they can provide some degree of error in the output as well and thus this aspectalso needs to be covered in the characterization and selection process.3Approximate FAs and CompressorsApproximate n-bit binary adders can be designed by modifying the carry generationand propagation of the addition process by using several overlapping sub-adders toreduce latency. Some examples include speculative [3], segmented [4] and carry select adders [5]. However, these designs involve several overlapping sub-adders, whichmakes them unsuitable to build energy efficient circuits. Low power approximate binary adders are generally constructed by replacing the accurate FAs with approximateFAs. We consider five approximate mirror adders (AMA1, AMA2, AMA3, AMA4and AMA5) [7], three approximate XOR/XNOR based full adders (AXA1, AXA2 andAXA3) [8] and three inexact adder cells (InXA1, InXA2 and InXA3) [9].Table 1 shows the truth tables of the 11 considered approximate FAs, and theircharacteristics including Size (A), Power consumption (P), Delay (D), number of Erroneous outputs (E), which indicates the likelihood of at least one output (Cout or Sum)being wrong, and PDP. All approximate FAs are Pareto-points, i.e., they provide lessarea and power consumption compared to the exact design at the cost of compromisingaccuracy [16]. Some of the FA designs have an enhanced performance (reduced delay),while other designs have degraded performance due to the internal structure and nodecapacitance. In [17], AMA5 is considered as a wire with zero area and zero powerconsumption. However, this is unrealistic as the output of AMA5 has to drive othersignals. Thus, we used two buffers instead of two wires to design it.Table 1: Truth Tables of Different Approximate FAs and Comparison of their CharacteristicsExact FA (E)AMA1 (M1)AMA2 (M2)AMA3 (M3)AMA4 (M4)AMA5 (M4)AXA1 (X1)AXA2 (X2)AXA3 (X3)InXA1 (In1)InXA2 (In2)InXA3 1111111111111011Size28201411158868686Power 355.164815011558381467Delay (ps)244195366360196740832767# of Error Cases022334442222PDP 2303.4295.44753.5Figure 2 shows the power consumption and delay of individual approximate FAs,where all FAs exhibit a reduced power consumption. But, only the mirror adder basedFAs have a reduced delay due to their internal structure. InXA2 and AXA2 havethe minimal power consumption with 53% reduction compared to the exact mirroradder (MA). Also, InXA1 and AXA3 have close-to-minimal power consumption. Since7
Figure 2: Power Consumption and Delay of Approximate FAsFigure 3: Power-Delay-Product of Approximate FAsFigure 4: Size and Number of erroneous outputs (ER) of Approximate FAsAMA5 is composed of only two buffers, it has the lowest delay while AXA3 has thehighest delay due to the threshold voltage drop of the pass transistors. AMA1 andAMA4 both have a close-to-minimal delay. PDP which is a figure of merit correlatedwith the energy efficiency of a digital design, is shown in Figure 3 for the FAs. Mirroradder based designs have a low PDP values. AMA5 and AXA1 exhibit the lowest andhighest PDP, respectively.Figure 4 shows the number of transistors for each FA, as well the number of erronous8
Figure 5: 8-to-4 Compressor Designoutputs. AXA2, InXA1 and InXA3 consist of 6 transistors each, and thus have a 78.6%area reduction compared to the exact MA. AMA5, AXA1, AXA3 and InXA2 all have8 transistors. AMA5, AXA1 and AXA2 have 4 erroneous outputs. AMA3 and AMA4have 3 erroneous outputs, and the remaining 6 designs have 2 erroneous outputs. Ourresults are consistent with the findings reported in [7] [8] [9].Assuming that the characteristics of approximate FAs are linearly applied to approximate arithmetic circuits (adders and multipliers), there is no single approximateFA, which is superior in all aspects. Therefore, we propose to use a fitness function toevaluate the designs based on its design metrics.F itness C1 A C2 P C3 D C4 E C5 P DP(1)where C1, C2, C3, C4 and C5 are application-dependent design coefficients within therange [0,1] which provide weights to specific design metrics for a specific application,e.g., E equals zero for the exact designs where approximation is not allowed, and P issmall for low power designs depending of application error-resiliency. The fitness of theapproximate circuit depends on the application resiliency and input data distribution.A minimal fitness value is preferred since the goal is to minimize A, P, D and E. Forthe remainder of this work, we use all 11 Pareto-design approximate FAs as elementarybuilding cells to construct approximate array multipliers.Higher-order compressors, e.g., 5-to-3 (which compresses five partial product bitsinto three) and 8-to-4 (which compresses eight partial product bits into four) [13],allow us to construct high speed tree multipliers. Therefore, we also developed approximate FA based compressors, e.g., a 8-to-4 binary compressor is depicted in Figure 5,for evaluation purposes. Table 2 shows the power consumption and area for differentapproximate compressors implemented using approximate FAs. The area for approximate compressors exhibits a linear relationship with the area of FAs. However, it looksdifficult to obtain a closed-form analytical expression for the power consumption. Fewdesigns have a larger power consumption compared to the exact one, and this behaviorneeds more investigation. For that, and as a future work, we plan to use several ap-9
Table 2: Power Consumption and Area for Different Approximate Compressors basedon Different Approximate FAsPower Consumption (µw)for Different CompressorsArea (number of transistors)for Different CompressorsCompressor TypeCompressor TypeFA Type3-24-35-36-37-38-4FA 6322466proximate compressors with different approximation degrees in order to cover a largerdesign space. Considering all options, the total combination of compressor settingsgrows exponentially O( (# of FA designs)# of FAs in compressor ) O (11)4 14641 in ourcase. Therefore, to show the effectiveness of designing approximate compressors basedon approximate FAs, we chose four FAs only. These FAs have superior designs metrics.The best approximate FA in terms of delay and PDP was AMA5, and in terms ofpower and area was AXA2. Also, the best FA with low error rate was InXA1. AMA3has moderate characteristics regarding area, power, delay, and number of errors. Theseselected FAs are used to design approximate high-order compressors, which in turn canbe used for designing approximate tree multipliers. However, these selected compressors are not guaranteed to be the optimal ones. But, they exhibit some improvementscompared to the exact designs.4Multiplier Basic BlocksIn this section, we use the approximate FAs and compressors, described above, to design8x8 array and tree based multipliers, respectively. These 8x8 approximate multiplierswill act as our basic blocks for designing higher-order multipliers, i.e., 32x32 and 64x64,as it will be discussed in Section 5.4.18x8 Array MultiplierAn n-bit array multiplier [18] is composed of n2 AND gates for partial products generation, and n-1 n-bit adders for partial products accumulation. The design space ofan nxn approximate array multiplier is quite huge, since it depends on the type ofFA used in the array, and the number of approximate FAs (from 0 to n) used in then-bit adder. Considering all options, the total combination of multiplier settings grow22exponentially O( (# of FAs)MultiplierSize ) O ((11)n ) (11)64 in our case.10
Table 3: 8x8 Approximate Array MultiplierTypeEEMREDMEDERNMEDDelay Power size(ps)(µW)0000000052731.411456EM18.55E-022.55E 029.70E-013.93E-0352724.171288M1M12.13E 001.33E 049.96E-012.05E-0186514.751072EM21.85E-012.29E 029.90E-013.52E-0355722.971162M2M21.73E 011.68E 041.00E 002.58E-0160014.4784EM34.03E-014.72E 029.99E-017.26E-0360524.951099M3M31.25E 011.72E 041.00E 002.64E-0159815.31640EM43.64E-021.11E 029.70E-011.71E-0357321.851183M4M46.11E-016.41E 039.96E-019.86E-0231311.17832EM53.03E-021.01E 029.30E-011.56E-0357322.151036M5M56.76E-018.24E 039.90E-011.27E-0125010.69496EX11.18E-012.09E 029.71E-013.21E-0354631.861036X1X12.84E 001.05E 049.96E-011.61E-0155821.33496EX21.09E-011.88E 021.00E 002.89E-0356923.38994X2X21.18E 011.51E 041.00E 002.31E-0125013.91400EX37.96E-023.48E 026.15E-015.35E-0353625.541036X3X39.88E-011.63E 049.96E-012.50E-0119715.06496EIn17.50E-023.19E 026.15E-014.91E-0351726.07994In1In11.62E 001.02E 048.54E-011.56E-0140314.82400EIn23.68E-021.80E 025.84E-012.76E-0352828.791036In2In24.63E-018.28E 038.26E-011.27E-0134012.56496EIn31.85E-012.29E 029.90E-013.52E-0355627.96994In3In31.73E 011.68E 041.00E 002.58E-0140423.92400We have used all 11 Pareto approximate FAs, described in Section 3, to construct8x8 approximate array multipliers, based on only one FA type per design to avoid theexponential growth of the design space. Regarding the degree of approximation, wehave used two options: i) all FAs are approximate, and ii) FAs that contribute to theleast significant 50% of the resultant bits are approximated to maintain acceptableaccuracy as recommended by [7] [12] [19]. Thus, we have designed, evaluated andcompared 22 different options for building 8x8 approximate array multipliers as shownin Table 3, using the TSMC65nm technology. The type of the multiplier in Table 3consists of two parts, i.e., the name of the adder used for the most significant and leastsignificant part. For example, in EM1, the most significant part is based on an exact(E) adder and the least significant part is based on the mirror adder 1 (M1).For our approximate designs, a specific approximation degree, from 1 to 2n, ratherthan n, may be chosen based on the maximum error allowed for a specific application,where in [20] [21], it is mentioned that it is suitable to chose a value of 10% for MaximumED and 0.5% for MED. Figure 6 shows the ER, NMED and MRED for various 8x8array multipliers. It is clear that fully approximate multipliers have high NMED. EM5has the lowest NMED, and EM4 has a close-to-minimal NMED. Designs with high11
NMED have a high MRED too. It can be observed that EIn2 exhibits the lowest ER.Also, EX3 and EIn1 have the same close-to-minimal ER.Figure 6: ER x10 2 , NMED x10 3 and MRED x10 1 of 8x8 Array MultiplierFigure 7: Area and PDP Reduction of 8x8 Array MultiplierAs shown in Table 3 and Figure 6, there is no single design that is superior in alldesign metrics. Therefore, a Pareto-analysis for the improvements in area and PDP isshown for the different designs proposed throughout this work. X3X3 has the lowestdelay, and M5M5 and X2X2 also exhibit a low delay. M5M5, M4M4 and In2In2exhibit the lowest power consumption among the 22 different designs. The size of theapproximate multiplier exhibits a linear relationship with the degree of approximation.Thus, X2X2, In1In1 and In3In3, have the smallest size.Figure 7 shows the area and PDP reduction of 8x8 array multipliers. The bestdesigns are located on the bottom left corner. M5M5 is a Pareto-design with PDPreduction of 84% and area reduction of 65%. The design X3X3 is Non-Pareto because ithas the same area reduction as the M5M5 but with a smaller PDP reduction. However,we have to consider other error metrics. Some designs such as EX1 have increasedPDP due to excessive switching activity compared to the original design.12
Table 4: 8x8 Approximate Tree MultiplierTypeCEE4.2MREDMEDERNMEDDelay Power size(ps)(µW)0000000050821.981218CEM34.76E-016.05E 021.00E 009.30E-0353719.65912CM3M31.06E 011.41E 041.00E 002.16E-0156016.27606CEM54.76E-021.54E 029.79E-012.40E-0335618.63858CM5M55.16E-015.32E 039.99E-018.18E-0228213.99498CEX23.28E-013.68E 029.97E-015.70E-0352523.52822CX2X27.35E 008.95E 031.00E 001.38E-0151322.6426CEIn19.03E-023.10E 028.73E-014.80E-0350525.12822CIn1In15.08E-015.08E 039.75E-017.81E-0250026.894268x8 Tree MultiplierThe Wallace multiplier [22] is an efficient parallel multiplier that is composed of a treeof half adders (HAs) and FAs. The main idea is that, the adders in each layer operate inparallel without carry propagation until the generation of two rows of partial products.The design space for approximate 8x8 tree multipliers [22] is also quite large, dependingon the compressor type and approximation degree. To avoid the exponentially growingdesign space, we choose to use compressors of the same type in the multiplier design.Also, we use two options for approximation degree: i) all compressors are approximate,and ii) compressors that contribute to the lowest significant 50% of the resultant bits areapproximated to maintain an acceptable accuracy. Thus, based on the four shortlistedcompressors, explained in Section 3, we compared 8 options for approximate 8x8 treemultipliers and the results are given in Table 4. The name of the multiplier consists ofthree parts. For example, CEM1 represents a compressor based multiplier (C), wherethe most significant part is based on an exact (E) compressor and the least significantpart is composed of the mirror adder 1 (M1) based compressor. As shown in Table 4,there is no single design superior is all metrics, but some designs are the best wrt somefew metrics.Figure 8 shows the ER, NMED and MRED for various 8x8 tree multipliers. Fullyapproximate designs have higher NMED and MRED than partially approximate designs. The designs based on InX1 (CEIn1 and CIn1In1 ) exhibit the lowest ER.CM3M3 have the highest MRED. The designs based on AMA5 have the lowest delayand power consumption due to their simple structures.As depicted in Figure 9 which shows area and PDP reduction, the best designs areon the left bottom corner, i.e., CM5M5 is a Pareto-design with maximum area andmaximum PDP reduction. However, CEM5 is a non Pareto-design because it has lessreduction. Few designs on the right side of the figure have a PDP value greater thanthe exact design, which makes them unsuitable for low-power design usage.13
Figure 8: ER x10 2 , NMED x10 3 and MRED x10 1 of 8x8 Tree MultiplierFigure 9: Area and PDP Reduction of 8x8 Tree Multiplier5Higher-Order Multiplier ConfigurationThe 8x8 multiplier basic modules can be used to construct higher-order target multiplier modules. In this report, we use the example of designing a 16x16 multiplierto illustrate this process. The partial product tree of the 16x16 multiplication can bebroken down into four products of 8x8 modules, which can be executed concurrently,as shown in Figure 10.Figure 10: 16x16 MultiplierIn the case of high requirements of accuracy, an exact 8x8 multiplier can be used forthe three most significant products, i.e., AHxBH, AHxBL, and ALxBH, and any oneof the approximate designs can be used for the least significant product, i.e., ALxBL.For low accuracy requirements, only one 8x8 exact multiplier can be used for the most14
significant product, i.e., AHxBH, and any of the other approximate designs can be usedfor the three least significant products, i.e., AHxBL, ALxBH, and ALxBL. Modulesthat contribute to the lowest significant 50% of the resultant bits are approximated tomaintain accuracy as recommended by [7] [12] [19] [23].We choose to design 16x16 multipliers with an exact AHxBH multiplier, and withexact MSBs and approximate LSBs for AHxBL and ALxBH, and a fully approximate orapproximate in LSBs only ALxBL. Any other approximation degree can be found basedon the required quality function (maximum error, area, power or delay). Therefore,when the 16x16 multipliers are explained, the types of AHxBH, AHxBL and ALxBHare eliminated from the name, and only the type of ALxBL is used in the name of themultiplier.5.116x16 Array MultiplierTable 5 shows the simulation results for 16x16 approximate array multipliers, whichshows similarities with Table 3. The multiplier name is based on the type of ALxBLmodule. Figures 11, 12 and 13 show the ER, NMED and MRED for 16x16 arraymultipliers, respectively. It can be observed that 16M1M1 is the most accurate designwith the lowest ER and lowest NMED. 16EIn2 is the second accurate design with lowER and NMED. For NMED, the best designs are 16M1M1, 16EIn2 and 16In2In2.Designs with high NMED show a high MRED value. EIn1In1 and 16In3In3 have thelowest delay. Fully approximate designs exhibit the minimal delay. Generally, designsbased on approximate mirror adders have the lowest power consumption, due to theelimination of static power dissipation. Since, the design size grows linearly with the FAsize, fully approximate designs based on 6 transistors cells including 16X2X2, 16In1In1and 16In3In3 have the smallest number of transistors. Also, fully approximate designsincluding 16M5M5, 16X1X1, 16X3X3 and 16In2In2, based on 8 transistors FAs, have avery small size as well. Finally, the best designs regarding area reduction are 16In1In1,16X2X2 and 16In3In3.Figure 11: ER x10 2 of 16x16 Array MultiplierAs depicted in Figure 14 which shows the reduction in area and PDP for 16x16 arraymultipliers, the best designs are on the lower left corner, i.e., 16In1In1 and 16In3In315
Table 5: 16x16 Approximate Array MultiplierTypeMREDMEDERNMEDDelay Power 6.31E 049.44E-017.69E-10534130.1532016M1M11.71E-041.33E 031.76E-021.10E-11526118.4510416EM22.82E 021.14E 051.00E 001.82E-05533128.4494216M2M23.53E 021.33E 051.00E 002.28E-05477116.5456216EM39.53E 023.34E 051.00E 006.16E-05519131.6475316M3M39.98E 023.51E 051.00E 006.45E-05490120.4429416EM47.80E-033.36E 049.29E-015.04E-10522118.8500516M4M47.90E-033.32E 049.79E-015.11E-10506105.1465416EM58.20E-034.06E 049.34E-015.30E-10533119456416M5M58.20E-034.06E 049.34E-015.30E-10535105.1402416EX11.15E-025.22E 049.51E-017.43E-10513154.9456416X1X11.29E-025.74E 049.79E-018.34E-10520138.5402416EX29.40E 015.96E 041.00E 006.07E-06521138443816X2X21.41E 026.85E 041.00E 009.11E-06514127.4384416EX31.69E-029.09E 049.65E-011.09E-09515134456416X3X31.97E-021.05E 059.79E-011.27E-09518121.8402416EIn17.80E-034.57E E 046.09E-015.43E-10408121.7384416EIn21.60E-038.08E E 044.29E-011.42E-10500126.4402416EIn32.82E 021.14E 051.00E 001.82E-05527157.6443816In3In133.53E 021.33E 051.00E 002.28E-05412153.23844Figure 12: NMED x10 5 of 16x16 Array Multiplierare Pareto-designs while 16M4M4 is a non-Pareto design. Designs with negative PDPreduction values, indicate a power or delay larger than the exact design.16
Figure 13: MRED x10 1 of 16x16 Array MultiplierFigure 14: Area and PDP Reduction of 16x16 Array Multiplier5.216x16 Tree MultiplierTable 6 depicts the characterization for 16x16 approximate tree multipliers, which tosome degree shows similarities to Table 4. The design 16CM5M5 has the lowest powerconsumpti
5. Design target approximate multipliers: Based on di erent con gurations of 8x8 approximate multipliers, the target multiplier modules are designed and charac-terized. 6. Selection of design points: Considering the required quality constrains of a spe-ci c application, a subset of power-e cient design points is selected.
1.1 Definition, Meaning, Nature and Scope of Comparative Politics 1.2 Development of Comparative Politics 1.3 Comparative Politics and Comparative Government 1.4 Summary 1.5 Key-Words 1.6 Review Questions 1.7 Further Readings Objectives After studying this unit students will be able to: Explain the definition of Comparative Politics.
significantly simplifies the design. For the accurate 4x4 multiplier tree implementation is the same a design 1 compressor and the accu same types of circuits. Hence, on need to be used in place of the desi multiplier, two accurate compress reduction stage. (a) (b) Fig. 5. Use of compressors for parti B. 8X8 bit designs 4 H4 multipliers are used in
structures the 4x4 and 8x8 Array multiplier. Section IV details the 4x4 and 8x8 Wallace multiplier. Section V deals with high speed 4x4 as well 8x8 Vedic multiplier. Section VI comprises the introduction of MTCMOS technique. Section VII presents Comparative analysis of multipliers. Section VIII describes the Conclusion.
approximate string joins. More formally, we wish to ad-dress the following problem: Problem 1 (Approximate String Joins) Given tables 1 and # 3with string attributes 1 ,an integer ), retrieve all pairs of ecords 1 3 such that edit distance(1 0) 3) . Our techniques for approximate string processing in databases share a principlecommon .
is a query string. Approximate selections are special cases of the similarity join operation. While several predicates are introduced and benchmarked in [5], the extension of ap-proximate selection to approximate joins is not considered. Furthermore, the effect of threshold values on accuracy for approximate joins is also not considered. 3 .
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Thus, regional input-output (I-O) multipliers, which ac-count for interindustry relationships within regions, are useful tools for regional economic impact analysis. In the1970’s, theBureau of EconomicAnalysis(BEA) developed a method for estimating regional I-O multi-pliers known as RIMS (Regional Industrial Multiplier
Am I My Brother's Keeper? is a project by British artist Kate Daudy, who has transformed a large UNHCR tent; previously home to a Syrian refugee family in Jordan’s Za’atari camp into a participatory art installation focussing on the concepts of home and identity. During the year and a half she spent researching the project, Daudy visited refugee camps in Jordan. There and across Europe and .
