System-level Simulation (HW/SW Co-simulation) - Ptolemy Project
EE290A: Design of Embedded SystemASV/LL 9/10System-level simulation(HW/SW co-simulation)OutlinennProblem statementSimulation and embedded system designuuunfunctional simulationperformance simulationè POLIS implementationè partitioning exampleimplementation simulationè softwaresoftware-orientedè hardwarehardware-centricSummary1
EE290A: Design of Embedded SystemASV/LL 9/10Embedded HeterogeneousSystemGSM Phoneanalog digitaluC coreLogic RAM & ROMSHAdemodandsyncdigitalD PcontrolprotocolViterbiEqls.SAW FILTERRF tionde-intl&decoderRPE-LTPspeechdecoder40Ms/sec - 540ks/sec270.8ks/secDSP coreModeling andSimulation Techniquesexecute C code on aworkstationexecute object code usingn instruction level modeluClinstruction cycleaccuratelclock cycle accuraten HDL model of the processorRFIFDSPorASIClRTLlgate level netlistn phase accurate modeln pin accurate modeln fully functional modeln spice model of the processorn in-circuit emulatorsn some sort of C coden some sort of C coden real hardwaren frequency domain modeln behavioral HDL codebus functional modeln spice modeln RTL HDL coden real hardwareldiscrete eventn SourceModelslclock cyclebasedn SmartModelsn gate level netlistn DesignWaren Hardware Modelern real hardware2
EE290A: Design of Embedded SystemASV/LL 9/10Problem StatementnnTo model the behavior of a combined hardwareand software system based on models of thebehavior of the hardware and software componentsUsually requires trading offaccuracyè throughputè convenienceusing the right abstractions for the taskèuFunction and InterfaceAbstraction?How much visibility do I need to have inton what is going on inside a subsystemfunction abstractionn how do two subsystems communicateinterface abstraction3
EE290A: Design of Embedded SystemASV/LL 9/10OutlinennProblem statementSimulation and embedded system designuuunfunctional simulationperformance simulationè POLIS implementationè partitioning exampleimplementation simulationè softwaresoftware-orientedè hardwarehardware-centricSummaryDesign titioning)Cycle-based,logic simul.Synthesis,coding4
EE290A: Design of Embedded SystemASV/LL 9/10Functional modelVariablelength dec.FlowsplittingMPEG 2decoderMotioncomp.Stream inVideo outIDCTImagememoryVideooutputfor (i 0;i 8;i )idctrow(i);for (i 0;i 8;i )idctcol(i);Functional simulationnnnTimeless (not really coco-simulation )Algorithm exploration, functional debugging,virtual prototypingDifferent formal models:uuncontrolcontrol-dominated: CSP, EFSMs,EFSMs, DE, etc.eventevent-based: Bones, StateCharts,StateCharts, etc.data dominated: DF networkstokentoken-based: Cossap,Cossap, SPW, etc.Single process network (Ptolemy(Ptolemy-style)5
EE290A: Design of Embedded SystemASV/LL 9/10HW and SW tDesign titioning)Cycle-based,logic simul.Synthesis,coding6
EE290A: Design of Embedded SystemASV/LL 9/10Architecture modelnAbstract model for mappinguunno detailed wiring (busses, serial links, etc.)blackblack-box components (ASICs(ASICs,, micromicro-controllers, DSPs,DSPs,memories, etc.)Later refined to a detailed designuuimplement communicationrefine interfacesArchitecture modelCPU(10 SPEC)ASIC(s)(160 Mops)Memory(2Mb)bus10Mb/s7
EE290A: Design of Embedded SystemASV/LL 9/10Design titioning)Cycle-based,logic simul.Synthesis,codingMappingnnnnAssociates functional units with architectural unitsPerforms HW/SW partitioningAssociates functional communication withresources (buffers, busses, serial links, etc.)Provides estimates of performance of a givenfunction on a given architectural unit8
EE290A: Design of Embedded SystemASV/LL 9/10MappingVariablelength dec.FlowsplittingMotioncomp.Stream inVideo outIDCTCPU(10 )bus10Mb/sMappingVariablelength dec.FlowsplittingMotioncomp.Stream inVideo outIDCTCPU(10 )bus10Mb/s9
EE290A: Design of Embedded SystemASV/LL 9/10MappingVariablelength dec.FlowsplittingMotioncomp.Stream inVideo outIDCTCPU(10 )bus10Mb/sMappingVariablelength dec.FlowsplittingMotioncomp.Stream inVideo outIDCTCPU(10 )bus10Mb/s10
EE290A: Design of Embedded SystemASV/LL 9/10Another mappingVariablelength dec.FlowsplittingMotioncomp.Stream inVideo outIDCTCPU(10 )bus10Mb/sPerformance simulationnnAnalyzes performance of behavior on givenarchitectureArchitectural model provides:uuperformance estimatesresource constraintsè CPU schedulingè bus arbitration policyè (abstract) cache modeling11
EE290A: Design of Embedded SystemASV/LL 9/10OutlinennProblem statementSimulation and embedded system designuuunfunctional simulationperformance simulationè POLIS implementationè partitioning exampleimplementation simulationè softwaresoftware-orientedè hardwarehardware-centricSummaryPerformance simulationprototypenPolisHigh level specificationu Unified model for both hardware and software (CFSMs)u Code generation and estimationu Hardware synthesisunPtolemySimulation environmentu Different simulation models can coexistu Nice graphical interfaceu12
EE290A: Design of Embedded SystemASV/LL 9/10The POLIS design flowGraphical gCFSMsSw SynthesisIntfc SynthesisSw Code RTOSSimulationHw SynthesisLogic NetlistPrototypePerformance simulationin POLISBased on synthesized software timing estimatesn Generate C code for both hardware and softwarecomponentsneach statement is labeled with the estimated runningtimeu accumulate delays during execution of softwarecomponentsu use cycle based simulation for hardware componentsunVery fastThe system is compiled on the host machineu Don’t need a model of the processoru13
EE290A: Design of Embedded SystemASV/LL 9/10Performance estimationnnCurrent practice: manual guess or detailedsimulationSoftware: need restrictions on coding styleuunnstill requires lots of user inputscan be automated if software is synthesizedHardware: need RTL specification or fastbehavioral synthesisCommunication: need communication mapping(and refinement)Performance estimationBEGINdetect(c)2640T41Fa bTFENDi f ( de t e c t c ) g o t o L1;e l se got o end;L1:i f ( a b) g o t o L3;e l s e g o t o L2;L2:a a 1;g o t o L4;L3:a 0;L4:e mi t ( y ) ;63a : a 1a : 0189emit(y)L0:end: c l ean up( ) ;1414
EE290A: Design of Embedded SystemASV/LL 9/10CFSM scheduling policynConcurrency and shared resourceshardware components are concurrentu only one software component can be executed at any timeu if a software component receives an event,but the simulated processor is busy,its execution is postponedu need a scheduler to choose among all enabled softwareprocessesunDiscrete event simulation with timetime-stampedevents is used to synchronize HW and SWCar dashboard examplefuelkey, el dispfuel dispspeed dispspeed dispRPM dispRPM dispwheelengineOdoRPMCrossdispodoodo dispTiming generatorsData processingPWM drivers15
EE290A: Design of Embedded SystemASV/LL 9/10Trade-off evaluationnInteractively changed simulation parametersDefine different aspects:è Implementation of each CFSMè CPU and clock frequencyè Scheduleru May be inherited in hierarchyu Automatically transmitted to following synthesis stepsuTrade-off evaluationnHw/Sw implementation and partitioningmeeting timing constraintsu tradetrade-offs:offs: speed, code size, chip areaunScheduling policiesRound Robinu PrePre-emptive and non prepre-emptiveunCPU selectionunMC 68HC11, MC 68332, MIPS R3000Don’t need to recompile the system16
EE290A: Design of Embedded SystemASV/LL 9/10Trade-off evaluationnInput patternsImpulse, clock, randomu Sliders, buttonsu Waveforms from fileunMonitoring the systemProcessor utilization and task scheduling chartsu Missed deadlinesu Cost of implementationu Internal valuesuPerformance Hz4142040Part.11233Wheel d090050003020Partition 1: HW {Timing unit, PWM drivers) SW {Data Processing}Partition 2: HW {Timing unit} SW {Data processing, PWM drivers}Partition 3: HW {} SW {Timing unit, Data processing, PWM drivers}17
EE290A: Design of Embedded SystemASV/LL 9/10Simulation t.Graph.cycles/sec3212NoNoNoYes 20000650000550000100000Partition 1: HW {Timing unit, PWM drivers) SW {Data Processing}Partition 2: HW {Timing unit} SW {Data processing, PWM drivers}Partition 3: HW {} SW {Timing unit, Data processing, PWM drivers}Design titioning)Cycle-based,logic simul.Synthesis,coding18
EE290A: Design of Embedded SystemASV/LL 9/10Architecture refinementCPU(10 SPEC)ASIC(160 Mops)Memory(2Mb)486(66 MHz)ASIC(30 Kgates66 MHz)Memory(2Mb)bus10Mb/sPCI bus132 Mb/sArchitecture simulationnnPerformed on refined model of the architecture,ignoring behaviorSimulation verifies interface correctnessuunbusbus-functional model for processors, with randomaddress and data generation(Logic Modeling, etc.)cyclecycle-based or logic simulation for the hardwareinterfacesInterface refinement simulation(Rowson et al., Hines et al.)19
EE290A: Design of Embedded SystemASV/LL 9/10HW and SW tBus Functional Modelcmd WRTval,addrcmd WRTR2,addrcmd RDaddr,R1cmd .C/C dwrtHWcommand interpreterexecuting memory busaccess cyclesnuudrives all relevantprocessor pinsdoes not implement thecomplete instruction set ofthe processor20
EE290A: Design of Embedded SystemASV/LL 9/10Refined mappingVariablelength dec.FlowsplittingMotioncomp.Stream inVideo outIDCT486(66 MHz)ImagememoryASIC(30Kgates66 MHz)VideooutputMemory(2Mb)PCI bus132 Mb/sDesign titioning)Cycle-based,logic simul.Synthesis,coding21
EE290A: Design of Embedded SystemASV/LL 9/10Synthesis and codingnnImplement functional specification on architectureIdeally should be automated(e.g. if function for HW is specified as RTL )nIn practice generally a mix of hand design andsynthesisOutlinennProblem statementSimulation and embedded system designuuunfunctional simulationperformance simulationè POLIS implementationè partitioning exampleimplementation simulationè softwaresoftware-orientedè hardwarehardware-centricSummary22
EE290A: Design of Embedded SystemASV/LL 9/10Implementation simulationnNecessary because:uunnneed detailed performance analysishand design is errorerror-proneMost errors should have been caught beforeHow to use test vectors and compare resultsbetween different abstraction levels ?HW and SW t23
EE290A: Design of Embedded SystemASV/LL 9/10Software OrientedSW&procHWHWsoftware executing on amodel of the processorn combine program and data memory withthe processor into a single modeln implement instruction fetch, decode, andexecution cycle in opcode interpreter in softwareClock Cycle AccurateInstruction Set Architecture ModelSW&procHWclock cycleaccurateISA modelHWC/C HDLlanguageand/orsimulatorbindingmodel derived/generated fromthe instruction set descriptionADDADD R1,R2,R3R1,R2,R3{{ A1.OPA1.OP 0x010x01A1.RAA1.RA R1R1A1.RBA1.RB R2R2.}}.{{ R3 R3 - ADD(R2,R1)ADD(R2,R1) }}24
EE290A: Design of Embedded SystemASV/LL 9/10Clock Cycle AccurateInstruction Set Architecture Modelclock cycleaccurateISA modelC/C dwrtHWhardware devices hangingoff the memory busnumemory read and write cyclesare executed when specificmemory addresses are beingreferencedInstruction Cycle AccurateInstruction Set Architecture ModelSW&procHWHWsame basic idea as Clock Cycle Accurate ISAModelnuuuprocessor status can only be observed at instructioncycle boundariesusually no notion of processor pins, besides serialand parallel portscan be enhanced to drive all pins, including thememory interfaceè Clock Cycle Accurate ISA Model25
EE290A: Design of Embedded SystemASV/LL 9/10SW&procHWVirtual ProcessorHWC/C code is compiled and executed on aworkstationnunaccuracy of numeric results may be an issueHardware devices hanging off the memory busuuadditional function calls to execute memory readand write cycles when specific memory addressesare being referenced can be inserted in the originalsoftwareneed estimation and synchronization with hardwaresimulation to model software timingHW and SW t26
EE290A: Design of Embedded SystemASV/LL 9/10Hardware-Centricprogmemoryhardware executing a softwareimage stored in memoryprocHWnHWPossible descriptions of the hardwareuuuactual hardwaregate level netlistclock cycle accurate architectural descriptionprogmemoryActual HardwareprocHWHWXPLORERMS- 3X00ModelSourceXPLORERMS- 3X00ModelSourceworkstation runningHardware Modeler discrete event simulatoruuuprocessor is plugged into a device connected to aworkstationdiscrete event simulator just sees anothercomponentsoftware image is loaded into memory and clockis applied27
EE290A: Design of Embedded SystemASV/LL 9/10progmemoryGate Level NetlistprocHWHWgate level netlist executed in a discreteevent verification environmentuuexact timing of the signals at all input and outputpinsfull visibility of all internal signals and storageClock Cycle-AccurateArchitectural DescriptionprogmemoryprocHWHWarchitectural description executing ina cycle based verification environmentuumodel delivers at each clock edgea set of stable output signals givena set of stable input signalsvisibility of internal signalsand storage depends ondegree of model refinement28
EE290A: Design of Embedded SystemASV/LL 9/10SummaryFunctional modelVERIFYFUNCTIONALITYArchitecture modelVERIFYINTERFACESPerformance modelVERIFYPERFORMANCEImplementation modelVERIFYABSTRACTIONSConclusionsnnnnnAbstraction key to speedupSeparate behavior (functionality), communicationand timingArchitecture refinement essential for true coco-designand fast coco-simulationSoftware and hardware synthesis helpsperformance estimationRapid prototyping may be the ultimate cocosimulation tool.29
n Simulation and embedded system design ufunctional simulation uperformance simulation ŁPOLIS implementation Łpartitioning example uimplementation simulation Łsoftware-oriented Łhardware-centric n Summary Cycle-based, logic simul. Design flow Behavior capture Mapping (partitioning) Architecture capture Functional simul. Architecture simul .
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I Introduction to Discrete-Event System Simulation 19 1 Introduction to Simulation 21 1.1 When Simulation Is the Appropriate Tool 22 1.2 When Simulation Is Not Appropriate 22 1.3 Advantages and Disadvantages of Simulation 23 1.4 Areas of Application 25 1.5 Some Recent Applications of Simulation
1 Simulation Modeling 1 2 Generating Randomness in Simulation 17 3 Spreadsheet Simulation 63 4 Introduction to Simulation in Arena 97 5 Basic Process Modeling 163 6 Modeling Randomness in Simulation 233 7 Analyzing Simulation Output 299 8 Modeling Queuing and Inventory Systems 393 9 Entity Movement and Material-Handling Constructs 489
I Introduction to Discrete-Event System Simulation Chapter 1 Introduction to Simulation 1.1 When Simulation 1s the Appropnate Tool 1.2 When Simulation 1s Not Appropriate 1.3 Advantages and Disadvantages of Simulation 1.4 Areas of Application 1.5 Systems and System Environment 1.6 Co
4.5 Simulation result for BD generator output system for case one. 78 4.6 Simulation result for BD generator output system for case two. 79 4.7 Simulation result for MT output for case one and two 80 4.8 Simulation results of Surrette battery for two cases. 82 4.9 Simulation data of converter components for two cases. 83
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Solutions Manual Discrete-Event System Simulation Fourth Edition Jerry Banks John S. Carson II Barry L. Nelson David M. Nicol January 4, 2005. Contents 1 Introduction to Simulation 1 2 Simulation Examples 5 3 General Principles 19 4 Simulation Software 20 5 Statistical Models in Simulation 21 6 Queueing Models 36 7 Random-Number Generation 44 8 .
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