MCP4902/4912/4922 Data Sheet - Chipsmall
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MCP4902/4912/49228/10/12-Bit Dual Voltage Output Digital-to-Analog Converterwith SPI InterfaceFeaturesDescription The MCP4902/4912/4922 devices are dual 8-bit,10-bit, and 12-bit buffered voltage outputDigital-to-Analog Converters (DACs), respectively. Thedevices operate from a single 2.7V to 5.5V supply withSPI compatible Serial Peripheral Interface. The usercan configure the full-scale range of the device to beVREF or 2 * VREF by setting the Gain Selection Optionbit (gain of 1 of 2). MCP4902: Dual 8-Bit Voltage Output DACMCP4912: Dual 10-Bit Voltage Output DACMCP4922: Dual 12-Bit Voltage Output DACRail-to-Rail OutputSPI Interface with 20 MHz Clock SupportSimultaneous Latching of the Dual DACswith LDAC pinFast Settling Time of 4.5 µsSelectable Unity or 2x Gain OutputExternal Voltage Reference InputsExternal Multiplier Mode2.7V to 5.5V Single-Supply OperationExtended Temperature Range: -40 C to 125 CApplications Set Point or Offset TrimmingPrecision Selectable Voltage ReferenceMotor Control Feedback LoopDigitally-Controlled Multiplier/DividerCalibration of Optical Communication DevicesRelated Products(1)P/NDACNo. ofResolution ChannelSVoltageReference(VREF)The user can shut down both DAC channels by usingSHDN pin or shut down the DAC channel individuallyby setting the Configuration register bits. In Shutdownmode, most of the internal circuits in the shutdownchannel are turned off for power savings and the outputamplifier is configured to present a known highresistance output load (500 k typical .The devices include double-buffered registers,allowing synchronous updates of two DAC outputs,using the LDAC pin. These devices also incorporate aPower-on Reset (POR) circuit to ensure reliable powerup.The devices utilize a resistive string architecture, withits inherent advantages of low DNL error and fastsettling time. These devices are specified over theextended temperature range ( 125 C).The devices provide high accuracy and low noiseperformance for consumer and industrial applicationswhere calibration or compensation of signals (such astemperature, pressure and humidity) are 4812102MCP4822122VDD 114 VOUTA13 VREFAInternal(2.048V)The MCP4902/4912/4922 devices are available in thePDIP, SOIC and TSSOP packages.Package TypesMCP490181NC 2MCP4911101CS 3ExternalSCK 4MCP4921121MCP490282SDI 52NC 62NC 7MCP4912MCP49221012Note 1: The products listed here have similar AC/DC performances. 2010 Microchip Technology Inc.MCP49X214-Pin PDIP, SOIC, TSSOP12 VSS11 VREFB10 VOUTB9 SHDN8 LDACMCP4902: 8-bit dual DACMCP4912: 10-bit dual DACMCP4922: 12-bit dual DACDS22250A-page 1
MCP4902/4912/4922Block DiagramLDACSDICSSCKInterface LogicInputRegister AInputRegister sterDACARegisterVREF APower-onResetVREF BBufferGainLogicOutputOp AmpsOutputLogicVOUTADS22250A-page 2SHDNVOUTB 2010 Microchip Technology Inc.
MCP4902/4912/49221.0ELECTRICALCHARACTERISTICS† Notice: Stresses above those listed under “MaximumRatings” may cause permanent damage to the device.This is a stress rating only and functional operation ofthe device at those or any other conditions above thoseindicated in the operational listings of this specificationis not implied. Exposure to maximum rating conditionsfor extended periods may affect device reliability.Absolute Maximum Ratings †VDD. 6.5VAll inputs and outputs w.r.t . VSS –0.3V to VDD 0.3VCurrent at Input Pins . 2 mACurrent at Supply Pins . 50 mACurrent at Output Pins . 25 mAStorage temperature . -65 C to 150 CAmbient temp. with power applied . -55 C to 125 CESD protection on all pins 4 kV (HBM), 400V (MM)Maximum Junction Temperature (TJ). 150 CELECTRICAL CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, VDD 5V, VSS 0V, VREF 2.048V, Output Buffer Gain (G) 2x, RL 5 k toGND, CL 100 pF TA -40 to 85 C. Typical values are at 25 C.ParametersSymMinTypMaxUnitsConditionsOperating VoltageVDD2.7—5.5VOperating CurrentInput CurrentIDD—350700µA—250500µAHardware Shutdown CurrentISHDN—0.32µAPower-on Reset circuit is turnedoffSoftware Shutdown CurrentISHDN SW—3.36µAPower-on Reset circuit stays onPower-on-Reset ThresholdVPOR—2.0—VPower RequirementsVDD 5VVDD 3VVREF input is unbuffered, all digitalinputs are grounded, all analogoutputs (VOUT) are unloaded.Code 000h.DC AccuracyMCP4902Resolutionn8——BitsINL ErrorINL-1 0.1251LSbDNLDNL-0.5 0.1 0.5LSbNote 1MCP4912Resolutionn10——BitsINL ErrorINL-3.5 0.53.5LSbDNLDNL-0.5 0.1 0.5LSbNote 1MCP4922Resolutionn12——BitsINL ErrorINL-12 212LSbDNLDNL-0.75 0.2 0.75LSbNote 1VOS— 0.021% ofFSRCode 0x000hOffset ErrorNote 1:2:Guaranteed monotonic by design over all codes.This parameter is ensured by design, and not 100% tested. 2010 Microchip Technology Inc.DS22250A-page 3
MCP4902/4912/4922ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise indicated, VDD 5V, VSS 0V, VREF 2.048V, Output Buffer Gain (G) 2x, RL 5 k toGND, CL 100 pF TA -40 to 85 C. Typical values are at 25 C.ParametersSymMinTypMaxUnitsVOS/ C—0.16—ppm/ C-45 C to 25 C—-0.44—ppm/ C 25 C to 85 CgE—-0.101% ofFSR G/ C—-3—ppm/ CInput Range – BufferedModeVREF0.040—VDD – 0.040VInput Range – UnbufferedModeVREF0—VDDVInput ImpedanceRVREF—165—k Input Capacitance –Unbuffered ModeCVREF—7—pFMultiplier Mode -3 dBBandwidthfVREF—450—kHzVREF 2.5V 0.2Vp-p,Unbuffered, G 1xfVREF—400—kHzVREF 2.5V 0.2 Vp-p,Unbuffered, G 2xTHDVREF—-73—dBVREF 2.5V 0.2Vp-p,Frequency 1 kHzOutput SwingVOUT—0.01 toVDD – 0.04—VAccuracy is better than 1 LSb forVOUT 10 mV to (VDD – 40 mV)Phase Margin m—66—degreesSlew RateSR—0.55—V/µsShort Circuit CurrentISC—1524mAtsettling—4.5—µsOffset Error TemperatureCoefficientGain ErrorGain Error TemperatureCoefficientConditionsCode 0xFFFh, not including offset errorInput Amplifier (VREF Input)Multiplier Mode –Total Harmonic DistortionNote 2Code 2048VREF 0.2V p-p, f 100 Hz and1 kHzUnbuffered ModeOutput AmplifierSettling TimeWithin 1/2 LSb of final value from1/4 to 3/4 full-scale rangeDynamic Performance (Note 2)DAC-to-DAC Crosstalk—10—nV-sMajor Code Transition Glitch—45—nV-sDigital Feedthrough—10—nV-sAnalog Crosstalk—10—nV-sNote 1:2:1 LSb change around major carry(0111.1111 to 1000.0000)Guaranteed monotonic by design over all codes.This parameter is ensured by design, and not 100% tested.DS22250A-page 4 2010 Microchip Technology Inc.
MCP4902/4912/4922ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATUREElectrical Specifications: Unless otherwise indicated, VDD 5V, VSS 0V, VREF 2.048V, Output Buffer Gain (G) 2x, RL 5 k toGND, CL 100 pF. Typical values are at 125 C by characterization or simulation.ParametersSymMinTypMaxOperating VoltageVDDOperating �AVREF input is unbuffered, all digital inputs are grounded, all analogoutputs (VOUT) are unloaded.Code 000h—1.5—µAPOR circuit is turned-off—5—µAPOR circuit stays turned-on—1.85—V8——BitsPower RequirementsHardware ShutdownCurrentSoftware Shutdown Current ISHDN SWPower-On Reset thresholdVPORDC AccuracyMCP4902ResolutionnINL ErrorINL 0.25LSbDNLDNL 0.2LSbNote 1MCP4912Resolutionn10——BitsINL ErrorINL 1LSbDNLDNL 0.2LSbNote 1MCP4922Resolutionn12——BitsINL ErrorINL 4LSbDNLDNL 0.25LSbVOS— 0.02—% of FSRVOS/ C—-5—ppm/ CgE—-0.10—% of FSR G/ C—-3—ppm/ CInput Range – BufferedModeVREF—0.040 toVDD – 0.040—VInput Range – UnbufferedModeVREF0—VDDVInput ImpedanceRVREF—174—k Input Capacitance –Unbuffered ModeCVREF—7—pFOffset ErrorOffset Error TemperatureCoefficientGain ErrorGain Error TemperatureCoefficientNote 1Code 0x000h 25 C to 125 CCode 0xFFFh, not including offset errorInput Amplifier (VREF Input)Note 1:2:Note 1Code 2048,VREF 0.2V p-p, f 100 Hz and1 kHzUnbuffered modeGuaranteed monotonic by design over all codes.This parameter is ensured by design, and not 100% tested. 2010 Microchip Technology Inc.DS22250A-page 5
MCP4902/4912/4922ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED)Electrical Specifications: Unless otherwise indicated, VDD 5V, VSS 0V, VREF 2.048V, Output Buffer Gain (G) 2x, RL 5 k toGND, CL 100 pF. Typical values are at 125 C by characterization or ��kHzVREF 2.5V 0.1 Vp-p,Unbuffered, G 1xfVREF—400—kHzVREF 2.5V 0.1 Vp-p,Unbuffered, G 2xTHDVREF———dBVREF 2.5V 0.1Vp-p,Frequency 1 kHzOutput SwingVOUT—0.01 toVDD – 0.04—VAccuracy is better than 1 LSb forVOUT 10 mV to (VDD – 40 mV)Phase Margin m—66—degreesSlew RateSR—0.55—V/µsShort Circuit CurrentISC—17—mAtsettling—4.5—µsDAC to DAC Crosstalk—10—nV-sMajor Code TransitionGlitch—45—nV-sDigital Feedthrough—10—nV-sAnalog Crosstalk—10—nV-sMultiplying Mode-3 dB BandwidthMultiplying Mode – TotalHarmonic DistortionConditionsOutput AmplifierSettling TimeWithin 1/2 LSb of final value from1/4 to 3/4 full-scale rangeDynamic Performance (Note 2)Note 1:2:1 LSb change around major carry(0111.1111 to1000.0000)Guaranteed monotonic by design over all codes.This parameter is ensured by design, and not 100% tested.DS22250A-page 6 2010 Microchip Technology Inc.
MCP4902/4912/4922AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)Electrical Specifications: Unless otherwise indicated, VDD 2.7V – 5.5V, TA -40 to 125 C.Typical values are at 25 C.ParametersSymMinTypMaxUnitsSchmitt Trigger High-LevelInput Voltage (All digital inputpins)VIH0.7 VDD——VSchmitt Trigger Low-LevelInput Voltage(All digital input pins)VIL——0.2 VDDVVHYS—0.05 VDD—VInput Leakage CurrentILEAKAGE-1—1 ASHDN LDAC CS SDI SCK VREF VDD or VSSDigital Pin Capacitance(All inputs/outputs)CIN,COUT—10—pFVDD 5.0V, TA 25 C,fCLK 1 MHz (Note 1)Clock FrequencyFCLK——20MHzHysteresis of Schmitt TriggerInputsConditionsTA 25 C (Note 1)Clock High TimetHI15——nsNote 1Clock Low TimetLO15——nsNote 1tCSSR40——nsApplies only when CS falls withCLK high. (Note 1)tSU15——nsNote 1CS Fall to First Rising CLKEdgeData Input Setup TimeData Input Hold TimetHD10——nsNote 1SCK Rise to CS Rise HoldTimetCHS15——nsNote 1CS High TimetCSH15——nsNote 1LDAC Pulse WidthtLD100——nsNote 1LDAC Setup TimetLS40——nsNote 1tIDLE40——nsNote 1SCK Idle Time before CS FallNote 1:This parameter is ensured by design and not 100% tested.tCSHCStIDLEtCSSRMode 1,1tHItLOtCHSSCK Mode 0,0tSUtHDSIMSb inLSb inLDACtLSFIGURE 1-1:tLDSPI Input Timing Data. 2010 Microchip Technology Inc.DS22250A-page 7
MCP4902/4912/4922TEMPERATURE CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, VDD 2.7V to 5.5V, VSS GND.ParametersSymMinTypMaxUnitsSpecified Temperature RangeTA-40— 125 COperating Temperature RangeTA-40— 125 CStorage Temperature RangeTA-65— 150 CThermal Resistance, 14L-PDIP JA—70— C/WThermal Resistance, 14L-SOIC JA—120— C/WThermal Resistance, 14L-TSSOP JA—100— C/WConditionsTemperature RangesNote 1Thermal Package ResistancesNote 1:The MCP4902/4912/4922 devices operate over this extended temperature range, but with reducedperformance. Operation in this range must not cause TJ to exceed the maximum junction temperature of150 C.DS22250A-page 8 2010 Microchip Technology Inc.
MCP4902/4912/49222.0TYPICAL PERFORMANCE CURVESNote:The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.Note: Unless otherwise indicated, TA 25 C, VDD 5V, VSS 0V, VREF 2.048V, Gain 2x, RL 5 k , CL 100 pF.0.30.0766Absolute DNL (LSB)DNL .07540.07520.075-0.30102420483072-404096FIGURE 2-1:DNL vs. Code (MCP4922).20406080100 1200.35Absolute DNL (LSB)0.1DNL (LSB)0FIGURE 2-4:Absolute DNL vs.Temperature 0483072Code (Decimal)14096125C85CINL (LSB)0.20.10-0.1-0.2-0.3-0.42048Code (Decimal)3072124096345.5FIGURE 2-3:DNL vs. Code and VREF,Gain 1 (MCP4922). 2010 Microchip Technology Inc.45FIGURE 2-5:Absolute DNL vs. VoltageReference (MCP4922).0.310243Voltage Reference (V)0.40225CFIGURE 2-2:DNL vs. Code andTemperature (MCP4922).DNL (LSB)-20Ambient Temperature (ºC)Code (Decimal)543210-1-2-3-4-5Ambient Temperature125C010248520483072Code (Decimal)254096FIGURE 2-6:INL vs. Code andTemperature (MCP4922).DS22250A-page 9
MCP4902/4912/4922Note: Unless otherwise indicated, TA 25 C, VDD 5V, VSS 0V, VREF 2.048V, Gain 2x, RL 5 k , CL 100 pF.220INL (LSB)Absolute INL bient Temperature (ºC)30724096Code (Decimal)FIGURE 2-7:Absolute INL vs.Temperature (MCP4922).FIGURE 2-10:Note:3INL vs. Code (MCP4922).Single device graph (Figure 2-10) forillustration of 64 code effect.0.2Temp - 40oC to 125oC2.50.12DNL (LSB)Absolute INL (LSB)20481.510-0.10.501234-0.250Voltage Reference (V)FIGURE 2-8:(MCP4922).Absolute INL vs. VREF3123384512 640Code768896 10241.545.50.510INL (LSB)INL (LSB)256FIGURE 2-11:DNL vs. Code andTemperature (MCP4912).VREF2128-1-2o85 C-0.5-1.5o-31024FIGURE 2-9:(MCP4922).DS22250A-page 1020483072Code (Decimal)4096INL vs. Code and VREF- 40 Co125 C-4025 Co-2.5-3.50128256384512 640Code768896 1024FIGURE 2-12:INL vs. Code andTemperature (MCP4912). 2010 Microchip Technology Inc.
MCP4902/4912/4922Note: Unless otherwise indicated, TA 25 C, VDD 5V, VSS 0V, VREF 2.048V, Gain 2x, RL 5 k , CL 100 pF.0326496128 160 192 224 256CodeFIGURE 2-13:DNL vs. Code andTemperature (MCP4902).325315305IDD (µA)IDD Histogram (VDD 2.7V).FIGURE 2-16:0.516o14o-40 C to 85 C12Occurrence0.25INL rrenceDNL (LSB)0.0420181614121086420235Temp -40oC to 125oC2250.06010864-0.252o125 C0326496128 160Code192224400415400385370355340325310295280IDD (µA)256FIGURE 2-17:5.0V).FIGURE 2-14:INL vs. Code andTemperature (MCP4902).IDD Histogram (VDD 5.5V5.0V4.0V3.0V2.7V350IDD (µA)2652500-0.5VDD300250200-40-20FIGURE 2-15:VDD.020 40 60 80 100 120Ambient Temperature (ºC)IDD vs. Temperature and 2010 Microchip Technology Inc.DS22250A-page 11
MCP4902/4912/4922Note: Unless otherwise indicated, TA 25 C, VDD 5V, VSS 0V, VREF 2.048V, Gain 2x, RL 5 k , CL 100 pF.2-0.08VDD5.5V5.0V4.0V13.0V2.7V0.55.5VGain Error (%)ISHDN -20-40020 40 60 80 100 120Ambient Temperature (ºC)FIGURE 2-18:Hardware Shutdown Currentvs. Ambient Temperature and VDD.-20020 40 60 80 100 120Ambient Temperature (ºC)FIGURE 2-21:Gain Error vs. AmbientTemperature and VDD.6VDD45.5V5.0V44.0V33.0V2.7V2VDD1VIN Hi Threshold (V)ISHDN SW (µA)505.0V32.54.0V23.0V2.7V1.51-40-20020406080 100 120Ambient Temperature (ºC)-40FIGURE 2-19:Software Shutdown Currentvs. Ambient Temperature and VDD.-20020 40 60 80 100 120Ambient Temperature (ºC)FIGURE 2-22:VIN High Threshold vsAmbient Temperature and .02-40-20020406080100 120Ambient Temperature (ºC)FIGURE 2-20:Offset Error vs. AmbientTemperature and VDD.DS22250A-page 12VIN Low Threshold (V)1.60.1Offset Error .90.8-40-20020 40 60 80 100 120Ambient Temperature (ºC)FIGURE 2-23:VIN Low Threshold vsAmbient Temperature and VDD. 2010 Microchip Technology Inc.
MCP4902/4912/4922VDD5.5V5.0V4.0V3.0V2.7V-40 -200.0045VOUT LOW Limit 0350.0035.0V0.00254.0V3.0V2.7V0.0020.0015-40 -20020406080 100 120Ambient Temperature (ºC)FIGURE 2-24:Input Hysteresis vs. AmbientTemperature and VDD.FIGURE 2-27:VOUT Low Limit vs. AmbientTemperature and VDD.18175VREF UNBUFFERED Impedance(kOhm)5.5V 21110155-40 -20-40020 40 60 80 100 120Ambient Temperature (ºC)FIGURE 2-25:VREF Input Impedance vs.Ambient Temperature and VDD.0.0455.00.035VREF 4.04.0V0.030.0253.0V2.7V0.02VDD0.0150.01020 40 60 80 100 120Ambient Temperature (ºC)6.05.5V5.0V0.04-20FIGURE 2-28:IOUT High Short vs. AmbientTemperature and VDD.VOUT (V)VOUT HI Limit (VDD-Y)(V)VDD0.004020 40 60 80 100 120Ambient Temperature (ºC)IOUT HI SHORTED (mA)VIN SPI Hysteresis (V)Note: Unless otherwise indicated, TA 25 C, VDD 5V, VSS 0V, VREF 2.048V, Gain 2x, RL 5 k , CL 100 pF.4.0Output Shorted to VDD3.02.01.0Output Shorted to VSS0.0050.00-40 -20020 40 60 80 100 120Ambient Temperature (ºC)FIGURE 2-26:VOUT High Limit vs. AmbientTemperature and VDD. 2010 Microchip Technology Inc.02FIGURE 2-29:46810IOUT (mA)121416IOUT vs VOUT. Gain 1x.DS22250A-page 13
MCP4902/4912/4922Note: Unless otherwise indicated, TA 25 C, VDD 5V, VSS 0V, VREF 2.048V, Gain 2x, RL 5 k , CL 100 pF.VOUTVOUTSCKLDACLDACTime (1 µs/div)FIGURE 2-30:VOUT Rise Time.Time (1 µs/div)FIGURE 2-33:VOUT Rise Time.VOUTVOUTSCKSCKLDACLDACTime (1 µs/div)VOUT Fall Time.FIGURE 2-34:Shutdown.VOUTSCKLDACTime (1 µs/div)FIGURE 2-32:DS22250A-page 14VOUT Rise Time ExitRipple Rejection (dB)FIGURE 2-31:Time (1 µs/div)VOUT Rise Time.Frequency (Hz)FIGURE 2-35:PSRR vs. Frequency. 2010 Microchip Technology Inc.
MCP4902/4912/4922Note: Unless otherwise indicated, TA 25 C, VDD 5V, VSS 0V, VREF 2.50V, Gain 2x, RL 5 k , CL 100 pF.0Attenuation (dB)-2-4-6-8-10-12100FIGURE 2-36:Frequency 232348837441,000Multiplier Mode Bandwidth.-45qVREF – qVOUTD D D D D D D D D D D D D D D 0D D D D D D D D D D D D D D D -90-135-180100FIGURE 2-38:Frequency 232348837441,000Phase Shift.Note:Bandwidth (kHz)Dn GVOUTAttenuation (dB) 20 log (- 20 log (4096 )VREF )600580560540520500480460440420400G 1G 7641016Worst Case Codes (decimal)FIGURE 2-37:Codes.-3 db Bandwidth vs. Worst 2010 Microchip Technology Inc.DS22250A-page 15
MCP4902/4912/4922NOTES:DS22250A-page 16 2010 Microchip Technology Inc.
MCP4902/4912/49223.0PIN DESCRIPTIONSThe descriptions of the pins are listed in Table 3-1.TABLE 3-1:3.1PIN FUNCTION TABLEPin No.SymbolFunction1VDDSupply Voltage Input (2.7V to 5.5V)2NCNo Connection3CSChip Select Input4SCKSerial Clock Input5SDISerial Data Input6NCNo Connection7NCNo Connection8LDAC9SHDNHardware Shutdown Input10VOUTBDACB Output11VREFBDACB Reference Voltage Input (VSS to VDD)12VSSSynchronization Input. This pin is used to transfer DAC settings (Input Registers)to the output registers (VOUT)Ground reference point for all circuitry on the device13VREFADACA Reference Voltage Input (VSS to VDD)14VOUTADACA OutputSupply Voltage Pins (VDD, VSS)VDD is the positive supply voltage input pin. The inputsupply voltage is relative to VSS and can range from2.7V to 5.5V. The power supply at the VDD pin shouldbe as clean as possible for a good DAC performance.It is recommended to use an appropriate bypasscapacitor of about 0.1 µF (ceramic) to ground. Anadditional 10 µF capacitor (tantalum) in parallel is alsorecommended to further attenuate high frequencynoise present in application boards.VSS is the analog ground pin and the current return pathof the device. The user must connect the VSS pin to aground plane through a low-impedance connection. Ifan analog ground path is available in the applicationPrinted Circuit Board (PCB), it is highly recommendedthat the VSS pin be tied to the analog ground path orisolated within an analog ground plane of the circuitboard.3.2Chip Select (CS)CS is the Chip Select input, which requires an activelow signal to enable serial clock and data functions.3.3Serial Clock Input (SCK)SCK is the SPI compatible serial clock input pin.3.4Serial Data Input (SDI)3.5Latch DAC Input (LDAC)LDAC (latch DAC synchronization input) pin is used totransfer the input latch registers to their correspondingDAC registers (output latches, VOUT). When this pin islow, both VOUTA and VOUTB are updated at the sametime with their input register contents. This pin can betied to low (VSS) if the VOUT update is desired at therising edge of the CS pin. This pin can be driven by anexternal control device such as an MCU I/O pin.3.6Hardware Shutdown Input (SHDN)SHDN is the hardware shutdown input pin. When thispin is low, both DAC channels are shut down. DACoutput is not available during the shutdown.3.7Analog Outputs (VOUTA, VOUTB)VOUTA is the DAC A output pin, and VOUTB is the DACB output pin. Each output has its own output amplifier.The DAC output amplifier of each channel can drive theoutput pin with a range of VSS to VDD.3.8Voltage Reference Inputs(VREFA, VREFB)VREFA is the voltage reference input for DAC channelA, and VREFB is the reference input for DAC channel B.The reference on these pins is utilized to set thereference voltage on the string DAC. The input signalcan range from VSS to VDD. These pins can be tied toVDD.SDI is the SPI compatible serial data input pin. 2010 Microchip Technology Inc.DS22250A-page 17
MCP4902/4912/4922NOTES:DS22250A-page 18 2010 Microchip Technology Inc.
MCP4902/4912/49224.0GENERAL OVERVIEWThe MCP4902, MCP4912 and MCP4922 are dualvoltage-output 8-bit, 10-bit and 12-bit DAC devices,respectively. These devices include input amplifiers,rail-to-rail output amplifiers, reference buffers ement circuitry. The devices use an SPIserial communication interface and operate with asingle supply voltage from 2.7V to 5.5V.The DAC input coding of these devices is straightbinary. Equation 4-1 shows the DAC analog outputvoltage calculation.TABLE 4-1:VOUT ------------------------------ Gn2Where:VREFDnGnANALOG OUTPUTVOLTAGE (VOUT) VREF Dn EXternal voltage referenceDAC input codeGain Selection2 for GA bit 01 for GA bit 1DAC Resolution8 for MCP490210 for MCP491212 for MCP4922GainSelectionDevice1xVREF/2562x(2* VREF)/256MCP49121xVREF/1024(n 10)2x(2* VREF)/1024MCP49221xVREF/4096(n 12)2x(2* VREF)/4096where VREF is the external voltage reference.4.1.1DC AccuracyINL ACCURACYIntegral Non-Linearity (INL) error is the maximumdeviation between an actual code transition point andits corresponding ideal transition point, after offset andgain errors have been removed. The two end points(from 0x000 and 0xFFF) method is used for the calculation. Figure 4-1 shows the details.A positive INL error represents transition(s) later thanideal. A negative INL error represents transition(s) earlier than ideal.INL 0111110The ideal output range of each device is:(b) 0 V to 255/256 * 2 * VREF when gain setting 2x.ActualTransferFunction101 MCP4902 (n 8)(a) 0 V to 255/256 * VREF when gain setting 1x.LSb SizeMCP4902(n 8)4.1EQUATION 4-1:LSb OF EACH DEVICEDigitalInputCode MCP4912 (n 10)100011(a) 0 V to 1023/1024 * VREF when gain setting 1x.010(b) 0 V to 1023/1024 * 2 * VREF when gain setting 2x.001Ideal TransferFunction MCP4922 (n 12)000(a) 0 V to 4095/4096 * VREF when Gain setting 1x.INL 0(b) 0 V to 4095/4096 * 2 * VREF when gain setting 2x.DAC OutputNote:See the output swing voltage specificationin Section 1.0 “Electrical Characteristics”.1 LSb is the ideal voltage difference between twosuccessive codes. Table 4-1 illustrates the LSbcalculation of each device. 2010 Microchip Technology Inc.FIGURE 4-1:4.1.2Example for INL Error.DNL ACCURACYA Differential Non-Linearity (DNL) error is the measureof variations in code widths from the ideal code width.A DNL error of zero indicates that every code is exactly1 LSb wide.DS22250A-page 19
101DigitalInputCode100Ideal transferfunction011010Wide code, 1 LSbVOLTAGE REFERENCEAMPLIFIERSThe input buffer amplifiers for the MCP4902/4912/4922devices provide low offset voltage and low noise. AConfiguration bit for each DAC allows the VREF input tobypass the VREF input buffer amplifiers, achieving aBuffered or Unbuffered mode. Buffered mode providesa very high input impedance, with only minor limitationson the input range and frequency response.Unbuffered ( BUF 0) is the default configuration.Unbuffered mode provides a wide input range (0V toVDD), with a typical input impedance of 165 k with7 pF.0014.2.3DAC OutputFIGURE 4-2:4.1.3Example for DNL Accuracy.OFFSET ERRORAn offset error is the deviation from zero voltage outputwhen the digital input code is zero.4.1.4GAIN ERRORA gain error is the deviation from the ideal output,VREF– 1 LSb, excluding the effects of offset error.4.24.2.1Circuit DescriptionsOUTPUT AMPLIFIERSThe DAC’s outputs are buffered with a low-power,precision CMOS amplifier. This amplifier provides lowoffset voltage and low noise. The output stage enablesthe device to operate with output voltages close to thepower supply rails. Refer to Section 1.0 “ElectricalCharacteristics” for the analog output voltage rangeand load conditions.In addition to resistive load driving capability, theamplifier will also drive high capacitive loads withoutoscillation. The amplifier’s strong outputs allow VOUT tobe used as a programmable voltage reference in asystem.Selecting a gain of 2 reduces the bandwidth of theamplifier in Multiplying mode. Refer to Section 1.0“Electrical Characteristics” for the Multiplying modebandwidth for given load conditions.4.2.1.1The internal Power-on Reset (POR) circuit monitors thepower supply voltage (VDD) during the deviceoperation. The circuit also ensures that the DACspower-up with high output impedance ( SHDN 0,typically 500 k . The devices will continue to have ahigh-impedance output until a valid write command isperformed to either of the DAC registers and the LDACpin meets the input low threshold.If the power supply voltage is less than the PORthreshold (VPOR 2.0V, typical), the DACs will be heldin their Reset state. The DACs will remain in that stateuntil VDD VPOR and a subsequent write command isreceived.Figure 4-3 shows a typical power supply transientpulse and the duration required to cause a reset tooccur, as well as the relationship between the durationand trip voltage. A 0.1 µF decoupling capacitor,mounted as close as possible to the VDD pin, canprovide additional transient immunity.5VSupply VoltagesNarrow code, 1 LSbPOWER-ON RESET CIRCUITVPORVDD - VPORTransient DurationTime10Transient Duration (µs)000Programmable Gain BlockThe rail-to-rail output amplifier has configurable gain,allowing optimal full-scale outputs for different voltagereference inputs. The output amplifier gain has twoselections, a gain of 1x ( GA 1) or a gain of 2x( GA 0). 64Transientsabovethe2Transients0FIGURE 4-3:TA81belowthe234VDD – VPOR (V)5Typical Transient Response.The default value is a gain of 2 ( GA 0).DS22250A-page 20 2010 Microchip Technology Inc.
MCP4902/4912/49224.2.4SHUTDOWN MODEThe user can shut down each DAC channel selectivelyby using a software command or shut down all channels by using the SHDN pin. During Shutdown mode,most of the internal circuits in the channel that was shutdown are turned off for power savings. The serial interface remains active, thus allowing a write command tobring the device out of the Shutdown mode. There willbe no analog output at the channel that was shut downand the VOUT pin is internally switched to a knownresistive load (500 k typical . Figure 4-4 shows theanalog output stage during the Shutdown mode.The condition of the Power-on Reset circuit during theshutdown is as follows:a)b)Turned-off, if the shutdown occurred by theSHDN pin;On, if the shutdown occurred by the software.VOUTOpAmpPower-DownControl CircuitResistiveLoad500 k Resistive String DACFIGURE 4-4:Mode.Output Stage for ShutdownThe device will remain in Shutdown mode until theSHDN pin is brought to high or a write command with SHDN bit 1 is latched into the device. When a DACis changed from Shutdown to Active mode, the outputsettling time takes less than 10 µs, but more than thestandard active mode settling time (4.5 µs). 2010 Microchip Technology Inc.DS22250A-page 21
MCP4902/4912/4922NOTES:DS22250A-page 22 2010 Microchip Technology Inc.
MCP4902/4912/49225.0SERIAL INTERFACE5.1OverviewThe MCP4902/4912/4922 devices are designed tointerface directly with the Serial Peripheral Interface(SPI) port, which is available on many microcontrollersand supports Mode 0,0 and Mode 1,1. Commands anddata are sent to the device via the SDI pin, with databeing clocked-in on the rising edge of SCK. Thecommunications are unidirectional, thus the datacannot be read out of the MCP4902/4912/4922. TheCS pin must be held low f
Ł MCP4902: Dual 8-Bit Voltage Output DAC Ł MCP4912: Dual 10-Bit Voltage Output DAC Ł MCP4922: Dual 12-Bit Voltage Output DAC Ł Rail-to-Rail Output Ł SPI Interface with 20 MHz Clock Support Ł Simultaneous Latching of the Dual DACs with LDAC pin Ł Selectable Unity or 2x Gain Output Ł External Voltage Reference Inputs Ł External .
Herbert Wertheim College of Engineering EGN 4912 Syllabus and Registration Form Course Number and Title: EGN 4912 Engineering Undergraduate Research Catalog Description: The primary purpose of this course is to provide the student an opportunity for firsthand, supervised research. “Resea
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The Create Sheet from Symbol command is for top-down design. Once the top sheet is fully defined, this command creates the sub-sheet for the chosen sheet symbol and places matching ports on it. The Create Symbol from Sheet command is for bottom-up design, creating a sheet symbol with sheet entries based on the chosen sub-sheet. This is the mode .
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