Vivado Design Suite Tutorial: Partial Reconfiguration (UG947)
Vivado Design Suite TutorialPartial ReconfigurationUG947 (v2014.3) October 1, 2014
Revision HistoryThe following table shows the revision history for this ns to manual for Vivado Design Suite 2014.3 release:Validated with release.Updated Figures in manual to reflect displays in 2014.3 release.06/04/20142014.2Validated with release.04/02/20142014.1Revisions to manual for Vivado Design Suite 2014.1 release:Added interactive floorplanning and snap-to-grid feature, and rearrangedprocedural steps to include floorplanning.Send Feedback
Table of ContentsRevision History . 2Introduction . 5Overview . 5Software Requirements . 5Hardware Requirements . 5Tutorial Design Description . 5Lab: Partial Reconfiguration . 6Step 1: Extract the Tutorial Design Files . 6Step 2: Examine the Scripts . 6The Main Script. 6The Supporting Scripts. 7Step 3: Synthesize the Design . 8Step 4: Assemble the Design . 8Implement the Design . 8Step 5: Build the Design Floorplan . 10Step 6: Implement the First Configuration . 15Save the Results . 17Step 7: Implement the Second Configuration . 20Implement the Design . 20Save Results . 21Step 8: Examine Results . 21Use Highlighting Scripts . 21Step 9: Generate Bitstreams . 23Verify Configurations . 23Generate Bitstreams. 23Step 10: Partially Reconfigure the FPGA . 25Configure the device with a full image . 25Partially reconfigure the device. 25Conclusion . 26Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback3
Legal Notices. 27Please Read: Important Legal Notices . 27Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback4
IntroductionOverviewThis tutorial covers the Partial Reconfiguration (PR) software support in Vivado Design Suite release2014.3. The tutorial steps through basic information about the current Partial Reconfiguration (PR)design flow, example Tcl scripts, and shows results within the Vivado integrated design environment(IDE). You run scripts for part of the tutorial and work interactively with the design for other parts. Youcan also script the entire flow, and a completed script is included with the tutorial files. The focus of thistutorial is specifically the software flow from RTL to bitstream, demonstrating how to process a PartialReconfiguration design. For more information about design considerations and techniques, furtherdetails about the commands and constraints, and other aspects of building a partially reconfigurabledesign, see the Vivado Design Suite User Guide: Partial Reconfiguration (UG909).VIDEO: The Vivado Design Suite QuickTake Video Tutorial: Partial Reconfiguration in Vivadoprovides an overview of the Vivado Partial Reconfiguration solution for 7 series devices.Software RequirementsThis tutorial requires that the Vivado Design Suite 2014.3 release or later is installed.Hardware RequirementsXilinx recommends a minimum of 2 GB of RAM when using the Vivado Design Suite.This tutorial targets the Xilinx KC705 demonstration board, Rev 1.0 or 1.1.Tutorial Design DescriptionThe sample design used throughout this tutorial is called led shift count. The design targets anxc7k325t device for use on the KC705 demonstration board. This design is very small, which (1) helpsminimize data size and (2) allows you to run the tutorial quickly, with minimal hardware requirements.TIP: The software flow shown here applies to all supported devices, but the floorplanning techniquesand bit file details are specific to 7 series devices. For more details on UltraScale device requirements,see the Vivado Design Suite User Guide: Partial Reconfiguration (UG909).Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback5
Lab: Partial ReconfigurationStep 1: Extract the Tutorial Design Files1. Download the ug947-vivado-partial-reconfiguration-tutorial.zip file from the ckthrough.do?cid 363334&license RefDesLicense&filename . Extract the zip file contents to any write-accessible location. The unzipped led shift count datadirectory is referred to in this tutorial as the Extract Dir .Step 2: Examine the ScriptsStart by reviewing the scripts provided in the design archive. The files design.tcl anddesign complete.tcl are located at the root level. Both files contain the same information, butdesign.tcl has parameters set such that only synthesis runs, while design complete.tcl runsthe entire flow for two configurations.The Main ScriptIn the Extract Dir , open design.tcl in a text editor. This is the master script where you definethe design parameters, design sources, and design structure. This is the only file you have to modify tocompile a complete Partial Reconfiguration design. Find more details regarding design.tcl and theunderlying scripts in the README.txt located in the Tcl subdirectory.Note the following details in this file: Visualization scripts are requested via the use of set param hd.visual 1 (on line 5, theset param command is called in run.tcl). This command creates scripts in the root directorythat you use later in the tutorial to identify the frames to be included in the partial bitstreams. Under flow control, you can control what phases of synthesis and implementation are run. In thetutorial, only synthesis is run by the script; implementation, verification, and bitstream generationare run interactively. To run these additional steps via the script, set the flow variables (e.g.,run.prImpl) to 1. The Output Directories and Input Directories set the file structure expected for design sourcesand results files. You must reflect any changes to your file structure here.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback6
Lab: Partial Reconfiguration The Top Definition and RP Module Definitions sections allow you to reference all source files foreach part of your design. Top Definition covers all sources needed for the static design, includingconstraints and IP. The RP Module Definitions section does the same for Reconfigurable Partitions(RP). Complete a section for each RP and list all Reconfigurable Module (RM) variants for each RP.o This design has two Reconfigurable Partitions (inst shift and inst count), and eachRP has two module variants.The Configuration Definition sections define the sets of static and reconfigurable modules thatmake up a configuration.oThis design has two configurations, Config shift right count up andConfig shift left count down. You can create more configurations by adding RMsor by combining existing RMs.The Supporting ScriptsUnderneath the Tcl subdirectory, several supporting Tcl scripts exist. The scripts are called bydesign.tcl, and they manage specific details for the Partial Reconfiguration flow. Provided below aresome details about what a few of the key PR scripts do.CAUTION! Do not modify the supporting Tcl scripts. step.tclManages the current status of the design by monitoring checkpoints. synth.tclManages all the details regarding the synthesis phase. impl.tclManages all the details regarding the module implementation phase. pr impl.tclManages all the details regarding the top-level implementation of a PR design. run.tclLaunches the actual runs for synthesis and implementation. log.tclHandles report file creation at key points during the flow.Remaining scripts provide details within these scripts (such as the * utils.tcl scripts) or manageother Hierarchical Design flows (such as ooc impl.tcl).Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback7
Lab: Partial ReconfigurationStep 3: Synthesize the DesignThe design.tcl script automates the synthesis phase of this tutorial. Five iterations of synthesis arecalled, one for the static top-level design and one for each of four Reconfigurable Modules.1. Open the Vivado Tcl shell:oOn Windows, select the Xilinx Vivado desktop icon or Start All Programs Xilinx DesignTools Vivado 2014.3 Vivado 2014.3 Tcl Shell.oOn Linux, simply type, vivado -mode tcl.2. In the shell, navigate to the Extract Dir directory.3. Run the design.tcl script by entering:source design.tcl -notraceAfter all five passes through Vivado Synthesis have completed, the Vivado Tcl shell is left open. You canfind log and report files for each module, alongside the final checkpoints, under each named folder inthe Synth subdirectory.TIP: In the Extract Dir directory, multiple log files have been created: run.log shows the summary as posted in the Tcl shell window command.log echoes all the individual steps run by the script critical.log reports all critical warnings produced during the runStep 4: Assemble the DesignNow that the synthesized checkpoints for each module, plus top, are available, you can assemble thedesign. Because project support for Partial Reconfiguration flows is not yet in place, you do not use theproject infrastructure from within the IDE.You will run all flow steps from the Tcl Console, but you can use features within the IDE (such as thefloorplanning tool) for interactive events.TIP: Copy and paste commands directly from this document to avoid redundant effort and typos inthe Vivado IDE. Copy and paste only one full command at a time. Note that some commands arelong and therefore span multiple lines.Implement the Design1. Open the Vivado IDE. You can open the IDE from the open Tcl shell by typing start gui or bylaunching Vivado with the command vivado -mode gui.2. Navigate to the Extract Dir directory if you are not already there. The pwd command canconfirm this.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback8
Lab: Partial Reconfiguration3. Load the static design by issuing the following command in the Tcl Console:open checkpoint Synth/Static/top synth.dcpYou can see the design structure in the Netlist pane, but black boxes exist for the inst shift andinst count modules. Note that the Flow Navigator pane is not present. You are working in nonproject mode.TIP: Place the IDE in floorplanning mode by selecting Layout Floorplanning. Make sure theDevice view is visible.Two critical warnings are issued regarding unmatched instances. These instances are theReconfigurable Modules that have yet to be loaded, and you can therefore ignore these warningssafely.4. Load the synthesized checkpoints for first Reconfigurable Module variants for each ofreconfigurable partitions:read checkpoint -cell inst shift Synth/shift right/shift synth.dcpread checkpoint -cell inst count Synth/count up/count synth.dcpNote that the inst shift and inst count modules have been filled in with logical resources.You can now traverse the entire hierarchy within the Netlist pane.5. Define each of these submodules as partially reconfigurable by setting the HD.RECONFIGURABLEproperty:set property HD.RECONFIGURABLE 1 [get cells inst shift]set property HD.RECONFIGURABLE 1 [get cells inst count]This is the point at which the Partial Reconfiguration license is checked. If you have a valid license,you see this message:Feature available: PartialReconfigurationIf you have no license with the PartialReconfiguration feature, contact your local Xilinx salesoffice for more information. Evaluation licenses are available.6. Save the assembled design state for this initial configuration:write checkpoint ./Checkpoint/top link right up.dcpPartial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback9
Lab: Partial ReconfigurationStep 5: Build the Design FloorplanNext, you must create a floorplan to define the regions that will be partially reconfigured.1. Select the inst count instance in the Netlist pane. Right click and select Floorplanning DrawPblock and draw a tall narrow box on the left side of the X0Y3 clock region. The exact size andshape do not matter at this point, but keep the box within the clock region.Figure 1: Pblock for the inst count Reconfigurable PartitionAlthough this Reconfigurable Module only requires CLB resources, also include RAMB16, RAMB32,or DSP48 resources if the box encompasses those types. This allows the routing resources for theseblock types to be included in the reconfigurable region. The General tab of the Pblock Propertiespane can be used to add these if needed. The Statistics tab shows the resource requirements of thecurrently loaded Reconfigurable Module.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback10
Lab: Partial Reconfiguration2. In the Properties pane, select the checkbox for RESET AFTER RECONFIG. This will utilize thededicated initialization of the logic in this module after reconfiguration has completed.3. Repeat steps 1 and 2 for the inst shift instance, this time targeting the right side of clock regionX1Y1. This Reconfigurable Module includes block RAM instances, so the resource type must beincluded. If omitted, the RAMB details in the Statistics tab will be shown in red.Figure 2: Pblock for the inst shift Reconfigurable Partition4. Run Partial Reconfiguration Design Rule Checks by selecting Tools Report Report DRC. Youcan uncheck All Rules and then check Partial Reconfiguration to focus this report strictly on PRDRCs.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback11
Lab: Partial ReconfigurationFigure 3: Partial Reconfiguration Design Rule Checks (DRCs)Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback12
Lab: Partial ReconfigurationOne or two DRCs will be reported at this point, and there are two ways of resolving them. We will useone method for inst shift and the other for inst count.The first DRC will be an error, HDPR-10, reporting that RESET AFTER RECONFIG requires Pblock framealignment.5. To resolve the first DRC error, make sure that the height of the Pblock aligns with the clock regionboundaries. Using the Pblock for inst shift, stretch the top and bottom edges to match the clockregion boundaries of X1Y1 as shown in Figure 4. Note that the shading of the Pblock is now moreuniform.Figure 4: Pblock for the aligned inst shift Reconfigurable PartitionThe other possible DRC is a warning, HDPR-26, reporting that a left or right edge of a reconfigurablePblock terminates on an improper boundary. Left or right edges must not split interconnect (INT)columns. More information on this requirement can be found in the Vivado Design Suite User Guide:Partial Reconfiguration (UG909), in the section entitled Reconfigurable Partition Pblock Sizes andShapes.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback13
Lab: Partial Reconfiguration6. To manually avoid this DRC warning, zoom into the upper or lower corner on the reported edge ofinst shift (or inst count, if inst shift did not report an issue) to see where the violation has occurred.Move this edge left or right one column, as shown by the yellow arrows in Figure 5, so it landsbetween two resource types (CLB-CLB or CLB-RAMB, for example) instead landing between CLB-INTor BRAM-INT.Figure 5: Adjusting the Edges of a Reconfigurable Pblock7. Run the PR DRCs again to confirm that the errors and warnings that you have addressed have beenresolved for the inst shift instance.An alternative to manually adjusting the size and shape of reconfigurable Pblocks is to use theSNAPPING MODE feature. This feature automatically adjusts edges to align with legal boundaries. It willmake the Pblock taller, aligning with clock region boundaries, if the RESET AFTER RECONFIG feature isselected. It will make the Pblock narrower, adjusting left and/or right edges as needed. Note that thenumber and type of resources available will be altered if SNAPPING MODE makes changes to thePblock.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback14
Lab: Partial Reconfiguration8. Select the Pblock for inst count, and in the Properties tab of the Pblock Properties pane, changethe value of SNAPPING MODE from OFF to ON.Note that the original Pblock does not change. The adjustments to the Pblock needed for it toconform to PR rules are done automatically, without modifying your source constraints.9. Run the PR DRCs once again to confirm that all issues have been resolved.10. Save these Pblocks and associated properties by issuing this command in the Tcl Console:write xdc ./Sources/xdc/fplan.xdcThis will export all the current constraints in the design. These constraints can be managed in theirown XDC file, merged with another XDC file (such as top io.xdc), or managed within a run script(as is typically done with HD.RECONFIGURABLE).Now that the floorplan has been established, you will implement the design.Step 6: Implement the First ConfigurationIn this step you will place and route the design and prepare the static portion of the design for reusewith new Reconfigurable Modules.1. Load the top-level constraint file by issuing the command:read xdc Sources/xdc/top io.xdcThis sets the device pinout and top-level timing constraints. This XDC file is not accessible from theIDE – it will not appear as a design source.This top-level XDC file should only contain constraints that reference objects in the static design.Constraints for logic or nets inside of the RP can be applied for specific Reconfigurable Modules ifneeded.2. Optimize, place, and route the design by issuing the following commands:opt designplace designroute designAfter both place design and route design, examine the state of the design in the Device view(See Figure 6). One thing to note after place design is the introduction of Partition Pins. These arethe physical interface points between static and reconfigurable logic and are the replacement in Vivadofor what was Proxy Logic in ISE. They are anchor points within an interconnect tile through which eachI/O of the Reconfigurable Module must route. They appear as white boxes in the placed design view.For pblock shift, they appear in the lower right corner, as the connections to static are just outsidethe Pblock in that area of the device.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback15
Lab: Partial ReconfigurationFigure 6: Partition Pins within Placed DesignTo find these partition pins in the GUI easily:a. Select the Reconfigurable Module (e.g., inst shift) in the Netlist pane.b. Select the Cell Pins tab in the Cell Properties pane.Select any pin to highlight it, or use Ctrl A to select them all. The Tcl equivalent of the latter is:select objects [get pins inst shift/*]In the routed design view, click the Show/Hide Nets iconto display all routes by type (FullytoRouted, Partially Routed, or Unrouted), as shown in Figure 7. Use the Routing Resources icontoggle between abstracted and actual routing information, and to change the visibility of the routingresources themselves. All nets in the design are fully routed at this point.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback16
Lab: Partial ReconfigurationFigure 7: Closeup of First Configuration RoutedSave the Results3. Save the full design checkpoint and create report files by issuing these commands:write checkpoint -forceImplement/Config shift right count up/top route design.dcpreport utilization -fileImplement/Config shift right count up/top utilization.rptreport timing summary -fileImplement/Config shift right count up/top timing summary.rpt4. [Optional] Save checkpoints for each of the Reconfigurable Modules by issuing these twocommands:write checkpoint -force -cell inst shift Checkpoint/shift right route design.dcpwrite checkpoint -force -cell inst count Checkpoint/count up route design.dcpTIP: When running design complete.tcl to process the entire design in batch mode, designcheckpoints, log files, and report files are created at each step of the flow.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback17
Lab: Partial ReconfigurationAt this point, you have created a fully implemented partial reconfiguration design from which you cangenerate full and partial bitstreams. The static portion of this configuration is used for all subsequentconfigurations, and to isolate the static design, the current Reconfigurable Modules must be removed.5. Make sure routing resources are enabled, and zoom in to an interconnect tile with partition pins.6. Clear out Reconfigurable Module logic by issuing the following commands:update design -cell inst shift -black boxupdate design -cell inst count -black boxIssuing these commands results in many design changes (see Figure 8):oThe number of Fully Routed nets (green) has decreased.oinst shift and inst count now appear in the Netlist view as empty.Figure 8: The inst shift module before (top) and after (bottom) update design -black boxPartial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback18
Lab: Partial Reconfiguration7. Issue the following command to lock down all placement and routing:lock design -level routingBecause no cell was identified in the lock design command, the entire design in memory(currently consisting of the static design with black boxes) is affected. All routed nets are nowdisplayed as locked, as indicated by dashed lines (Figure 9).Figure 9: Closeup of Static-Only Design with Locked Routing8. Issue the following command to write out the remaining static-only checkpoint:write checkpoint -force Checkpoint/static route design.dcpThis static-only checkpoint would be used for any future configurations , but in this tutorial, you simplykeep this design open in memory.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback19
Lab: Partial ReconfigurationStep 7: Implement the Second ConfigurationThe static design result is now established and locked, and you will use it as context for implementingfurther Reconfigurable Modules.Implement the Design1. With the locked static design open in memory, read in post-synthesis checkpoints for the other twoReconfigurable Modules.read checkpoint -cell inst shift Synth/shift left/shift synth.dcpread checkpoint -cell inst count Synth/count down/count synth.dcp2. Optimize, place and route the new RMs in the context of static by issuing these commands:opt designplace designroute designThe design is again fully implemented, now with the new Reconfigurable Module variants. The routingis a mix of dashed (locked) and solid (new) routing segments, as shown in Figure 10.Figure 10 Second Configuration Routed, Showing Locked and New RoutesPartial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback20
Lab: Partial ReconfigurationSave Results3. Save the full design checkpoint and report files by issuing these commands:write checkpoint -forceImplement/Config shift left count down/top route design.dcpreport utilization -fileImplement/Config shift left count down/top utilization.rptreport timing summary -fileImplement/Config shift left count down/top timing summary.rpt4. [Optional] Save checkpoints for each of the Reconfigurable Modules by issuing these twocommands:write checkpoint -force -cell inst shift Checkpoint/shift left route design.dcpwrite checkpoint -force -cell inst count Checkpoint/count down route design.dcpAt this point, you have implemented the static design and all Reconfigurable Module variants. Thisprocess would be repeated for designs that have more then two Reconfigurable Modules perReconfigurable Partition.Step 8: Examine ResultsUse Highlighting ScriptsWith the routed configuration open in the IDE, run some visualization scripts to highlight tiles and nets.These scripts identify the resources allocated for partial reconfiguration, and are automaticallygenerated when the hd.visual parameter is enabled.1. In the Tcl Console, issue the following commands from the Extract Dir directory:source hd visual/pblock inst shift AllTiles.tclhighlight objects -color blue [get selected objects]2. Click somewhere in the Device view to deselect the frames (or enter unselect objects), thenissue the following commands:source hd visual/pblock inst count AllTiles.tclhighlight objects -color yellow [get selected objects]The partition frames appear highlighted in the Device view, as shown in Figure 11 below.Partial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback21
Lab: Partial ReconfigurationFigure 11: Reconfigurable Partition Frames HighlightedThese highlighted tiles represent the configuration frames that are sent to bitstream generation tocreate the partial bitstreams. In Figure 11 above, the SNAPPING MODE feature has adjusted all fouredges to account for RESET AFTER RECONFIG and legal reconfigurable partition widths.The other “tile” scripts are variations on these. If you had not created Pblocks that vertically aligned tothe clock region boundaries, the FrameTiles script would highlight the explicit Pblock tiles, while theAllTiles script extends those tiles to the full reconfigurable frame height. Note that these leave gapswhere unselected frame types (e.g., global clocks) exist.The GlitchTiles script is a subset of frame sites, avoiding dedicated silicon resources; the other scriptsare more informative than this one.Finally, the Nets scripts are created for Tandem Configuration and do not apply to PR.3. Close the current design:close projectPartial ReconfigurationUG947 (v2014.3) October 1, 2014www.xilinx.comSend Feedback22
Lab: Partial ReconfigurationStep 9: Generate BitstreamsVerify ConfigurationsRECOMMENDED: Before generating bitstreams, verify all configurations to ensure that the staticportion of each configuration match identically, so the resulting bitstreams are safe to use insilicon. The PR Verify feature examines the complete static design up to and including thepartition pins, confirming that they are identical. Placement a
Revisions to manual for Vivado Design Suite 2014.3 release: Validated with release. Updated Figures in manual to reflect displays in 2014.3 release. 06/04/2014 : 2014.2 . Validated with release. 04/02/2014 . 2014.1 : Revisions to manual for Vivado Design Suite 2014.1 release: Added interactive floorplanning and snap-to-grid feature, and rearranged
2 Vivado Partial Reconfiguration - Documentation UG909: Vivado Design Suite User Guide - Partial Reconfiguration. UG947: Vivado Design Suite Tutorial - Partial Reconfiguration. You can follow this for the Xilinx-provided ug947-vivado-partial-reconfiguration-tutorial.zip file (this is a Verilog design for
For more information about the Vivado IDE and the Vivado Design Suite flow, see: Vivado Design Suite User Guide: Using the Vivado IDE (UG893) [Ref 4] Vivado Design Suite User Guide: Design Flows Overview (UG892) [Ref 12] Simulation Flow Simulation can be applied at several points in the design flow. It is one of the first steps after .
For more information about the Vivado IDE and the Vivado Design Suite flow, see: Vivado Design Suite User Guide: Using the Vivado IDE (UG893) [Ref 3] Vivado Design Suite User Guide: Design Flows Overview (UG892) [Ref 11] Simulation Flow Simulation can be applied at several points in the design flow. It is one of the first steps after .
Vivado Design Suite 2016.2 Release Notes www.xilinx.com 5 UG973 (v2016.2) June 8, 2016 Chapter 1 Release Notes 2016.2 What's New Vivado Design Suite 2016.2 and updated UltraFast Design Methodology Guide for the Vivado Design Suite (UG949) [Ref 1] Available Now. Get Vivado Design Suite 2016.2 with support for Virtex UltraScale and Defense-Grade .
See the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for a complete list and description of the system and software requirements. Configuring MATLAB to the Vivado Design Suite Before you begin, you should verify that MATLAB is configured to the Vivado Design Suite. Do the following: 1. Configure MATLAB.
those objects, in the Xilinx Vivado Design Suite. It consists of the following: Chapter 1, Vivado Design Suite First Class Objects: Describes the various design and device objects used by the Vivado Design Suite to model the FPGA design database. Presents the objects sorted according to specific categories, with links to detailed
more information on the different design flow modes, see this link in the Vivado Design Suite User Guide: Design Flows Overview (UG892). Note: Installation, licensing, and release information is available in the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). W o r k i n g w i t h t h e V i v a d o I D E
Vivado Design Suite User Guide: Programming and Debugging, (UG908) Objectives These tutorials: Show you how to take advantage of integrated Vivado logic analyzer features in the Vivado design environment that make the debug process faster and simpler.
