Getting Started With UVM - Verilab
12/13/12 Getting Started with UVM Vanessa Cooper Verification Consultant Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 1
12/13/12 Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code What is UVM? § NOT a new language § Library of base classes § Based off previous methodologies § Accellera standard 2
12/13/12 Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code Testbench Architecture TEST Testbench: Environment Verification Component: Agent DUT Verification Component: Agent 3
12/13/12 Testbench Architecture Sequencer Driver Sequencer AHB Bus Agent Monitor Driver DUT Pipe Input Agent ACTIVE Monitor Monitor ACTIVE Pipe Output Agent PASSIVE Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 4
12/13/12 Phases build phase Builds components top-down connect phase Connects the components in the environment end of elaboration phase Post elaboration activity start of simulation phase Configuration of components before the simulation begins run phase Test Execution extract phase Collects test details after run execution check phase Checks simulation results report phase Reporting of simulation results Phases virtual function void build phase(uvm phase phase);! super.build phase(phase);! if(is active UVM ACTIVE) begin! sequencer pipe sequencer::type id::create("sequencer", this);! driver pipe driver::type id::create("driver", this);! end! monitor pipe monitor::type id::create("monitor", this);! uvm info(get full name( ), "Build phase complete", UVM LOW)! endfunction: build phase Call super.build phase first Configure before creating Create the component 5
12/13/12 Phases virtual function void connect phase(uvm phase phase);! ahb env.agent.monitor.ic port.connect(sboard.pkts coll.analysis export);! ahb env.agent.monitor.ic port.connect(coverage.analysis export);! uvm info(get full name( ), "Connect phase complete", UVM LOW)! endfunction: connect phase Sequencer Driver Scoreboard AHB Bus Agent Monitor Phases Sequences Sequencer Agent Driver DUT Monitor virtual task run phase(uvm phase phase);! fork! .! get and drive( );! .! join! endtask: run phase 6
12/13/12 Phases virtual task get and drive( );! forever begin! @(posedge vif.rst n);! while(vif.rst n ! 1'b0) begin! seq item port.get next item(req);! drive packet(req);! seq item port.item done( );! end! end! endtask: get and drive Sequencer seq item export! seq item port! virtual task drive packet(data packet pkt);! @(posedge vif.clk);! vif.data pkt.data;! endtask: drive packet Driver Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 7
12/13/12 Sequence Items class data packet extends uvm sequence item;! rand bit [15:0] data;! ! uvm object utils begin(data packet)! uvm field int(data, UVM DEFAULT)! uvm object utils end! ! function new(string name "data packet");! super.new(name);! endfunction! endclass: data packet Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 8
12/13/12 Macros and the Factory § Macros § § § Utility macros registers the class with the factory and gives access to the create method: uvm object utils and uvm component utils Field automation macros give access to common functions such as copy( ) and clone( ) : uvm field int Factory § § Substitute components Defer to run-time for object allocation Macros and the Factory ! uvm object utils begin(data packet)! uvm field int(data, UVM DEFAULT)! uvm object utils end! Macros ! class monitor extends uvm monitor;! data packet pkt;! .! pkt new("pkt");! pkt data packet::type id::create("pkt", this);! .! endclass Factory 9
12/13/12 Macros and the Factory All object::type id::set type override(derived obj::get type( ));! ! data packet::type id::set type override(short pkt::get type( )); Inst object::type id::set inst override(derived obj::get type( ), “path");! ! data packet::type id::set inst override(short pkt::get type( ), "env.agent.*"); Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 10
12/13/12 Configuration Database uvm config db#(TYPE)::set(uvm root::get( ), "*.path", "label", value); “dut intf” vif “retry count” rty cnt “my env cfg” env cfg uvm config db#(TYPE)::get(this, "", "label", value); “retry count” rty cnt Configuration Database Top dut if vif(.clk(clk),.rst n(rst n)); initial begin . uvm config db#(virtual dut if)::set(uvm root::get( ), "*", "dut intf", vif); . end static function void set(uvm component string string T cntxt, inst name, field name, value) 11
12/13/12 Configuration Database uvm config db#(virtual dut if)::get(this, "", "dut intf", vif); Monitor static function bit get( uvm component string string ref T cntxt, inst name, field name, value) Configuration Database uvm config db#(virtual dut if)::get(this, "", "dut intf", vif); Monitor if(!uvm config db#(virtual dut if)::get(this, "", "dut intf", vif)) uvm fatal("NOVIF", {"virtual interface must be set for: ", get full name( ), ".vif"}); 12
12/13/12 Configuration Database class ahb agent extends uvm agent;! uvm active passive enum is active UVM ACTIVE! ! uvm component utils begin(ahb agent)! uvm field enum(uvm active passive enum, is active, UVM ALL ON)! uvm component utils end! ! .! endclass Configure in env in test uvm config db#(int)::set(this, "env.agent", "is active", UVM PASSIVE); Create env in test env ahb env::type id::create("env", this); Create agent in env agent ahb agent::type id::create("agent", this); Configuration Database PROBLEM Reuse Monitor and Interface for Input and Output Ensure Monitor selects correct Interface Sequencer Driver DUT Pipe Input Agent Monitor ACTIVE Monitor Pipe Output Agent PASSIVE 13
12/13/12 Configuration Database Top dut if dut ivif(.clk(clk), .rst n(rst n)); dut if dut ovif(.clk(clk), .rst n(rst n)); ! initial begin . uvm config db#(virtual dut if)::set(uvm root::get( ), "*", "input dut intf",dut ivif); uvm config db#(virtual dut if)::set(uvm root::get( ), "*", "output dut intf", dut ovif); . end Configuration Database class dut monitor extends uvm monitor; virtual dut if vif; string monitor intf; . endclass: dut monitor Monitor uvm config db#(string)::set(this,"input env.agent.monitor", "monitor intf", "input dut intf"); ENV uvm config db#(string)::set(this, "output env.agent.monitor", "monitor intf", "output dut intf"); 14
12/13/12 Configuration Database “*” “input dut intf” dut ivif “*” “output dut intf” dut ovif “input env.agent.monitor” “monitor intf” “input dut intf” “output env.agent.monitor” “monitor intf” “output dut intf” Configuration Database class dut monitor extends uvm monitor; virtual dut if vif; string monitor intf; Monitor uvm config db#(string)::get(this, "", "monitor intf", monitor intf); uvm config db#(virtual dut if)::get(this, "", monitor intf, vif); . endclass: dut monitor “input env.agent.monitor” “*” “monitor intf” “input dut intf” “input dut intf” dut ivif 15
12/13/12 Configuration Database uvm config db#(virtual dut if)::set(uvm root::get( ), "*", "input dut intf",dut ivif); Top uvm config db#(virtual dut if)::set(uvm root::get( ), "*.dut agent.monitor", "input dut intf",dut ivif); Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Interfaces and Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 16
12/13/12 Connecting a Scoreboard PROBLEM What is a simple way to connect the monitors to the scoreboard? Scoreboard Sequencer Monitor DUT Pipe Agent Monitor Driver Pipe Agent Connecting a Scoreboard class dut monitor extends uvm monitor; . uvm analysis port #(data packet) items collected port; data packet data collected; data packet data clone; . endclass: dut monitor Monitor Scoreboard CLONE DATA 17
12/13/12 Connecting a Scoreboard class dut monitor extends uvm monitor; . virtual task collect packets; . cast(data clone, data collected.clone( )); items collected port.write(data clone); endtask: collect packets . endclass: dut monitor Monitor CLONE Scoreboard FIFO DATA Connecting a Scoreboard class dut scoreboard extends uvm scoreboard; . uvm tlm analysis fifo #(data packet) input packets collected; uvm tlm analysis fifo #(data packet) output packets collected; . virtual task watcher( ); forever begin @(posedge top.clk); if(input packets collected.used( ) ! 0) begin . end end endtask: watcher endclass: dut scoreboard 18
12/13/12 Connecting a Scoreboard virtual task watcher( ); forever begin @(posedge top.clk); if(input packets collected.used( ) ! 0) begin . end end endtask: watcher virtual task watcher( ); forever begin input packets collected.get(input packets); . end end endtask: watcher Connecting a Scoreboard input env.agent.monitor.items collected port.connect (scoreboard.input packets collected.analysis export); ENV output env.agent.monitor.items collected port.connect (scoreboard.output packets collected.analysis export); Monitor CLONE Scoreboard FIFO DATA 19
12/13/12 Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Interfaces and Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Interfaces and Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 20
12/13/12 Test Structure TEST Testbench: Environment Verification Component: Agent DUT Verification Component: Agent Test Structure class base test extends uvm test;! uvm component utils(base test)! ! dut env env;! dut env cfg env cfg;! ! function new(string name, uvm component parent);! super.new(name, parent);! endfunction! ! function void build phase(uvm phase phase);! super.build phase(phase);! env cfg dut env cfg::type id::create("env cfg");! ! uvm config db#(dut env cfg)::set(this, "*", "dut env cfg",! env cfg);! ! env dut env::type id::create("env", this);! endfunction! ! endclass: base test! 21
12/13/12 Test Structure class test extends base test;! uvm component utils(test)! random sequence seq;! ! function new(string name, uvm component parent);! super.new(name, parent);! endfunction! ! function void build phase(uvm phase phase);! super.build phase(phase);! endfunction! ! virtual task run phase(uvm phase phase);! phase.raise objection(this);! seq random sequence::type id::create("seq");! seq.start(env.agent.sequencer);! phase.drop objection(this);! endtask! endclass: test! Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Interfaces and Sequence Items Macros and the Factory Configuration Database Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 22
12/13/12 Sequences seq Sequencer Driver DUT Agent Monitor Sequences class random sequence extends uvm sequence #(data packet);! uvm object utils(random sequence)! ! function new(string name "random sequence");! super.new(name);! endfunction! ! virtual task body( );! uvm do(req);! endtask! ! endclass: random sequence req is a member of uvm sequence that is parameterized as data packet uvm do creates the transaction, randomizes it, and sends it to the sequencer 23
12/13/12 Sequences class constrained seq extends uvm sequence #(data packet);! uvm object utils(constrained seq)! ! function new(string name "constrained seq");! super.new(name);! endfunction! ! virtual task body( );! uvm do with(req, {req.data 16'ha;})! endtask! ! endclass: constrained seq! uvm do with further constrains sequence item members Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Interfaces and Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 24
12/13/12 Objections § Used to communicate when it is safe to end § Components or Sequences can raise or drop objections § Objections must be raised at start of a phase § Phase persists until all objections are dropped Objections virtual task run phase(uvm phase phase);! phase.raise objection(this);! seq random sequence::type id::create("seq");! seq.start(env.agent.sequencer);! phase.drop objection(this);! endtask 25
12/13/12 Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Interfaces and Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code Execution module top;! .! dut if intf(.clk(clk), .rst n(rst n));! ! initial begin! uvm config db#(virtual dut if)::set(uvm root::get( ), "*",! "dut intf", intf);! ! run test( );! end! endmodule: top UVM TESTNAME “test1” 26
12/13/12 Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Interfaces and Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code Register Model PROBLEM Use the Register Model with the pipeline AHB bus Capture read data accurately Register Model A D A P T E R Sequencer AHB Bus Agent Driver DUT Monitor 27
12/13/12 Register Model Address Phase Data Phase HCLK A HADDR B HWRITE DATA (A) HWDATA[31:0] Register Model Register Model A D A P T E R Sequencer AHB Bus Agent Driver DUT Monitor PREDICTOR 28
12/13/12 Register Model § § build phase § Create the predictor with the bus uvm sequence item parameter in your env connect phase § § § Set the predictor map to the register model map Set the predictor adapter to the register adapter Connect the predictor to the monitor Register Model ENV Declare uvm reg predictor#(ahb transfer) reg predictor; Create reg predictor uvm reg predictor#(ahb transfer):: type id::create("reg predictor", this); Map reg predictor.map master regs.default map; reg predictor.adapter reg2ahb master; ahb env.agent.monitor.item collected port. connect(reg predictor.bus in); Connect 29
12/13/12 Register Model master regs.default map.set auto predict(0); Implicit Explicit Passive Getting Started with UVM § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Interfaces and Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 30
12/13/12 Hooking to Legacy Code § § § Don’t Touch the BFM Reusable access to items in the instantiated hierarchy and module items Informing the SV testbench about the legacy BFM Hooking to Legacy Code Legacy BFM SV API UVM Testbench 31
12/13/12 Hooking to Legacy Code module SAMPLE BFM(ports to connect to DUT signals);! logic L;! task T( ); . endtask! endmodule! Need access to signal L and task T UVM TESTNAME “test1” Hooking to Legacy Code § Define a API § § § Access to the UVM testbench Access to the legacy BFM Base class with pure virtual methods § § Define in a package Derived class will implement functions 32
12/13/12 Hooking to Legacy Code package SAMPLE BFM uvm wrapper;! import uvm pkg::*;! ! virtual class SAMPLE BFM access extends uvm object;! function new(string name);! super.new(name);! endfunction! ! pure virtual function logic get L( );! pure virtual task run T( );! endclass! endpackage! Hooking to Legacy Code § § § Derive a child class and implement functions Physical hook to Legacy BFM Create class in interface 33
12/13/12 Hooking to Legacy Code interface SAMPLE BFM uvm gasket;! import SAMPLE BFM uvm wrapper::*;! ! //This class lives in the hierarchy so it can access! //signals and task by XMR.! class concrete access extends SAMPLE BFM access;! function new(string name);! super.new(name);! endfunction! ! Upwards XMR! function logic get L( );! return SAMPLE BFM.L;! endfunction! ! task run T( );! SAMPLE BFM.T( );! endtask! ! endclass! . Hooking to Legacy Code § § Assume that the interfaces will be instantiated within an instance of the legacy BFM. Any XMR in this interface that begins with the module name SAMPLE BFM will become and upwards XMR. 34
12/13/12 Hooking to Legacy Code .! concrete access ACCESS;! ! //Provide a function that will return the! //concrete access object, constructing it on demand.! function automatic SAMPLE BFM access get access( );! if (ACCESS null)! ACCESS new( sformatf("%m.ACCESS"));! return ACCESS;! endfunction! endinterface signal and task access straightforward since embedded class is in the scope of the interface get access( ) provides easy access to embedded UVM object Hooking to Legacy Code Create an instance of the interface in the hierarchy! bind SAMPLE BFM SAMPLE BFM uvm gasket uvm gasket instance( ); Reference probe class and pass to UVM testbench! module top;! import uvm pkg::*;! ! initial begin! uvm config db#(SAMPLE BFM uvm wrapper::SAMPLE BFM access)::! set(uvm root::get( ), "*",! "access gasket", BFM inst.uvm gasket instance.get access( ));! ! run test( );! end! endmodule: top 35
12/13/12 Questions? § § What is UVM? Building a Testbench § § § § § § § Creating Tests § § § § § § Testbench Architecture Phases Interfaces and Sequence Items Macros and the Factory Configuration Database Connecting a Scoreboard Test Structure Sequences Objections Execution Register Model Hooking to Legacy Code 36
Getting Started with UVM Vanessa Cooper Verification Consultant Getting Started with UVM ! What is UVM? ! Building a Testbench ! Testbench Architecture ! Phases ! Sequence Items ! Macros and the Factory ! Configuration Database ! Connecting a Scoreboard ! Creating Tests ! .
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Easier UVM is meant to be taken as a set of coding guidelines or biases. Easier UVM alone will not address every issue you are going to face as you build a complex verification environment, and for that reason, every rule in Easier UVM can have exceptions. While all the code produced from the Easier UVM
SystemVerilog, UVM, functional verification, constrained random verification, programming language, code generator ancestor methodologies, it is itself complex and challenging to learn 1. MOTIVATION . Easier UVM "version 1" was primarily educational and pedagogical, that is, to reduce UVM to a set of simple concepts and coding idioms .
Easier UVM – Functional Verification for Mainstream Designers Introducing UVM Transactions and Components Sequencers and Drivers Configurations and the Factory
User Experience with UVM Stephen D’Onofrio & Peter D’Antonio Stacking Verification Components in UVM . - Improve functional verification and ultimately product . - Easier to understand, create, and share - 2, 3 and 4 stacked UVCs .
Verification tools Universal Verification Methodology (UVM) – Class library written in SystemVerilog – Very powerful, but very complex Over 300 classes in UVM! – Grad students unlikely to have prior experience with SystemVerilog Open Source VHDL Verification Methodology (OSVVM) – Library written in VHDL – Similar to UVM
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