Easier UVM For Functional Verification By Mainstream Users
Easier UVM –Functional Verification forMainstream DesignersJohn Aynsley,DoulosCopyright 2011-2012by Doulos. All rights reserved.1
Easier UVM –Functional Verification for Mainstream Designers Introducing UVM Transactions and Components Sequencers and Drivers Configurations and the Factory What next?
Easier UVM? Aimed at mainstream Verilog & VHDL users Goal Reduce UVM to a set of simple concepts and coding idioms Easier UVM is UVM Use more features of UVM as you learn Learning UVM is still not easy.Copyright 2011-2012 by Doulos. All rights reserved.3
Why UVM?UVM Universal Verification MethodologyThe big wins are Verification quality Testbench reuse Knowhow reuseReusable verification environmentCopyright 2011-2012 by Doulos. All rights reserved.4
UVM Highlights 1 Constrained random verification Configurable, flexible, test benchesA standard approach – consistency and uniformity Open source SystemVerilog Base Class Library Supported by all the main vendorsCopyright 2011-2012 by Doulos. All rights reserved.5
UVM Highlights 2 Separation of tests from test bench Transaction-level communication (TLM) Layered sequential stimulus Message reporting Register layerCopyright 2011-2012 by Doulos. All rights reserved.6
Test versus TestbenchTest writerTests define differencesVerificationspecialistAllows for unanticipatedchangesCopyright 2011-2012 by Doulos. All rights reserved.7
Testbench StructureA consistent spatial structureuvm envuvm agentCopyright 2011-2012 by Doulos. All rights reserved.8
Quasi-static vs Dynamic ObjectsCopyright 2011-2012 by Doulos. All rights reserved.9
Quasi-static vs Dynamic ObjectsCopyright 2011-2012 by Doulos. All rights reserved.10
Quasi-static vs Dynamic ObjectsCopyright 2011-2012 by Doulos. All rights reserved.11
Quasi-static vs Dynamic Objectsclass my comp extends uvm component; uvm component utils(my comp)Pattern 1function new (string name, uvm component parent);Pattern 2super.new(name, parent);class my tx extends uvm sequence item;endfunction uvm object utils(my tx).endclassfunction new (string name "");super.new(name);endfunction.endclassCopyright 2011-2012 by Doulos. All rights reserved.12
Classes Permit Extensionsclass my tx extends uvm sequence item; uvm object utils(my tx)Original VIPfunction new (string name class refined tx extends my tx; uvm object utils(refined tx)Polymorphismfunction new (string name "");super.new(name);endfunctionsome type extra property;constraint C { . }endclassCopyright 2011-2012 by Doulos. All rights reserved.Specific test13
Transactions Methodsclass my tx extends uvm sequence item; uvm object utils(my tx)Pattern 2arand bit cmd;rand int addr;rand int data;constraint c addr { addr 0; addr 256; }constraint c data { data 0; data 256; }function new (string name "");super.new(name);endfunctionfunction string convert2string;.function void do copy( uvm object rhs );.function bit do compare( uvm object rhs, uvm comparer comparer );.endclassCopyright 2011-2012 by Doulos. All rights reserved.14
Execution PhasesA consistent temporal structureCopyright 2011-2012 by Doulos. All rights reserved.15
Phase Methods of a Componentclass my comp extends uvm component; uvm component utils(my comp)Pattern 1function new (string name, uvm component parent);super.new(name, parent);endfunctionfunction void build phase (uvm phase phase);super.build phase(phase);.endfunctionfunction void connect phase (uvm phase phase);.endfunctiontask run phase (uvm phase phase);.endtaskfunction void report phase (uvm phase phase);.endclassCopyright 2011-2012 by Doulos. All rights reserved.16
Build Phaseclass my agent extends uvm agent; uvm component utils(my agent)my driverdriv;my sequencer seqr;.function void build phase (uvm phase phase);super.build phase(phase);driv my driver::type id::create(“driv", this);drivseqrseqr my sequencer::type id::create(“seqr", this);endfunctionFactory-made componentsfunction void connect phase (uvm phase phase);b.p port.connect( c.q export );endfunctionCopyright 2011-2012 by Doulos. All rights reserved.17
Connect Phaseclass my agent extends uvm agent; uvm component utils(my agent)my driverdriv;my sequencer seqr;.function void build phase (uvm phase phase);super.build phase(phase);driv my driver::type id::create(“driv", this);drivseqrseqr my sequencer::type id::create(“seqr", this);PortendfunctionExportfunction void connect phase (uvm phase phase);driv.seq item port.connect( seqr.seq item export );endfunctionCopyright 2011-2012 by Doulos. All rights reserved.18
Transaction-Level ConnectionsPushtask put(input my tx tx);.endtaskport.put(tx);PortExportPulltask get(output my tx tx);.endtaskport.get(tx);PortExportCopyright 2011-2012 by Doulos. All rights reserved.19
Analysis PortsBroadcastfunction void write(input my tx tx);.endfunctionfunction void write(input my tx tx);.endfunctionport.write(tx);Analysis portfunction void write(input my tx tx);.endfunctionAnalysis export / impReadonly, non-blockingCopyright 2011-2012 by Doulos. All rights reserved.20
Run Phaseclass my monitor extends uvm component; uvm component utils(my monitor)uvm analysis port #(my tx) port;.function void build phase (uvm phase phase);super.build phase(phase);port new("port", this);endfunctionmontask run phase (uvm phase phase);PortchkExportmy tx tx;tx my tx::type id::create("tx");.port.write(tx);endtaskCopyright 2011-2012 by Doulos. All rights reserved.21
Constrained Random Generation Populate/randomize configuration objectsSet factory overridesTop-down buildFactory-made sequencesFactory-made transactionsConstraintsCopyright 2011-2012 by Doulos. All rights reserved.22
Agent ArchitectureAgentAgentAgentChecking andConstrained randomstimulus generationCoverageAgent-per-interfaceCopyright 2011-2012 by Doulos. All rights reserved.23
Sequence versus SequencerSequencesx countTransactionsCopyright 2011-2012 by Doulos. All rights reserved.24
SequencesFunction object can beconstrained or overriddenbody()body()body()body()Sequence of transactionsCopyright 2011-2012 by Doulos. All rights reserved.25
Transaction vs Sequenceclass my tx extends uvm sequence item; uvm object utils(my tx)Pattern 2afunction new (string name "");super.new(name);endfunction.endclassclass my seq extends uvm sequence #(my tx); uvm object utils(my seq)Pattern 2bfunction new (string name "");super.new(name);endfunctiontask body;.endtask.endclassCopyright 2011-2012 by Doulos. All rights reserved.26
Body of a SequencePattern 2bclass my seq extends uvm sequence #(my tx); uvm object utils(my seq)function new (string name "");super.new(name);endfunctiontask body;repeat (6)beginreq my tx::type id::create("req");Factory-made transactionstart item(req);Handshakewith driverassert( req.randomize() with { data 127; } );finish item(req);endendtaskLate randomizationendclassCopyright 2011-2012 by Doulos. All rights reserved.27
Sequencer – Driver – DUTSequencesTLM port-exportTransactionsVirtual interfaceSystemVerilog interfaceSystemVerilog moduleCopyright 2011-2012 by Doulos. All rights reserved.28
The Configuration DatabasesetScopeName ValueScopeName ValueScopeName Valuegetx countSequencesCopyright 2011-2012 by Doulos. All rights reserved.29
Driver 1Pattern 1class my driver extends uvm driver #(my tx); uvm component utils(my driver)virtual dut if dut vi;Driver-DUT comms via interface.function void build phase( uvm phase phase );super.build phase(phase);uvm config db #(virtual dut if)::get( this, "", "dut vi", dut vi );endfunction.Interface set using config dbCopyright 2011-2012 by Doulos. All rights reserved.30
Driver 2task run phase( uvm phase phase );foreverSequencer-driver comms via implicit portbeginseq item port.get next item(req);@(posedge dut vi.clock);dut vi.cmd req.cmd;dut vi.addr req.addr;Wiggle DUT pins through interfacedut vi.data req.data;seq item port.item done();or item done(rsp);endendtaskendclassCopyright 2011-2012 by Doulos. All rights reserved.31
Configuration Objectclass my top seq config extends uvm object;rand int count;A set of parameters / genericsrand endclassCopyright 2011-2012 by Doulos. All rights reserved.32
Populate Configuration from a TestPattern 1class my test extends uvm test; uvm component utils(my test).function void build phase (uvm phase phase);super.build phase(phase);beginmy top seq config config new;config.count 6;Could randomize the configurationuvm config db #(my top seq config)::set(this, "*.*seq*", "config", config);env top::type id::create("env", this);endcf. parameter overrides / generic mapCopyright 2011-2012 by Doulos. All rights reserved.33
Retrieve Configuration Informationclass my top seq extends uvm sequence #(my top tx);Pattern 2b uvm object utils(my top seq) uvm declare p sequencer(my top seqr)rand int count;constraint how many { count inside { [4:10] }; }.task body;my top seq config config;if ( uvm config db #(my top seq config)::get(p sequencer, "", "config", config) )count config.count; endtaskCopyright 2011-2012 by Doulos. All rights reserved.34
Factory Overridesclass my seq extends uvm sequence #(my tx); uvm object utils(my seq)Pattern 2bfunction new (string name "");super.new(name);endfunctiontask body;req my tx::type id::create("req");.endtaskendclassclass my test extends uvm test;.function void build phase (uvm phase phase);.my tx::type id::set type override( alt tx::get type() );Pattern 1my component::type id::set inst override(alt component::get type(), "subsys.*", this );.Copyright 2011-2012 by Doulos. All rights reserved.35
Start Sequence from TestPattern 1class my test extends uvm test; uvm component utils(my test).my env env;.task run phase( uvm phase phase );my top seq seq;seq my top seq::type id::create("seq");assert( seq.randomize() with { count 8; } );Randomize with constraintseq.start( env.sequencer );Start sequence on sequencerendtask.Copyright 2011-2012 by Doulos. All rights reserved.36
Running the Testmodule top;import uvm pkg::*;UVM packageimport my pkg::*;dut if dut if1 ();dutdut1 ( . if(dut if1) );SV interfaceDesign-Under-Testinitialbeginuvm config db #(virtual dut if)::set(null, "*", "dut vi", dut if1);run test();endendmoduleCopyright 2011-2012 by Doulos. All rights reserved.37
End-of-TestTest ends when allobjections droppedtask run phase(uvm phase phase);task body;@(posedge dut vi.clock);uvm test done.raise objection(this);foreverrepeat(n)beginbeginseq item port.get next item(req);req my top req::type id::create("req");phase.raise objection(this);start item(req);.assert( req.randomize() );@(posedge dut vi.clock);finish item(req);dut vi.data req.data;endphase.drop objection(this);uvm test done.drop objection(this);.endtaskendendtaskCopyright 2011-2012 by Doulos. All rights reserved.38
Summary of Coding IdiomsPattern 1class my comp extends uvm component; uvm component utils(my comp)function new(string name, uvm component parent);super.new(name, parent);endfunctionfunction void build phase(.);.endclassPattern 2aPattern 2bclass my tx extends uvm sequence item; uvm object utils(my tx)class my seq extends uvm sequence #(my tx); uvm object utils(my seq)function new (string name "");super.new(name);endfunction.endclassfunction new(string name "");super.new(name);endfunction.task body;.endclassCopyright 2011-2012 by Doulos. All rights reserved.39
Other Features of UVM Message reporting Further sequence mechanisms (lock, arbitration, sequence library) User-defined phasing Further transaction-level communication, including TLM-2.0 Printing, recording, and packing/unpacking of transactions Synchronization mechanisms (events, barriers, heartbeats) Customized reporting and report catching Command line processor The register abstraction layerCopyright 2011-2012 by Doulos. All rights reserved.40
What Next? Download m/ Download Easier UVM vm/easier uvm Future webinars from DoulosCopyright 2011-2012 by Doulos. All rights reserved.41
SystemVerilog Training PortfolioPublic ClassesNothingSystemVerilog for FPGA/ASIC DesignRTL and test benchesVerilogComprehensive SystemVerilogSV for DesignersClass-basedverificationUVM Adopter ClassCopyright 2011-2012 by Doulos. All rights reserved.42
Copyright 2011-2012 by Doulos. All rights reserved.43
Easier UVM – Functional Verification for Mainstream Designers Introducing UVM Transactions and Components Sequencers and Drivers Configurations and the Factory
Easier UVM is meant to be taken as a set of coding guidelines or biases. Easier UVM alone will not address every issue you are going to face as you build a complex verification environment, and for that reason, every rule in Easier UVM can have exceptions. While all the code produced from the Easier UVM
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SystemVerilog, UVM, functional verification, constrained random verification, programming language, code generator ancestor methodologies, it is itself complex and challenging to learn 1. MOTIVATION . Easier UVM "version 1" was primarily educational and pedagogical, that is, to reduce UVM to a set of simple concepts and coding idioms .
User Experience with UVM Stephen D’Onofrio & Peter D’Antonio Stacking Verification Components in UVM . - Improve functional verification and ultimately product . - Easier to understand, create, and share - 2, 3 and 4 stacked UVCs .
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Getting Started with UVM Vanessa Cooper Verification Consultant Getting Started with UVM ! What is UVM? ! Building a Testbench ! Testbench Architecture ! Phases ! Sequence Items ! Macros and the Factory ! Configuration Database ! Connecting a Scoreboard ! Creating Tests ! .
to express constraints, functional coverage, and to abstract the interface between the design-under-test and the class-based verification environment, the resultant set of language features is robust and sufficient for hardware verification. Keywords SystemVerilog, Verilog, UVM, functional verification, C,
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