University Of California, Davis EEC 110A* Electronics Circuits I .
1 University of California, Davis Society of Manufacturing Engineers at UC Davis EEC 110A* Electronics Circuits I Unofficial Mock Unofficial Practice Midterm Exam ia l *Disclaimer: This document is a sample final exam of an Electronics Circuits I midterm. It is a mock exam and does not necessarily reflect the format—in the length of the exam, content covered, the protocol, and other aspects—of an actual midterm exam of EEC 110A in University of California, Davis. However, this covers multiple topics that seems to be a halfway agenda of EEC 110A and this document is an attempt to give students extra practice. The problems in this document are written entirely by the author. Any similarity, either in part or in whole, is a complete coincidence. If an error is caught, or if you have any questions and inquiries, please contact the author at mnhyu@ucdavis.edu. no ffi c A calculator is not encouraged where not needed. Scoring distribution for each question is not provided as it is not graded and discourages students from judging the importance of a topic over another. Please do not physically print out this document. This examination has five (5) pages, including this front cover page and the end topology sheet. DO NOT share these documents outside of https://sme.ucdavis.edu. Please do not distribute these to other websites, including Chegg, CourseHero, Discord, Quizlet, etc. All copyrights reserved by the author. Question 1) Diode Circuits Question 2) Small Signal Model for BJTs U Question 3) Amplifier Topology By Man Yu mnhyu@ucdavis.edu. Do not print out a physical copy. Version 2 revised December 25, 2022 DO NOT distribute this document. All copyrights reserved by the author.
2 1) Plot PIN, the power dissipated by VIN, with respect to VIN using the constant voltage U no ffi c ia l model with VD,ON 1V. Label your graphs with units and important values. By Man Yu mnhyu@ucdavis.edu. Do not print out a physical copy. Version 2 revised December 25, 2022 DO NOT distribute this document. All copyrights reserved by the author.
3 2) You are not allowed to use the topology formula sheet to solve this problem. Given the circuit below with 1 PNP BJT, 1 NPN BJT, 4 capacitors, and 8 resistors, and all transistors the same temperature with VA , ia l operate in the forward active region in a) Find the transconductance of each BJT in terms of the resistor values, capacitor values, β1 (current gain of Q1), β2 (current gain of Q2), VBE (for the NPN BJT), VEB (for the PNP BJT), no ffi c VT (thermal voltage), and VCC. Do not neglect base currents. b) Using the small signal model, find VOUT/VIN in terms of gm1, gm2, rπ1, rπ2, and other resistor values in the circuit. You do not have to replace g m1 and gm2 with results from part a); instead, simply put gm1 and gm2. Assume that all capacitors are large enough so that any AC signal would short them. c) Repeat part b), but instead of gain, find input resistance and output resistance (resistance looking into VIN and VOUT, respectively). U You could use the topology formula sheet to check your work for part b) and c). By Man Yu mnhyu@ucdavis.edu. Do not print out a physical copy. Version 2 revised December 25, 2022 DO NOT distribute this document. All copyrights reserved by the author.
4 3) The saturation current of this BJT is 10-16 A, current gain is 100, Early voltage is infinite, and thermal voltage is 26 mV. Using the topology formula sheet, find a) AV VIN/VOUT, b) output resistance, ROUT, the resistance looking into VOUT, and c) input resistance, RIN, the resistance looking into VIN. U no ffi c ia l Do not neglect base currents. By Man Yu mnhyu@ucdavis.edu. Do not print out a physical copy. Version 2 revised December 25, 2022 DO NOT distribute this document. All copyrights reserved by the author.
5 Topology Sheet to (1 gmY0)(Rall(rx RB)( ia l RB a r (B HRE gre RB(iV x) no ffi c RE Common Collector Common Base ac Emitter Follower Rc vo t VB Rc Vin vo t Vin ⑳ ⑳ U vo t RE voin Vorvin g RE Ra VA D RE RE ac ac VorYWin REIT Voryvin -Rc VA g D By Man Yu mnhyu@ucdavis.edu. Do not print out a physical copy. Version 2 revised December 25, 2022 DO NOT distribute this document. All copyrights reserved by the author. RE
Mock Unofficial Practice Midterm Exam *Disclaimer: This document is a sample final exam of an Electronics Circuits I midterm. It is a mock exam and does not necessarily reflect the format—in the length of the exam, content covered, the protocol, and other aspects—of an actual midterm exam of EEC 110A in University of California, Davis.
Jun 30, 2003 · which could become explosive under certain conditions (the danger is a potential one). . though the latter could be self certified. Standards Standards must be current. This may mean, as with dust, entirely new standards. In the . 73/23/EEC 93/68/EEC 89/336/EEC 92/31/EEC 93/68/EEC 89/392/EEC 91/368/EEC 93/44/EEC 93/68/EEC 94/9/EC Ref Nos
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