Adopting Model-Based Design For FPGA, ASIC, And SoC Development

Adopting Model-Based Design for FPGA, ASIC, and SoC Development Fahd Morchid 2015 The MathWorks, Inc. 1

Agenda Why Model-Based Design for FPGA, ASIC, or SoC? Case Study – Pulse Detector HW/SW Co-Design Customer results Just an example, the workflow is the same for. 2

Agenda Why Model-Based Design for FPGA, ASIC, or SoC? Case Study – Pulse Detector HW/SW Co-Design Customer results 3

FPGA, ASIC, and SoC Development Projects 67% of ASIC/FPGA projects are behind schedule Over 50% of project time is spent on verification 75% of ASIC projects require a silicon re-spin 84% of FPGA projects have non-trivial bugs escape into production Statistics from 2018 Mentor Graphics / Wilson Research survey, averaged over FPGA/ASIC 4

Many Different Skill Sets Need to Collaborate RESEARCH RESEARCH REQUIREMENTS SPECIFICATIONS System Architecture Poor communication across teams Key decisions made in silos System-level issues found in late stages Hard to adapt to changing requirements “Rapid innovation under a rapid timeline – that’s when this flow falls apart.” SPECIFICATIONS Jamie Haas Allegro Microsystems Algorithms SPECIFICATIONS Embedded Software Digital Hardware Analog Hardware Verification System Integration 5

SoC Collaboration with Model-Based Design RESEARCH RESEARCH DESIGN System Architecture Design Elaboration Algorithms HOW am I making it? SIMULATION Implementation Architectures Export Models Generate Code Implementation Knowledge MAKE IT! Embedded Software Digital Hardware Analog Hardware Validation & Verification WHAT am I making? REQUIREMENTS Am I making the right thing? Is it going to work? Have I made it right? System Integration 6

General Approach: Use the Strengths of MATLAB and Simulink MATLAB DESIGN Simulink System Architecture Large data sets Explore mathematics Control logic Data visualization Algorithms Streaming Implementation Architectures Algorithms Streaming Hardware Architectures Fixed-Point Hardware Architectures Parallel architectures Timing Data type propagation Mixed-signal modeling Implementation Architectures 7

Agenda Why Model-Based Design for FPGA, ASIC, or SoC? Case Study – Pulse Detector HW/SW Co-Design Customer results 8

Case Study Pulse Detector 1. Example Overview 2. Reference Pulse Detector 3. Pulse Detector Design 4. Prepare for Hardware Implementation 5. Fixed-point Conversion 6. HDL code generation, synthesis and verification 9

Case Study Pulse Detector 1. Example Overview 2. Reference Pulse Detector 3. Pulse Detector Design 4. Prepare for Hardware Implementation 5. Fixed-point Conversion 6. HDL code generation, synthesis and verification 10

Pulse Detector Overview Send Reference Design (MATLAB) Receive Detector Design (Simulink) Detect Hardware Implementation (HDL) 11

Case Study Pulse Detector 1. Example Overview 2. Reference Pulse Detector 3. Pulse Detector Design 4. Prepare for Hardware Implementation 5. Fixed-point Conversion 6. HDL code generation, synthesis and verification 12

Pulse Detector Reference Design (MATLAB) Algorithm Stimulus Reference Algorithm Software Algorithm Analysis 13

Pulse Detector Reference Design (MATLAB) Reference Algorithm Algorithm Stimulus Verification “Scoreboard” Design Under Test Streaming Algorithms Streaming Hardware Architectures Fixed-Point Hardware Architectures Self-checking 14

Pulse Detector Reference Design (MATLAB) Reference Algorithm Algorithm Stimulus HDL Verifier DPI Verification “Scoreboard” HDL Verifier C DPI C Reuse MATLAB/Simulink models in verification – Scoreboard, stimulus, or models external to the RTL – Runs natively in SystemVerilog simulator – Eliminate re-work and miscommunication – Save testbench development time – Easy to update when requirements change DPI Scoreboard Scoreboard DPI C C Seq. Items Driver Design Under Test (DUT) RTL Monitor SystemVerilog verification environment 15

Pulse Detector Reference Design (MATLAB) MATLAB / Simulink Algorithm Stimulus Reference Algorithm Verification “Scoreboard” HDL Verifier cosimulation HDL Simulator DUT RTL Co-simulate with 3rd-party HDL simulator – Reuse MATLAB/Simulink test environment – Run HDL design in a supported simulator* – Generate co-simulation infrastructure and handshaking – Analyze both the design and test environment * Mentor Graphics ModelSim or Questa Cadence Incisive or XceliumTM 16

Case Study Pulse Detector 1. Example Overview 2. Reference Pulse Detector 3. Pulse Detector Design 4. Prepare for Hardware Implementation 5. Fixed-point Conversion 6. HDL code generation, synthesis and verification 17

Pulse Detector Design in Simulink Streaming Architecture 18

Pulse Detector Design in Simulink Streaming Architecture 19

Case Study Pulse Detector 1. Example Overview 2. Reference Pulse Detector 3. Pulse Detector Design 4. Prepare for Hardware Implementation 5. Fixed-point Conversion 6. HDL code generation, synthesis and verification 20

Pulse Detector Prepare for Hardware Design Micro Architecture In this step, we: prepare the model for HDL code generation pipeline the data path using various techniques add data valid control signal verify against MATLAB golden reference 21

Pulse Detector Prepare for Hardware Design Micro Architecture 22

Case Study Pulse Detector 1. Example Overview 2. Reference Pulse Detector 3. Pulse Detector Design 4. Prepare for Hardware Implementation 5. Fixed-point Conversion 6. HDL code generation, synthesis and verification 23

Pulse Detector Fixed-Point Conversion In this step, we: convert the model to fixed-point compare the Simulink fixed-point model to the MATLAB golden reference 24

Pulse Detector Fixed-Point Conversion 25

Some words about Fixed-Point conversion. 26

Fixed-Point Conversion Automated Approach 27

Fixed-Point Conversion Native Floating-Point Fixed-Point Mix Fixed- and Floating-Point Saturate on overflow HDL Coder Native Floating Point Extensive math and trigonometric operator support Optimal implementations without sacrificing numerical accuracy Mix floating- and fixed-point operations Generate target-independent HDL High dynamic range 28

Case Study Pulse Detector 1. Example Overview 2. Reference Pulse Detector 3. Pulse Detector Design 4. Prepare for Hardware Implementation 5. Fixed-point Conversion 6. HDL code generation, synthesis and verification 29

Pulse Detector HDL Code Generation and Verification In this step, we: generate HDL code and reports synthesize the design using Xilinx Vivado verify the design 30

Pulse Detector HDL Code Generation and Verification 31

Pulse Detector HDL Code Generation and Verification 32

Is there more? 33

Pulse Detector HDL Code Generation and Verification 34

Case Study Pulse Detector 1. Example Overview 2. Reference Pulse Detector 3. Pulse Detector Design 4. Prepare for Hardware Implementation 5. Fixed-point Conversion 6. HDL code generation, synthesis and verification 35

Case Study Workflow Summary Golden Reference MATLAB Hardware Architecture Fixed Point Designer Fixed-point Implementation Simulink HDL Coder HDL Code Generation and Optimization Integrated Verification HDL Verification and Targeting 36

A few more words about code generation . 37

Automatically Generate Production RTL DESIGN Algorithms Implementation Knowledge Streaming Algorithms Streaming Hardware Architectures Fixed-Point Hardware Architectures Choose from over 300 supported blocks – Including MATLAB functions and Stateflow charts Quickly explore implementation options Generate readable, traceable Verilog/VHDL Implementation Architectures HDL Coder – Optionally generate AXI interfaces with IP core Production-proven across a variety of applications and FPGA, ASIC, and SoC targets Synthesizable RTL AXI Interfaces Synthesis scripts 38

Agenda Why Model-Based Design for FPGA, ASIC, or SoC? Case Study – Pulse Detector HW/SW Co-Design Customer results 39

HW/SW Design 40

Model Based Design Workflow for SoC Deploy to Hardware with Coders and HW Support Package Algorithmic Model HDL FPGA Memory C/C Processor GPIO ADC Interconnect CAN DAC TCP/IP Algorithmic Code HW Support Package (Reference Design) PWM Hardware Platform 41

Actual Data Exchange Between FPGA and Processor FIFO size? How to synchronize incoming data with task execution? Number of buffers? Data rate? Burst size? FPGA Ts (ns) Alg1 Burst Memory Tb (us) Buffer1 Buffer2 Buffer3 Buffer4 FIFO Sample ARM Tf (ms) Frame Memory Reader Alg2 FIFO size Contention Other Memory Readers and Writers Contention Other Threads and Processes 42

SoC Blockset Model and Simulate SoC Architecture 43

SoC Blockset Model and Simulate SoC Architecture Simulate algorithms as well as hardware/software architecture Memory Internal/external connectivity I/O Task scheduling FPGA Memory Processor GPIO ADC Interconnect TCP/IP CAN Deploy on support hardware DAC TCP/IP PWM Profile performance using external mode 44

SoC Blockset Example Latency Requirements 45

SoC Blockset Workflow Summary 46

Agenda Why Model-Based Design for FPGA, ASIC, or SoC? Case Study – Pulse Detector HW/SW Co-Design Customer results 47

Results at Allegro Microsystems Link to MATLAB Expo video 48

Getting Started Collaborating with Model-Based Design RESEARCH RESEARCH REQUIREMENTS Refine algorithm toward implementation DESIGN Algorithms Implementation Architectures Implementation Knowledge Embedded Software Export Models Generate Code Digital Hardware System Integration Analog Hardware Validation & Verification System Architecture Verify refinements versus previous versions Generate verification models Add hardware implementation detail and generate optimized RTL Simulate System-on-Chip architecture Eliminate communication gaps Key decisions made via cross-skill collaboration Identify and address system-level issues before implementing subsystems Adapt to changing requirements with agility 49

Learn More Visit FPGA & SoC booth! Next steps to get started with: – – – – Verification: Improve RTL Verification by Connecting to MATLAB webinar Fixed-point quantization: Fixed-Point Made Easy webinar Incremental refinement, HDL code generation: HDL self-guided tutorial SoC Blockset: Getting Started with SoC Blockset 50

FPGA, ASIC, and SoC Development Projects 67% of ASIC/FPGA projects are behind schedule 75% of ASIC projects require a silicon re-spin Over 50% of project time is spent on verification Statistics from 2018 Mentor Graphics / Wilson Research survey, averaged over FPGA/ASIC 84% of FPGA projects have non-trivial bugs escape into production