ASIC Design And Development - INDICO-FNAL (Indico)
ASIC Design and Development Paul Rubinov 2021 All Engineers Retreat 24 Feb
The Fermilab ASIC Group Application Specific Integrated Circuits The history of ASIC design for HEP is tied to the development of Si strip detectors. The first Fermilab ASIC : QPA02 (Quad Preamp), bipolar, semi-custom First Si strip detector at CERN NA11 (1981) 60um readout pitch, 400 chan Readout 1 sq meter R. Yarema, “ASIC Design at Fermilab”, FERMILAB-Conf-91/170 2 2/24/2021 Rubinov ASIC Design and Development
Need for collider detectors drives full custom design in CMOS By 2005, Fermilab ASIC group is BUSY – 5 (!) ASIC engineers Analog and Digital Test engineers – Many projects, most in TSMC 0.25um (250nm) QIE9 DCAL RMCC TriP-t SVX4 MASDA(X) APD RO (NOvA) Going to 130nm FSSR 3 2/24/2021 Rubinov ASIC Design and Development FPIX2
Today J. Hoff C. Gingu A. Shenai C. Syal R. Wickwire (M. Hammer) S. Li T. England H. Sun X. Wang G. Drake D. Braga Q. Sun T. Zimmerman Test engineers, IT support, firmware support etc. 4 2/24/2021 Rubinov ASIC Design and Development F. Fahim Deputy Head Quantum Science Program, FQI
The power of Integrated Circuits Moore and friends – digital scaling 4in wafer 300mm wafer 5 2/24/2021 Rubinov ASIC Design and Development
Moore’s law cont. 1990: 25K for prototype run 2020: 40K for 55nm GF for 9mm2 (50 chips) wikipedia 6 2/24/2021 Rubinov ASIC Design and Development
Analog scaling 7 2/24/2021 Rubinov ASIC Design and Development P. O’Connor and G. De Geronimo Prospects for charge sensitive amplifiers in scaled CMOS NIM A 480 (2002) 713-725 Written exactly 20 yrs ago
Analog scaling cont. 8 2/24/2021 Rubinov ASIC Design and Development
ADC scaling 10 to 14 bit, 100MSPS 9 2/24/2021 FOM Power/(2 ENOB *freq) Technology Year Area (sq mm) FOM (fJ/step) 250nm 2010 4.5 344 180nm 2012 0.5 89 130nm 2012 0.24 31 65nm 2012 0.19 46 28nm 2015 0.047 13 Rubinov Engineers Week 2021
The power of Application Specific Moore’s law does not drive design decisions 10 2/24/2021 Rubinov ASIC Design and Development
Functionality Context Sensitivity 28nm 22/20nm 16/14nm GF 22FDX Overview- April 2018 Complexity
12 GF 22FDX Overview- April 2018
Need for Extreme Environments ACES 2016, F. Faccio https://indico.cern.ch/event/468486 13 2/24/2021 Rubinov ASIC Design and Development
Need for Extreme Environments 14 2/24/2021 Rubinov ASIC Design and Development
Need for Extreme Environments 15 2/24/2021 Rubinov ASIC Design and Development
Projects within the ASIC group (current, recent and near future) CMS Upgrades ECON-T and ECON-D: data concentrators for trigger and DAQ paths of HGCAL ETROC: precision timing for MIPs in the forward region using LGADs DUNE Cold electronics COLDADC: (with LBNL and BNL) 16ch, 12 bit, 2 MSPS ADC COLDATA: “Digital-on-Top” leveraging FNAL cold models. 1E-15 BER @25m and1.28gbps 65nm 16 2/24/2021 Rubinov ASIC Design and Development 22nm FD SOI
Projects within the ASIC group (current, recent and near future) Quantum projects MIDNA: readout of Skipper CCDs to allow large number of channels SNSPD: readout of Superconducting Nanowire Single Photon Detector (part of QuantISED) ACC1: Atomic Clock Control – shrinking Atomic Clocks to be chip sized (part of QuantISED) CITC1: Cryo-electronics Ion Trap control for Qubits and other quantum applications CryoADC: Collaboration with Microsoft, component for quantum computing Skipper in CMOS (R&D) : extending Skipper technology to CMOS sensors SiSeRO (R&D) : Joint development with MIT LL to extend Skipper technology to MIT-LL process Other: FALCON: High speed Xray camera for APS upgrade at ANL VIPRAM (130nm): 3D CAM (Vertically Integrated Pattern Recognition Associative Memory) 17 2/24/2021 Rubinov ASIC Design and Development
Take Home Message One Size does NOT fit all. Fermilab ASIC group is here to do apply expertise in Integrated Circuits to our Specific Applications 18 2/24/2021 Rubinov ASIC Design and Development
BACKUP 19 2/24/2021 Rubinov ASIC Design and Development
Backup: MPW prices from Europractice 20 2/24/2021 Rubinov ASIC Design and Development
BACKUP: QPA02 4 chan Gain 17mv/fC ENC 1600e @ 20pF Rise 6 ns Falltime 12ns Power 42 mw/channel QPA02 Schematic Diagram R. Yarema, “ASIC Design at Fermilab”, FERMILAB-Conf-91/170 21 2/24/2021 Rubinov ASIC Design and Development
22 2/24/2021 Rubinov ASIC Design and Development
The history of ASIC design for HEP is tied to the development of Si strip detectors. The first Fermilab ASIC : QPA02 (Quad Preamp), bipolar, semi-custom The Fermilab ASIC Group 2 2/24/2021 Rubinov ASIC Design and Development R. Yarema, "ASI Designat Fermilab", FERMILA-Conf-91/170 First Si strip detector at CERN NA11 (1981)
FPGA ASIC Trend ASIC NRE Parameter FPGA ASIC Clock frequency Power consumption Form factor Reconfiguration Design security Redesign risk (weighted) Time to market NRE Total Cost FPGA vs. ASIC ü ü ü ü ü ü ü ü FPGA Domain ASIC Domain - 11 - 18.05.2012 The Case for FPGAs - FPGA vs. ASIC FPGAs can't beat ASICs when it comes to Low power
FPGA, ASIC, and SoC Development Projects 67% of ASIC/FPGA projects are behind schedule 75% of ASIC projects require a silicon re-spin Over 50% of project time is spent on verification Statistics from 2018 Mentor Graphics / Wilson Research survey, averaged over FPGA/ASIC 84% of FPGA projects have non-trivial bugs escape into production
ASIC vs. FPGA ASIC Performance Range FPGA ormance Time ormance Planning Deployment Superiority Depends Development First Use Time mance ASIC Superiority FPGA Superiority Under heavy change First Use Requirement lock to decommission is over a decade (as long as Azure itself has existed)
3 FPGA, ASIC, and SoC Development Projects 67% of ASIC/FPGA projects are behind schedule 75% of ASIC projects require a silicon re-spin Over 50% of project time is spent on verification Statistics from 2018 Mentor Graphics / Wilson Research survey, averaged over FPGA/ASIC 84% of FPGA projects have non-trivial bugs escape into production
ASIC or FPGA with few RTL code changes when migrating between FPGAs and ASIC, whereas the others embedded processors like Blackfin, MicroBlaze and PowerPC are proprietary and are not available in the ASIC technology. By using IP cores from Opencores to design a SoC, designer are able to prototype their system on FPGA platform with ASIC .
Certificate Program (GCP) in ASIC Design and Verification (ADV). ASIC stands for "Application Specific Integrated Circuit". It refers to a digital silicon chip designed and optimized for a small range of functions. ASIC Design and Verification courses have long been a strong feature of our MS offerings in ECE.
ASIC Careers uide. 9. Reconciliation Action . Plan Officer. Aaron Collins. Aaron is ASIC's Reconciliation Action Plan (RAP) Officer in . the People and Development team. What makes ASIC unique is its approach to acceptance and curiosity. I am incredibly proud of the way we embrace diversity and inclusion.
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