Power Management For VLSI Circuits
University of TorontoPower Management for VLSICircuitsFarid N. NajmUniversity of Torontof.najm@utoronto.ca
Outline The Power Problem Impact, issues, objectives, trendsTechnology Trends and ProjectionsHistorical trends (since 1960) Future projections (up to 2020) EDA for Power ManagementLow-level power models Power estimation and optimization High-level power models Bottom-up Top-down ConclusionFMCAD-07Power Management for VLSI Circuits2
The Power Problem High frequency and chip density lead to high powerToday’s microprocessors consume 100-150 W Future microprocessors may consume over 200 W Power has an impact on: System performance (battery life)Chip performance (circuit speed)Packaging and cooling (cost)Signal integrity: Inductive kick (Ldi/dt), IR drop, noise, etc.Physical reliability: Electromigration, hot-carriers, etc.Power is a problem in both portable & fixed equipmentFMCAD-07Power Management for VLSI Circuits3
Impact on Performance Power dissipation affects chip speed in two ways:Power supply (voltage) variations (IR drop, Ldi/dt drop) Temperature variations Power supply reduction causes a circuit to slow down A 5% reduction in Vdd may cause a 15% increase in gate delayIncreased temperature has acomplex effect on speedTraditionally: slow down Today: gates speed-up, wires slow down V drop -IddVddId Overallresult depends on the “mix” Speed-up is not necessarily a goodthing, due to thermal runawayFMCAD-07Power Management for VLSI Circuits4
Cooling/Packaging Cost Tj TaR th PavgTjTaEnergy FMCAD-07Power Management for VLSI Circuits5
Impact on Signal Integrity Power supply current transientscause:Inductive kick due to Ldi/dt IR drop due to line resistance Ldi/dtIddVdd IdLeads to supply voltage glitchesand signal integrity problems:Glitches get coupled to sensitiveanalog or mixed signal nodes Can cause dynamic circuits to loosecharge Can cause latches to change state FMCAD-07Power Management for VLSI Circuits6
Impact on Chip Reliability ICs are subject to a variety ofphysical failure mechanisms:Electromigration (EM) Hot-carrier degradation (HC) OtherElectromigration Damage Voiding in metal1 due to electronwind from right-to-left through via.Reliability is worse under:High switching activity High temperature Result: chip MTF is reducedunder high power conditionsFMCAD-07Power Management for VLSI Circuits7
Power ddCn C pCpVddCpnCnCtotVdd2ddQhlVddCtotVCtotVdd2(average energy per logic transition)CtotVdd2 f(average power at frequency: f )12 Average power depends on: FMCAD-07pswitching frequencysupply voltage (squared)transistor or gate count (C)Power Management for VLSI Circuits8
Bottom Line Power has become a primary design concern As part of a low-power design methodology, tools areneeded to accomplish several tasks: Power Modeling and Characterization Levels:MOSFET, gate, cell, macro, core, memory, IO Objectives: static, average, RMS, peak power Power Estimation (Analysis) At Power Optimization (Synthesis) At all levels and for all objectivesall levels and for all objectivesHigh-level tools are highly desirableFMCAD-07Power Management for VLSI Circuits9
Power Depends on Workload Power, much more so than delay, depends on whatstimulus is applied to the circuit, i.e., power is:Pattern-dependent Mode-dependent Workload-dependent Example: Running MS-Word on a laptop requires muchless power than running a 3D video gameFor power estimation, reasonable accuracy is possibleonly when the mode of operation is understoodFMCAD-07Power Management for VLSI Circuits10
Power Analysis Objectives Different power objectives: Transient power (waveform over time) v.s. average power Usetransient power for IR drop, power bus sizing, signalintegrity, physical reliability, etc.Sometimes, only interested in peak power May be interested only in highest current slope Useaverage power for package selection, battery life, temperatureanalysis, etc.P(t) Static power v.s. dynamic powertIt is possible to talk about the transient static power,and the average static power Static power is pattern-dependent (it’s not exactly DC)FMCAD-07Power Management for VLSI Circuits11
Dynamic Power Dynamic power is consumedwhen signals areswitching, and is due to:Short-circuit current, also calledcrowbar, or rush-through current Current to charge internal nodes Current required to charge outputand loading capacitance Best understood as dynamicenergy per transitionFMCAD-07Power Management for VLSI Circuits12
Static PowerStatic power consists of: 40002000191715013Standby current (sneakpaths, pull-ups, trickledevices, sense-amplifiers)600011 80009 100007 Sub-threshold currentGate oxide leakagepn-junction leakage5 120003Off-current (leakage)140001 16000Number of Vectors Leakage Power (x 2.3 nW)In CMOS, leakage can be large: 1996: 100 MHz DSP core: 10%1998: 600 MHz Alpha uP: 2W/72W2002: 90nm FPGA: 10W2006: 65nm 2-core Itanium: 40%Future: 50% ?FMCAD-07Leakage, being exponential inVth, is the key reason why Vddwill not scale any more!Power Management for VLSI Circuits13
Outline The Power Problem Impact, issues, objectives, trendsTechnology Trends and ProjectionsHistorical trends (since 1960) Future projections (up to 2020) EDA for Power ManagementLow-level power models Power estimation and optimization High-level power models Bottom-up Top-down ConclusionFMCAD-07Power Management for VLSI Circuits14
Moore’s Law Empirical observation by Gordon Moore, 1965: “the number of transistorson a chip [for minimum component cost] doubles about every two years” This exponential trend has fueled economic expansion on a global scale Very few things in nature are “exponential”Things cannot grow exponentially forever!Source: Power Management for VLSI Circuits15
Microprocessor Performance10,000100IntelDECGate 64A21164II21066MPC750604604 10Pentium Pro601, 603 (R)Pentium(R)100Gate Delays/ ClockProcessor freqscales by 2X pergenerationIBM Power 0Source: IntelFMCAD-07Power Management for VLSI Circuits16
1998 DEC Alpha 21264Average Power Dissipation8070Power (W)605040302010000.35 , 2.2VRth 0.3 C/W2W at DC, mostly leakageMax 95W at 600MHzFMCAD-07100200300400500600Frequency (MHz)72 W, 33 A, at 600 MHz15.2 Million Transistors, 3.14 cm2Power Management for VLSI Circuits17
1998 DEC Alpha 21264Power Breakdown at 600 MHz5% 2%8%Global Clock Network32%10%Instruction Issue UnitsCachesFloating Execution UnitsInteger Execution Units10%Memory Management UnitI/OMiscellaneous Logic15%FMCAD-0718%Power Management for VLSI Circuits18
Intel uPs, Maximum Power50Pentium-IIPower (W)4030Pentium Pro20PentiumPentium/MMX10386 wer Management for VLSI Circuits19
Processors Reported in ISSCC1000Power (W)1001010.10.0119801985199019952000YearSource: T. Sakurai, ICCAD-02 TutorialFMCAD-07Power Management for VLSI Circuits20
Intel uPs, Power Density (1999)1000Rocket Nozzle( 2016)Nuclear Reactor( 2008)Watts/cm2100Pentium IVPentium IIIPentium IIHot Plate( 1996)10Pentium 0.13u0.1u0.07uProcess GenerationsSource: F. J. Pollack, “New microarchitecture challenges in the coming generations of CMOS process technologies,” 32nd Annual ACM/IEEEInternational Symposium on Microarchitecture (Micro32), Haifa, Israel, p. 2, 1999. (Plenary Presentation)FMCAD-07Power Management for VLSI Circuits21
Intel Leakage Trend (2000)250120%Active Power200Leakage100%Power (Watts)80%15060%10040%5020%00%TechnologySource (Intel paper): Kam, Rawat, Kirkpatrick, Roy, Spirakis, Sherwani andPeterson, “EDA challengesfacing future microprocessor design”, IEEE Transactions on Computer-Aided Design, Vol. 19, No. 12,December 2000.FMCAD-07Power Management for VLSI Circuits22
IBM Leakage Trend (2002)1000100Active-powerdensity?Power (W/cm2)1010.10.01Subthreshold-powerdensityE.J. Nowak. Maintaining the benefits ofCMOS scaling when scaling bogs down.Volume 46, Numbers 2/3, Page 169(2002)0.0010.000110-50.010.11Gate Length (um)FMCAD-07Power Management for VLSI Circuits23
Intel di/dt Trend (2000)1.E 08di/dt in AU1.E 071.E 061.E 051.E 041.E 031.E 021.E 01PentiumPro (R)Pentium(R)3864861.E 00Source (Intel paper): Kam, Rawat, Kirkpatrick, Roy, Spirakis, Sherwani andPeterson, “EDAchallenges facing future microprocessor design”, IEEE Transactions on Computer-Aided Design, Vol.19, No. 12, December 2000.FMCAD-07Power Management for VLSI Circuits24
Outline The Power Problem Impact, issues, objectives, trendsTechnology Trends and ProjectionsHistorical trends (since 1960) Future projections (up to 2020) EDA for Power ManagementLow-level power models Power estimation and optimization High-level power models Bottom-up Top-down ConclusionFMCAD-07Power Management for VLSI Circuits25
Feature Size160DRAM 1/2 pitchMPU/ASIC M1 1/2 2020YearsSource: ITRS-05 & 06, http://public.itrs.net.FMCAD-07Power Management for VLSI Circuits26
FunctionalityMPU cost-perfMPU perfASICDRAM100000100010000100010100DRAM Giga-bits/chipMillion YearsSource: ITRS-05 & 06, http://public.itrs.net.FMCAD-07Power Management for VLSI Circuits27
SpeedLocal Clock Frequency (GHz)100101200020052010201520202025YearsSource: ITRS-05 & 06, http://public.itrs.net.FMCAD-07Power Management for VLSI Circuits28
Power Dissipation 0650302000Maximum Power (Mobile) (W)Maximum Power (Desktop) (W)High-perf02005201020152020YearsSource: ITRS-03, http://public.itrs.net.FMCAD-07Power Management for VLSI Circuits29
Power Dissipation 06Maximum Power (Mobile) (W)Maximum Power (Desktop) (W)20050302000020052010201520202025YearsSource: ITRS-06, http://public.itrs.net.FMCAD-07Power Management for VLSI Circuits30
Supply Voltage1.4High-performance1.2Low powerSupply Voltage ce: ITRS-05 & 06, http://public.itrs.net.FMCAD-07Power Management for VLSI Circuits31
Max Supply Current (ITRS-03)High-perfCost-perfMobile4502040018Max Total Current (A)1430012250102008150610045002002Max Total Current (Mobile) sFMCAD-07Power Management for VLSI Circuits32
Max Supply Current (ITRS-06)35020High-perfCost-perfMobile18Max Total Current (A)1625014122001015086100Max Total Current (Mobile) ower Management for VLSI Circuits33
Chip PadsMPU TotalMPU P/G (2/3)ASIC TotalASIC P/G (1/2)70006000Pad YearsSource: ITRS-05 & 06, http://public.itrs.net.FMCAD-07Power Management for VLSI Circuits34
Outline The Power Problem Impact, issues, objectives, trendsTechnology Trends and ProjectionsHistorical trends (since 1960) Future projections (up to 2020) EDA for Power ManagementLow-level power models Power estimation and optimization High-level power models Bottom-up Top-down ConclusionFMCAD-07Power Management for VLSI Circuits35
The Language of Power Power modeling, estimation, and optimization methodshave been in development since the late 80sA specialized terminology has developed signal probability, static probability, transitionprobability, entropy, state probability, conditional probabilityswitching activity, transition density, transition activity, togglerate, activity factorspatial correlation, temporal correlation, spatio-temporalcorrelation, pair-wise correlation, correlation factorsindependence, conditional independence, lag-one modelbottom-up, top-down models, cycle-accuratemodel, compactionetc .FMCAD-07Power Management for VLSI Circuits36
Basics In order to introduce basic power concepts, it is helpfulto consider the case of a single CMOS logic gateThe static power, Ps , for a given input vector, is theconstant power dissipated by the gate in steady statewhen that vector is applied Due to “off-current” (leakage)The dynamic energy, Ed , for a given input (ordered)pair of vectors is the energy dissipated in the gate dueto that vector transition.Includes short-circuit, internal charging, and external chargingcurrents Energy QV CV2 is measured in Joules, 1 J 1 Watt-second FMCAD-07Power Management for VLSI Circuits37
Avoid Double-Counting During a transition, we must avoid mixing up the staticand dynamic components; here’s one way of doing this:vdd (t )vdd (t )idd (t )Edidd (t )Ps 2Ps1WEtotFMCAD-07EdPs1 Ps 22WPower Management for VLSI Circuits38
Power Vector Set Power dissipation is well defined in connection with agiven input vector sequence, called a power vector setLet Tpvs be the time duration of this vector set, then: Transient power waveform is given by:Average static power is given by:Average dynamic power is given by:FMCAD-07vdd (t )idd (t )1TpvsT pvs1TpvsPower Management for VLSI CircuitsPs (t )dt0Ed (i )i39
Signal Statistics Define: Indicator Function Ix(t) of a signal x(t) : Ix(t) is 1 when x(t) is at logic highIx(t) is 0 when x(t) is at logic lowIx(t) changes value instantaneously halfway through thetransition window duration WDefine: Signal Probability of a signal x(t) as the fractionof time during which x(t) is high; formally:T1P( x) P( x;0, Tpvs )I x (t )dtTpvs 0pvs The signal probability is a non-negative dimensionlessreal number between 0 and 1.FMCAD-07Power Management for VLSI Circuits40
Switching Activity Define: Switching Activity of a signal x(t) as the averagenumber of logic transitions per unit time; formally:R( x) Tpvswhere Nx(0, t) is the number of (complete) logictransitions of the signal between 0 and t.Other names for the switching activity: R ( x;0, T pvs )N x (0, T pvs )switching rate, toggle rate, activity factor, transitionactivity, and transition densityThe switching activity is a non-negative real numberwith units of transitions per secondFMCAD-07Power Management for VLSI Circuits41
Outline The Power Problem Impact, issues, objectives, trendsTechnology Trends and ProjectionsHistorical trends (since 1960) Future projections (up to 2020) EDA for Power ManagementLow-level power models Power estimation and optimization High-level power models Bottom-up Top-down ConclusionFMCAD-07Power Management for VLSI Circuits42
Single Gate Power Consider a gate with output node x, and let the staticpower when x is low (high) be Ps0 (Ps1), then theAverage Static Power is:Pavg , s1Ps1T pvsPs1 P ( x) T pvsT pvsI x (t ) dtPs 00(1 I x (t ))dt0Ps 0 1 P ( x)Let Ed be the dynamic energy per transition, then theAverage Dynamic Power is:Ed N x (0, Tpvs )Pavg ,dEd R ( x )TpvsFMCAD-07Power Management for VLSI Circuits43
Different Rise/Fall Energies If the dynamic energy on a low to high transition is Ed,01and is different from the dynamic energy on a high tolow transition Ed,10 , then: If the initial state of the node is low, the expression for averagedynamic power becomes:Pavg ,dEd ,01 N x (0, Tpvs ) 2TpvsEd ,01 Ed ,102 Ed ,10 N x (0, Tpvs ) 2R( x)It is enough to talk about the average of Ed,01 and Ed,10 as theaverage dynamic energy per transition, EdFMCAD-07Power Management for VLSI Circuits44
Power and Capacitance Let us ignore the internal power of a gate and focus onthe energy required to switch the output (drain andinterconnect) capacitance:VddCtotQlhCn C pCnVddQlhQlhhlEd ,01 Ed ,10EdQhl12QhlQlhVddCpnCnCtotVddQhlVdd2tot ddC VCtotVdd2Pavg ,dFMCAD-07CpVddp12CtotVdd2 R( x)Power Management for VLSI Circuits45
Clocked Circuits If the circuit is clocked, then it becomes convenient andnatural to normalize by the clock period Let T be the clock period, and let Tpvs NT, and lett0 0, t1 T, t2 2T, , tN NT Tpvs , then:P( x) P( x;0, Tpvs )1NNP( x; ti 1 , ti )i 1Thus, the signal probability is equal to the averagefraction of a cycle in which the signal is high.FMCAD-07Power Management for VLSI Circuits46
Clocked Circuits Switching activity is best normalized by the clockfrequency, leading to a revised definition :D( x) D( x;0, )1NNN x (ti 1 , ti )i 1Thus, the (normalized) switching activity is the averagenumber of transitions per cycle, which is a dimensionless nonnegative real numberThe two definitions are related by:D( x) T R( x) And the average dynamic power is now given by:Pavg ,dFMCAD-07Ed R( x)Ed D( x) fPower Management for VLSI Circuits47
The Zero-Delay Case If all gates have zero-delay, then:1 NP( x) P( x;0, Tpvs )I x (i )N i1where Ix(i) is the indicator function evaluated at any timeduring (but not at the start of) cycle i So, the signal probability becomes: the average fraction ofcycles in which the signal has a final value of logic high. In this case, we also have:D( x) Pt ( x) where Pt(x) is the transition probability of x(t), defined as: theaverage fraction of clock cycles in which the final value of thesignal is different from its initial valueFMCAD-07Power Management for VLSI Circuits48
Outline The Power Problem Impact, issues, objectives, trendsTechnology Trends and ProjectionsHistorical trends (since 1960) Future projections (up to 2020) EDA for Power ManagementLow-level power models Power estimation and optimization High-level power models Bottom-up Top-down ConclusionFMCAD-07Power Management for VLSI Circuits49
Power Estimation At a low-level, power estimation requires computationof the node switching activity R(x) or D(x) A major difficulty is: pattern-dependenceThe obvious solution approach is to use simulation:Simulate a power-vector set to measure the toggle count Combine with capacitance information to compute the power Disadvantages: simulation is slow and expensiveMany attempts have been made to develop “static”techniques to compute the power without simulation:Analytical (probabilistic) methods Monte Carlo (statistical) methods FMCAD-07Power Management for VLSI Circuits50
Analytical Techniques Propagate switching activity directly on the netlistKey result: transition density propagation:x1x2xn Logic GateorBoolean Functionf(x)yD( y )Pi 1yD( xi )xiThe partial derivative is the Boolean difference:xi nf ( x)f ( x) xi0f ( x) xi1Probability computation is possible using a BDDFMCAD-07Power Management for VLSI Circuits51
Analytical Techniques A key assumption: inputs are uncorrelatedIn practice, signals are often correlated, in complex ways It is impractical to keep track of signal correlation As a result, overall, these methods are inaccurateTotal large circuit accuracy within 10% Local error can be much larger Limited use:Inside an optimization loop Incremental analysis FMCAD-07Power Management for VLSI Circuits52
Monte Carlo Techniques Randomly select and simulate (only) short vectorsequences, from a large power-vector setUse Monte Carlo theory to converge on themean, which is the average powerAlthough more accurate, these methods have notdisplaced the simple simulation based approachDealing with unknown circuit state is a complication The power vector set can itself be viewed as a collection of“samples” and can be chosen small enough to simulate The method of choice today remains simulation, andthat remains unsatisfactoryFMCAD-07Power Management for VLSI Circuits53
Low-Power Synthesis Incorporate power as an objective during synthesis Practical experience shows that doing this during logicsynthesis is not very effectiveThis refers to standard logic synthesis, employing Booleanoptimizations followed by technology mapping Once a circuit has been optimized for area, there is only 5-10%further improvement to be had by further power optimization It is generally agreed that optimizations at
FMCAD-07 Power Management for VLSI Circuits 3 The Power Problem High frequency and chip density lead to high power Today’s microprocessors consume 100-150 W Future microprocessors may consume over 200 W Power has an impact on: System performance (battery life) Chip performance (circuit speed) Packaging and cooling (cost) Signal
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