FPGA Construction: The Art Behind It

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FPGA Construction:The Art behind itArun VeeramaniNational Instruments1

Outline Digital design fundamentalsWhat is FPGA?Steps for constructing FPGATesting the design VHDL basics2

Digital Design Fundamentals Building blocks for ALL LOGIC ?Input A Input BNAND GateOutput0010111011103

Single Bit Adder Half Adder Sum (not A).B A.(not B)Carry A.BInput AInput BCarrySum00000101100111105

Single Bit Adder Full 1010010111010001101101101011111CinSum6

Four Bit Adder Cascade Four Single Bit Full AddersA3C4B3A2C3S3B2A1A0C1C2S2B1B0C0S1S0Quiz: Propagation Delay ?7

What is an FPGA? What it is Field-programmable gate array A silicon chip with unconnected gates User can define and re-definefunctionality How it works Define behavior in software Compile and download to the hardware Hardware implementation of code When it is used Custom hardware or ICs, replacement forASICs Reconfiguration required afterdeployment9

FPGA Hardware FabricInterconnectIOBLogic Elements arebasic buildingblocks of an FPGAand can beprogrammed tocarry out differentfunction as requiredby the ntLogicElementInterconnectswire differentlogic cellstogether to formmore complexdesign connectInput/Output Block connect internalFPGA architecture to the externaldesign via interfacing pinsNote: Precise architecture of an FPGA various frommanufacturers to manufacturers.Every manufacturers has different version of a specific FPGA;basically increasing the number of logic cells.10

Active Interconnect Powerful S1SliceS0 Fully buffered Fast, predictable 8 LUTs 128b distributed RAM Wide input functions (32:1) Support for slice-based multipliersBlock RAM 18KBit TrueDual-Port Up to 3 Mbitsper deviceSliceS2BRAMMultipliers 18b x 18b multiplier 200 MHz pipelinedTypical FPGA Architecture (Xilinx Virtex II & Virtex II Pro)11

Development StagesFour development stages MULATE12SIMULATE

Step #1: Design Schematic captureGraphical depiction Easy to understand Vendor specific Ex: ViewDraw, Ease Hardware Description languages (HDL)Text based – “Firmware” Generic or vendor specific Ex: VHDL, Verilog 13

HDL Styles StructuralSoftware equivalent of schematic capture Uses vendor specific components Repeat design process for different vendors BehavioralDescribe digital functions in generic terms Vendor independent 14

Step #2: Simulate Verification of code Simulate after each stepRegister transfer (RTL) level Functional Gate level Testbenches – Apply stimulusAutomatic Manual Ex: ModelSim, Riviera 15

Testbenches RTL LevelVerify logic of code No timing Functional levelOccurs after synthesis Verify intactness of design Gate levelOccurs after implementation Verify timing 16

Step #3: Synthesis Reduces and optimizes designCreating structural elements Optimizing Mapping 17

Step #4: Implementation Final stage Place and routeAutomatic or manual pin assignment Uses constraint file 3 stepsTranslate Fit Generate program file 18

VHDL Basics VHDLVHSIC Hardware Description LanguageVery High Speed Integrated Circuit Industry Standard for Description, Modelingand Synthesis of Digital Circuits and Systems19

VHDL Framework & Syntax VHDL Description of Logic Blocks is splitinto Entities Defines the Inputs & Outputs of a design Similar to a declaration of a function in C, C Architecture Describes the logic behind the entity Similar to a description of a function in C, C 20

VHDL Example: 1-Bit Adderlibrary ieee;use ieee.std logic 1164.all;ENTITY Single Adder IS PORT(A, B: IN std logic ;S, C: OUT std logic);END Single Adder;ARCHITECTURE Architecture Single OF Single Adder ISBEGINS A xor B;C A and B;END Architecture Single;21

FPGA ImplementationASBC22

HDL – Statement Types Concurrent statements actat the same time Think of a schematic A Process containssequential statements Like software Parallel and Sequential Processes run in parallel andinteract concurrently23

Language Basics - Entity Architecture Pair Entity is like Front Panel and connector Pane Architecture is like block diagram24

LabVIEW FPGA Module Software for developing VIs forFPGA target VIs for host PC interaction withFPGA target Target LabVIEW FPGA EnabledHardware Plug-In Reconfigurable I/O (RIO)boardsCompactRIO ModularReconfigurable I/O SystemCompact Vision System25

LabVIEW FPGA Tool ChainXilinx Compiler LabVIEW VI Bitfile VHDLLabVIEW FPGAFPGA Target26

Advantages of FPGA Based SystemsExample: R-SeriesADCsPCIInterfacingDACsDIOSimilar to M-series, DAQ-STC replaced with an FPGA27

VHDL Example: 4-Bit Adderlibrary ieee;use ieee.std logic 1164.all;ENTITY Four Bit Adder IS PORT(A, B: IN std logic vector (0 downto 3) ;CoutCin: IN std logic;S: OUT std logic vector(0 downto 3);Cout: OUT std logic);END Four Bit Adder;ARCHITECTURE Architecture Four OF Four Bit Adder ISCOMPONENT Single Adder PORT(A, B, Cin: IN std logic ;A S,B C: OUT std logic);END COMPOENNT;SIGNAL Cint: std logic vector (0 downto 2)CinBEGINAdd1: Single Adder port map (A(0), B(0), Cin, S(0), Cint(0));Add2: Single Adder port map (A(1), B(1), Cint(0), S(1), Cint(1));SumAdd3: Single Adder port map (A(2), B(2), Cint(1), S(2), Cint(2));Add4: Single Adder port map (A(3), B(3), Cint(2), S(3), Cout);END Architecture Four;28

LabVIEW FPGA Equivalent29

LabVIEW FPGA vsVHDL66 Pages 4000 linesCounterAnalog I/OI/O with DMA30

Summary 4 Main steps in putting together an FPGA Good for custom circuits and reliablearchitectures Tools abstracting the complexity available31

What is an FPGA? What it is Field-programmable gate array A silicon chip with unconnected gates User can define and re-define functionality How it works Define behavior in software Compile and download to the hardware Hardware implementation of code When

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