1. General Description - NXP
LPC11Axx32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash, 8 kBSRAM, 4 kB EEPROM; configurable analog/mixed-signalRev. 4 — 30 October 2012Product data sheet1. General descriptionThe LPC11Axx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for8/16-bit microcontroller applications, offering performance, low power, simple instructionset and memory addressing together with reduced code size compared to existing 8/16-bitarchitectures.The LPC11Axx operate at CPU frequencies of up to 50 MHz.Analog/mixed-signal subsystems can be configured by software from interconnecteddigital and analog peripherals.The digital peripherals on the LPC11Axx include up to 32 kB of flash memory, up to 4 kBof EEPROM data memory, up to 8 kB of SRAM data memory, a Fast-mode Plus I2C-businterface, a RS-485/EIA-485 USART, two SSP controllers, four general purposecounter/timers, and up to 42 general purpose I/O pins.Analog peripherals include a 10-bit ADC, a 10-bit DAC, an analog comparator, atemperature sensor, an internal voltage reference, and UnderVoltage LockOut (UVLO)protection.2. Features and benefits System: ARM Cortex-M0 processor, running at frequencies of up to 50 MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Serial Wire Debug (SWD) JTAG boundary scan. System tick timer. Memory: Up to 32 kB on-chip flash program memory. Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable. Up to 8 kB SRAM data memory. 16 kB boot ROM. In-System Programming (ISP) for flash and In-Application Programming (IAP) forflash and EEPROM via on-chip bootloader software. Includes ROM-based 32-bit integer division and I2C-bus driver routines. Digital peripherals: Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-downresistors, repeater mode, and open-drain mode.
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontroller LPC11AXXProduct data sheet Up to 16 pins are configurable with a digital input glitch filter for removing glitcheswith widths of 10 ns or less and two pins are configurable for 50 ns glitch filters. GPIO pins can be used as edge and level sensitive interrupt sources. High-current source output driver (20 mA) on one pin (PIO0 21). High-current sink driver (20 mA) on true open-drain pins (PIO0 2 and PIO0 3). Four general purpose counter/timers with a total of up to 16 capture inputs and 14match outputs. Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internallow-power WatchDog Oscillator (WDOsc).Analog peripherals: 10-bit ADC with input multiplexing among 8 pins. 10-bit DAC with flexible conversion triggering. Highly flexible analog comparator with a programmable voltage reference. Integrated temperature sensor. Internal voltage reference. UnderVoltage Lockout (UVLO) protection against power-supply droop below 2.4 V.Serial interfaces: USART with fractional baud rate generation, internal FIFO, support forRS-485/9-bit mode and synchronous mode. Two SSP controllers with FIFO and multi-protocol capabilities. Support data ratesof up to 25 Mbit/s. I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus witha data rate of 1 Mbit/s with multiple address recognition and monitor mode.Clock generation: Crystal Oscillator (SysOsc) with an operating range of 1 MHz to 25 MHz. 12 MHz internal RC Oscillator (IRC) trimmed to 1% accuracy that can optionally beused as a system clock. Internal low-power, Low-Frequency Oscillator (LFOsc) with programmablefrequency output. Clock input for external system clock (25 MHz typical). PLL allows CPU operation up to the maximum CPU rate with the IRC, the externalclock, or the SysOsc as clock sources. Clock output function with divider that can reflect the SysOsc, the IRC, the mainclock, or the LFOsc.Power control: Supports one reduced power mode: The ARM Sleep mode. Power profiles residing in boot ROM allowing to optimize performance andminimize power consumption for any given application through one simple functioncall. Processor wake-up from reduced power mode using any interrupt. Power-On Reset (POR). Brown-Out Detect (BOD) with two programmable thresholds for interrupt and onehardware controlled reset trip point. POR and BOD are always enabled for rapid UVLO protection against power supplyvoltage droop below 2.4 V.Unique device serial number for identification.All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.2 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontroller Single 3.3 V power supply (2.6 V to 3.6 V). Temperature range 40 C to 85 C. Available as LQFP48 package, HVQFN33 (7 7) and HVQFN33 (5 5) packages, andin a very small WLCSP20 package.3. Applications Power managementIndustrial controlRemote monitoringPoint-of-saleTest and measurement equipmentNetwork appliances and servicesFactory automation Gaming equipmentMotion controlMedical instrumentationFire and securitySensorsPrecision instrumentationHVAC and building control4. Ordering informationTable 1.Ordering informationType 20 wafer level chip-size package; 20 bumps; 2.5 2.5 0.6 mm-LPC11A04UKWLCSP20 wafer level chip-size package; 20 bumps; 2.5 2.5 0.6 mm-LPC11A11FHN33/001 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/aterminals; body 7 7 0.85 mmLPC11A12FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/aterminals; body 7 7 0.85 mmLPC11A13FHI33/201HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/aterminals; body 5 5 0.85 mmLPC11A14FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/aterminals; body 7 7 0.85 mmLPC11A12FBD48/101 LQFP48LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC11A14FBD48/301 LQFP48LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC11AXXProduct data sheetAll information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.3 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontroller4.1 Ordering optionsFlashSRAMEEPROM10-bit DACTemperature sensorAnalog comparatorUSARTSSP/SPII2CGPIOOrdering optionsType number10-bit ADC channelsTable 2.PackageLPC11A02UK16 kB4 kB2 kB811111118WLCSP20LPC11A04UK32 kB8 kB4 kB811111118WLCSP20LPC11A11FHN33/0018 kB2 kB512 B811112128HVQFN33LPC11A12FHN33/10116 kB4 kB1 kB811112128HVQFN33LPC11A12FBD48/10116 kB4 kB1 kB811112142LQFP48LPC11A13FHI33/20124 kB6 kB2 kB811112128HVQFN33LPC11A14FHN33/30132 kB8 kB4 kB811112128HVQFN33LPC11A14FBD48/30132 kB8 kB4 kB811112142LQFP48LPC11AXXProduct data sheetAll information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.4 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontroller5. Block diagramSWDXTALIN XTALOUTLPC11AxxSysOsc(3)ARMCORTEX-M0system busBODCLKOUTCLKINPOREEPROM512 B/1/4 kBclocks, internal voltage reference,and controlsFLASH8/16/24/32 kBslaveHIGH-SPEEDGPIOCLOCKGENERATION,POWER CONTROL,SYSTEMFUNCTIONSIRC, LFOSC, WDOSCTEST/DEBUGINTERFACEGPIO portsRESETSRAM2/4/6/8 kBslaveROM16 kBslaveslaveAHB-LITE BUSslaveRXDTXDCTS, DCD, DSR, RIRTS, DTRSCLKCT32B0 MAT[3:0]CT32B0 CAP[2:0]CT32B1 MAT[3:0]CT32B1 CAP[2:0]CT16B0 MAT[3:0]CT16B0 CAP[2:0]CT16B1 MAT[3:0]CT16B1 CAP[2:0]AHB TO APBBRIDGEUSART(4)AD[7:0]ATRG[1:0]10-bit ADCTEMPERATURE SENSOR32-bit COUNTER/TIMER 0ACMP I[5:1]ACMP OVDDCMPANALOG COMPARATOR32-bit COUNTER/TIMER 110-bit DAC16-bit COUNTER/TIMER 0AOUT16-bit COUNTER/TIMER 1SCL, SDA(1)SCL, SDA(2)SCL, SDA(2)SCL, SDA(2)I2C-BUSWINDOWED WATCHDOGTIMERIOCONFIGPMUSYSTEM CONTROLSSP0SCK0, SSEL0,MISO0, MOSI0SSP1(3)SCK1, SSEL1,MISO1, MOSI1002aaf428(1) Open-drain pins.(2) Standard I/O pins.(3) Not available on WLCSP packages.(4) Modem control pins not available on WLCSP packages.Fig 1.LPC11Axx block diagramLPC11AXXProduct data sheetAll information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.5 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontroller6. Pinning informationLPC11AXXProduct data sheet37 PIO1 238 SWDIO/PIO0 1039 PIO0 1140 PIO0 3042 VSS41 PIO0 1544 VDD(3V3)43 PIO0 2745 PIO0 2346 PIO0 12PIO0 26136 PIO1 1PIO0 28235 TRST/PIO0 9RESET/PIO0 0334 TDO/PIO0 8PIO0 1433 TMS/PIO0 7VSS(IO)5XTALIN6XTALOUT730 PIO0 14VDD(IO)829 TCK/SWCLK/PIO0 5PIO0 24928 PIO0 432 TDI/PIO0 6LPC11A12FBD48/101LPC11A14FBD48/30131 PIO1 0PIO0 31 24PIO0 21 23PIO0 20 22PIO0 17 21PIO1 5 20PIO1 4 19PIO0 16 18PIO0 25 1725 PIO1 7PIO0 3 1626 PIO1 8PIO1 9 12PIO0 2 1527 PIO0 22PIO1 6 11PIO0 19 14PIO0 18 10PIO0 29 13Fig 2.47 PIO0 1348 PIO1 36.1 Pinning002aaf499Pin configuration LQFP48 packageAll information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.6 of 84
LPC11AxxNXP SemiconductorsVDD(3V3)PIO0 27PIO0 15PIO0 11SWDIO/PIO0 10272625PIO0 2328PIO0 123029PIO0 1331terminal 1index area3232-bit ARM Cortex-M0 microcontrollerPIO0 26124RESET/PIO0 0223TDO/PIO0 8PIO0 1322TMS/PIO0 7TRST/PIO0 9XTALIN421TDI/PIO0 6XTALOUT520PIO0 14VDD(IO)619TCK/SWCLK/PIO0 5PIO0 24718PIO0 4PIO0 18817PIO0 22910111213141516PIO0 19PIO0 2PIO0 3PIO0 25PIO0 16PIO0 17PIO0 20PIO0 2133 VSS002aaf500Transparent top viewParts: LPC11A11FHN33/001, LPC11A12FHN33/101, LPC11A13FHI33/201,LPC11A14FHN33/301Fig 3.Pin configuration HVQFN 33 packageEDCBA1234002aaf175Parts: LPC11A02UK, LPC11A04UKFig 4.Pin configuration WLCSP20 package6.2 Pin descriptionAll functional pins on the LPC11Axx are mapped to GPIO port 0 and port 1 (see Table 4).The port pins are multiplexed to accommodate more than one function (see Table 3).The pin function is controlled by the pin’s IOCON register (see the LPC11Axx usermanual). The standard I/O pad configuration is illustrated in Figure 31 and a detailed pindescription is given in Table 4.LPC11AXXProduct data sheetAll information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.7 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 3.FunctionPin multiplexingTypeLQFP48HVQFN33WCSP20Glitch filterPinPinBallPIO0 1no43B2PIO0 12no4631E1PIO0 19no149-PIO0 24no97-PIO0 1no43B2PIO0 19no149-PortSystem clocks, reset, and nalog)--75-RESETIPIO0 020 ns[1]32C1PIO0 910 ns[2]3524D4PIO0 510ns[2]2919B310ns[2]3221C3Serial Wire Debug (SWD) and JTAGTRSTTCKTDIIIIPIO0 6TDOOPIO0 8no3423C2TMSIPIO0 710 ns[2]3322C4PIO0 250ns[2]1510A110ns[2]2919B3PIO0 350ns[2]1611B1PIO0 1010 ns[2]3825D3SWCLKIPIO0 5SWDIOI/OAnalog peripherals (ADC, DAC, comparator)LPC11AXXProduct data sheetACMP I1I(analog)PIO0 27no4328-ACMP I2I(analog)PIO0 13no4732D1ACMP I3I(analog)PIO0 16no1813A2ACMP I4I(analog)PIO0 17no2114A3ACMP I5I(analog)PIO0 22no2717-ACMP OO(digital)PIO0 2no1510A1PIO0 3no1611B1PIO0 12no4631E1PIO0 21no2316-PIO0 23no4530-AD0I(analog)PIO0 6no3221C3AD1I(analog)PIO0 7no3322C4All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.8 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 3.Pin tch filterPinPinBallAD2I(analog)PIO0 8no3423C2AD3I(analog)PIO0 9no3524D4AD4I(analog)PIO0 10no3825D3AD5I(analog)PIO0 11no3926D2AD6I(analog)PIO0 14no3020B4AD7I(analog)PIO0 15no4127E4AOUTO(analog)PIO0 4no2818A4ATRG0IPIO0 1610 ns[2]1813A2ATRG1IPIO0 1710 ns[2]2114A3VDDCMPI(analog)PIO0 14no3020-PIO0 5no--B3PIO0 250 ns[2]1510A1PIO0 12no4631E11813A2I2C-businterfaceSCLI/OPIO0 16SDAI/O10ns[2]PIO0 24no97-PIO0 350 ns[2]1611B110ns[2]4732D1PIO0 1510ns[2]4127E4PIO0 25no1712-PIO0 610 ns[2]3221C3ns[2]2717-PIO0 13SSP0 controllerMISO0I/OPIO0 22MOSI0SCK0SSEL0LPC11AXXProduct data sheetI/OI/OI/O10PIO1 2no37--PIO0 410 ns[2]2818A4PIO0 19no149-PIO1 3no48--PIO1 7no25--PIO0 510 ns[2]2919B3PIO0 20no2215-PIO1 0no31--PIO0 1no43B2PIO0 18no108-PIO1 1no36--All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.9 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 3.Pin tch filterPinPinBallPIO0 1410 ns[2]3020-SSP1 controllerMISO1MOSI1SCK1SSEL1I/OI/OI/OI/OPIO0 26no11-PIO1 8no26--4328-24--PIO0 2710PIO0 31nons[2]PIO0 30no40--PIO1 6no11--PIO0 810 ns[2]3423-PIO1 5no20--PIO0 29no13--PIO0 25no1712-PIO1 4no19--PIO0 28no2--PIO0 1no43B2PIO0 12no4631E1PIO1 ct data sheetIOI/OIOIIOPIO1 8no26--PIO0 13no4732D1PIO0 15no4127E4PIO0 26no11-PIO1 5no20--PIO0 1110 ns[2]3926D2PIO0 21no2316-PIO0 23no4530-ns[2]PIO0 9103524D4PIO0 21no2316-PIO1 7no25--PIO0 10no3825D3PIO0 23no4530-PIO1 6no11--PIO1 9no12--PIO1 0no31--PIO0 29no13--PIO1 2no37--PIO0 28no2--PIO1 1no36--All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.10 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 3.FunctionRIPin multiplexingTypeILQFP48HVQFN33WCSP20PortGlitch filterPinPinBallPIO0 30no40--PIO0 31no24--PIO1 3no48--PIO0 250 ns[2]1510A1PIO0 18no108-16-bit counter/timer CT16B0CT16B0 CAP0 ICT16B0 CAP1 IPIO0 30no40--PIO0 1610 ns[2]1813A2PIO1 4no19--2114A3ns[2]CT16B0 CAP2 IPIO0 1710PIO1 5no20--CT16B0 MAT0 OPIO0 7no3322C4PIO0 17no2114A3PIO1 6no11--CT16B0 MAT1 OCT16B0 MAT2 OPIO0 4no2818A4PIO0 9no3524D4PIO1 0no31--PIO0 5no2919B3PIO0 10no3825D3PIO1 7no25--50 ns[2]1611B116-bit counter/timer CT16B1CT16B1 CAP0 ICT16B1 CAP1 ICT16B1 CAP2 ICT16B1 MAT0 OCT16B1 MAT1 OCT16B1 MAT2 OLPC11AXXProduct data sheetPIO0 3PIO0 24no97-PIO1 3no48--PIO0 18no108-PIO0 26no11-PIO0 31no24--PIO0 2710 ns[2]4328-PIO1 7no25--PIO0 19no149-PIO0 25no1712-PIO1 1no36--PIO0 14no3020B4PIO1 2no37--PIO1 8no26--PIO0 20no2215-PIO1 2no37--PIO1 9no12--All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.11 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 3.FunctionPin multiplexingTypeLQFP48HVQFN33WCSP20Glitch filterPinPinBallPIO0 1110 ns[2]3926D2PIO0 23no4530-PIO0 28no2--3020B413--Port32-bit counter/timer CT32B0CT32B0 CAP0 ICT32B0 CAP1 ICT32B0 CAP2 ICT32B0 MAT0 OCT32B0 MAT1 OCT32B0 MAT2 OCT32B0 MAT3 OPIO0 1410PIO0 29nons[2]ns[2]PIO0 15104127E4PIO0 26no11-PIO0 12no4631E1PIO0 30no40--PIO0 13no4732D1PIO1 4no19--PIO0 1no43B2PIO1 5no20--PIO0 6no3221C3PIO1 6no11--PIO0 710 ns[2]3322C4PIO0 20no2215-PIO1 4no19--PIO0 21no2316-PIO1 5no20--32-bit counter/timer CT32B1CT32B1 CAP0 ICT32B1 CAP1 ICT32B1 CAP2 ICT32B1 MAT0 OCT32B1 MAT1 OCT32B1 MAT2 OCT32B1 MAT3 Ons[2]PIO0 22102717-PIO1 6no11--PIO0 8no3423C2PIO0 31no24--PIO1 8no26--PIO0 9no3524D4PIO0 27no4328-PIO1 7no25--PIO0 10no3825D3PIO0 22no2717-PIO1 9no12--PIO0 11no3926D2PIO1 1no36--PIO1 0no31----86E2Supply and ground pinsVDD(IO)LPC11AXXProduct data sheetSupplyAll information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.12 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 3.Pin tch 233E3VSS(IO)Ground--533E3[1]Always on.[2]Programmable on/off. By default, the glitch filter is disabled.Table 4 shows all pins in order of their port number. The default function after reset islisted first. All port pins PIO0 0 to PIO1 9 have internal pull-up resistors enabled afterreset with the exception of the true open-drain pins PIO0 2 and PIO0 3.Pull-up/pull-down configuration, repeater, and open-drain modes can be programmedthrough the IOCON registers for each of the port pins.Table 4.LPC11Axx pin description tableSymbolPin/BallType Reset DescriptionstateLQFP48HVQFN33WLCSP20[1]32C1[2]PIO0 1/RXD/CLKOUT/ 4CT32B0 MAT2/SSEL0/CLKIN3B2[3]RESET/PIO0 0PIO0 2/SCL/ACMP O/ 15 10 A1TCK/SWCLK/CT16B0 CAP0LPC11AXXProduct data sheet[4][5]II; PURESET — External reset input with fixed 20 ns glitch filter: ALOW on this pin resets the device, causing I/O ports andperipherals to take on their default states and processorexecution to begin at address 0.I/O-PIO0 0 — General purpose digital input/output pin.I/OI; PUPIO0 1 — General purpose digital input/output pin. A LOWlevel on this pin during reset starts the ISP command handler.I-RXD — Receiver data input for USART.O-CLKOUT — Clock output.O-CT32B0 MAT2 — Match output 2 for 32-bit timer 0.I/O-SSEL0 — Slave Select for SSP0.I-CLKIN — External clock input.I/OI; IAPIO0 2 — General purpose digital input/output pin.High-current sink (20 mA) or standard-current sink (4 mA)programmable; true open-drain for all pin functions. Inputglitch filter (50 ns) capable.I/O-SCL — I2C-bus clock (true open-drain) input/output. Inputglitch filter (50 ns) capable.O-ACMP O — Analog comparator output.I-TCK/SWCLK — Serial Wire Debug Clock (secondary forLQFP and HVQFN packages). Input glitch filter (50 ns)capable. For the WLCSP20 package only, this pin isconfigured to the SWCLK function by the boot loader afterreset.I-CT16B0 CAP0 — Capture input 0 for 16-bit timer 0. Inputglitch filter (50 ns) capable.All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.13 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 4.LPC11Axx pin description tableSymbolPin/BallType Reset DescriptionstateWLCSP20PIO0 3/SDA/ACMP O/ 16 11SWDIO/CT16B1 CAP0B1LQFP48HVQFN33[1]PIO0 4/R/AOUT/CT16B0 MAT1/MOSI0TCK/SWCLK/PIO0 5/R/CT16B0 MAT2/SCK0TCK/SWCLK/PIO0 5/VDDCMP/CT16B0 MAT2/SCK0LPC11AXXProduct data sheet28 18 A429 19 ---B3[4][6][7][9][7][8]I/OI; IAPIO0 3 — General purpose digital input/output pin.High-current sink (20 mA) or standard-current sink (4 mA)programmable; true open-drain for all pin functions. Inputglitch filter (50 ns) capable.I/O-SDA — I2C-bus data (true open-drain) input/output. Inputglitch filter (50 ns) capable.O-ACMP O — Analog comparator output.I/O-SWDIO — Serial Wire Debug I/O (secondary for LQFP andHVQFN packages). Input glitch filter (50 ns) capable. For theWLCSP20 package only, this pin is configured to the SWDIOfunction by the boot loader after reset.I-CT16B1 CAP0 — Capture input 0 for 16-bit timer 1. Inputglitch filter (50 ns) capable.I/OI; PUPIO0 4 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.--R — Reserved.O-AOUT — D/A converter output.O-CT16B0 MAT1 — Match output 1 for 16-bit timer 0.I/O-MOSI0 — Master Out Slave In for SSP0. Input glitch filter(10 ns) capable.II; PUTCK/SWCLK — Test clock TCK for JTAG interface andprimary (default) Serial Wire Debug Clock. Input glitch filter (10ns) capable.I/O-PIO0 5 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.--R — Reserved.O-CT16B0 MAT2 — Match output 2 for 16-bit timer 0.I/O-SCK0 — Serial clock for SSP0. Input glitch filter (10 ns)capable.II; PUTCK/SWCLK — Test clock TCK for JTAG interface andsecondary Serial Wire Debug ClocK. Use PIO0 2 for thedefault TCK/SWCLK function. Input glitch filter (10 ns)capable.I/O-PIO0 5 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I-VDDCMP — Analog comparator alternate reference voltage.O-CT16B0 MAT2 — Match output 2 for 16-bit timer 0.I/O-SCK0 — Serial clock for SSP0. Input glitch filter (10 ns)capable.All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.14 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 4.LPC11Axx pin description tableSymbolPin/BallType Reset DescriptionstateTDI/PIO0 6/AD0/CT32B0 MAT3/MISO0TMS/PIO0 7/AD1/CT32B1 CAP0/CT16B0 MAT0TDO/PIO0 8/AD2/CT32B1 MAT0/SCK1TRST/PIO0 9/AD3/CT32B1 MAT1/CT16B0 MAT1/CTSLPC11AXXProduct data sheetWLCSP20HVQFN33LQFP48[1]32 21 C333 22 C434 23 C235 24 D4[9][9][9][9]II; PUTDI — Test Data In for JTAG interface. Input glitch filter (10 ns)capable.I/O-PIO0 6 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I-AD0 — A/D converter input 0.O-CT32B0 MAT3 — Match output 3 for 32-bit timer 0.I/O-MISO0 — Master In Slave Out for SSP0. Input glitch filter(10 ns) capable.II; PUTMS — Test Mode Select for JTAG interface. Input glitch filter(10 ns) capable.I/O-PIO0 7 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I-AD1 — A/D converter input 1.I-CT32B1 CAP0 — Capture input 0 for 32-bit timer 1. Inputglitch filter (10 ns) capable.O-CT16B0 MAT0 — Match output 2 for 16-bit timer 0.OI; PUTDO — Test Data Out for JTAG interface.I/O-PIO0 8 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I-AD2 — A/D converter input 2.O-CT32B1 MAT0 — Match output 0 for 32-bit timer 1.I/O-SCK1 — Serial clock for SSP1. Input glitch filter (10 ns)capable.II; PUTRST — Test Reset for JTAG interface. Input glitch filter(10 ns) capable.I/O-PIO0 9 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I-AD3 — A/D converter, input 3.O-CT32B1 MAT1 — Match output 1 for 32-bit timer 1.O-CT16B0 MAT1 — Match output 1 for 16-bit timer 0.I-CTS — Clear To Send input for USART. Input glitch filter(10 ns) capable.All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.15 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 4.LPC11Axx pin description tableSymbolPin/BallType Reset DescriptionstateSWDIO/PIO0 10/AD4/CT32B1 MAT2/CT16B0 MAT2/RTSPIO0 11/SCLK/AD5/CT32B1 MAT3/CT32B0 CAP0PIO0 12/RXD/ACMP O/CT32B0 MAT0/SCL/CLKINPIO0 13/TXD/ACMP I2/CT32B0 MAT1/SDALPC11AXXProduct data sheetWLCSP20HVQFN33LQFP48[1]38 25 D339 26 D246 31 E147 32 D1[9][9][3][9]I/OI; PUSWDIO — Primary (default) Serial Wire Debug I/O for theLQFP48 and HVQFN33 packages. For the WLCSP20package, use PIO0 3. Input glitch filter (10 ns) capable.I/O-PIO0 10 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I-AD4 — A/D converter, input 4.O-CT32B1 MAT2 — Match output 2 for 32-bit timer 1.O-CT16B0 MAT2 — Match output 2 for 16-bit timer 0.O-RTS — Request To Send output for USART.I/OI; PUPIO0 11 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I/O-SCLK — Serial clock for USART. Input glitch filter (10 ns)capable.I-AD5 — A/D converter, input 5.O-CT32B1 MAT3 — Match output 3 for 32-bit timer 1.I-CT32B0 CAP0 — Capture input 0 for 32-bit timer 0. Inputglitch filter (10 ns) capable.I/OI; PUPIO0 12 — General purpose digital input/output pin.I-RXD — Receiver data input for USART. This pin is used forISP communication.O-ACMP O — Analog comparator output.O-CT32B0 MAT0 — Match output 0 for 32-bit timer 0.I/O-SCL — I2C-bus clock input/output. This is not an I2C-busopen-drain pin[10].I-CLKIN — External clock input.I/OI; PUPIO0 13 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.O-TXD — Transmitter data output for USART. This pin is usedfor ISP communication.I-ACMP I2 — Analog comparator input 2.O-CT32B0 MAT1 — Match output 1 for 32-bit timer 0.I/O-SDA — I2C-bus data input/output. This is not an I2C-busopen-drain pin[10]. Input glitch filter (10 ns) capable.All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.16 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 4.LPC11Axx pin description tableSymbolPin/BallType Reset DescriptionstatePIO0 14/MISO1/AD6/CT32B0 CAP1/CT16B1 MAT1/VDDCMPPIO0 14/MISO1/AD6/CT32B0 CAP1/CT16B1 MAT1PIO0 15/TXD/AD7/CT32B0 CAP2/SDAPIO0 16/ATRG0/ACMP I3/CT16B0 CAP1/SCLLPC11AXXProduct data sheetWLCSP20HVQFN33LQFP48[1]30 20 ---B441 27 E418 13 A2[7][9][9][9]I/OI; PUPIO0 14 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I/O-MISO1 — Master In Slave Out for SSP1. Input glitch filter(10 ns) capable.I-AD6 — A/D converter, input 6.I-CT32B0 CAP1 — Capture input 1 for 32-bit timer 0. Inputglitch filter (10 ns) capable.O-CT16B1 MAT1 — Match output 1 for 16-bit timer 1.I-VDDCMP — Analog comparator alternate reference voltage.I/OI; PUPIO0 14 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I/O-MISO1 — Master In Slave Out for SSP1. Input glitch filter(10 ns) capable.I-AD6 — A/D converter, input 6.I-CT32B0 CAP1 — Capture input 1 for 32-bit timer 0. Inputglitch filter (10 ns) capable.O-CT16B1 MAT1 — Match output 1 for 16-bit timer 1.I/OI; PUPIO0 15 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.O-TXD — Transmitter data output for USART.I-AD7 — A/D converter, input 7.I-CT32B0 CAP2 — Capture input 2 for 32-bit timer 0. Inputglitch filter (10 ns) capable.I/O-SDA — I2C-bus data input/output. This is not an I2C-busopen-drain pin[10]. Input glitch filter (10 ns) capable.I/OI; PUPIO0 16 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I-ATRG0 — Conversion trigger 0 for ADC or DAC. Input glitchfilter (10 ns) capable.I-ACMP I3 — Analog comparator input 3.I-CT16B0 CAP1 — Capture input 1 for 16-bit timer 0. Inputglitch filter (10 ns) capable.I/O-SCL — I2C-bus clock input/output. This is not an I2C-busopen-drain pin[10]. Input glitch filter (10 ns) capable.All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.17 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 4.LPC11Axx pin description tableSymbolPin/BallType Reset DescriptionstatePIO0 17/ATRG1/ACMP I4/CT16B0 CAP2/CT16B0 MAT0PIO0 18/R/SSEL0/CT16B0 CAP0/CT16B1 CAP1PIO0 19/CLKIN/CLKOUT/MOSI0/CT16B1 MAT0PIO0 20/R/SCK0/CT32B1 CAP0/CT16B1 MAT2PIO0 21/CTS/ACMP O/CT32B1 CAP1/SCLKPIO0 22/MISO0/ACMP I5/CT32B1 MAT2/CT32B1 CAP2LPC11AXXProduct data sheetWLCSP20HVQFN33LQFP48[1]21 14 A310 814 9--22 15 -23 16 -27 17 -[9][3][3][3][3][9]I/OI; PUPIO0 17 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I-ATRG1 — Conversion trigger 1 for ADC or DAC. Input glitchfilter (10 ns) capable.I-ACMP I4 — Analog comparator input 4.I-CT16B0 CAP2 — Capture input 2 for 16-bit timer 0. Inputglitch filter (10 ns) capable.O-CT16B0 MAT0 — Match output 0 for 16-bit timer 0.I/OI; PUPIO0 18 — General purpose digital input/output pin.--R — Reserved.I/O-SSEL0 — Slave Select for SSP0.I-CT16B0 CAP0 — Capture input 0 for 16-bit timer 0.I-CT16B1 CAP1 — Capture input 1 for 16-bit timer 1.I/OI; PUPIO0 19 — General purpose digital input/output pin.I-CLKIN — External clock input.O-CLKOUT — Clock output.I/O-MOSI0 — Master Out Slave In for SSP0.O-CT16B1 MAT0 — Match output 0 for 16-bit timer 1.I/OI; PUPIO0 20 — General purpose digital input/output pin.--R — Reserved.I/O-SCK0 — Serial clock for SSP0.I-CT32B1 CAP0 — Capture input 0 for 32-bit timer 1.O-CT16B1 MAT2 — Match output 2 for 16-bit timer 1.I/OI; PUPIO0 21 — General purpose digital input/output pin. Ifconfigured as output, this pin is a high-current source outputdriver (20 mA).I-CTS — Clear To Send input for USART.O-ACMP O — Analog comparator output.I-CT32B1 CAP1 — Capture input 1 for 32-bit timer 1.I/O-SCLK — Serial clock for USART.I/OI; PUPIO0 22 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I/O-MISO0 — Master In Slave Out for SSP0. Input glitch filter(10 ns) capable.I-ACMP I5 — Analog comparator input 5.O-CT32B1 MAT2 — Match output 2 for 32-bit timer 1.I-CT32B1 CAP2 — Capture input 2 for 32-bit timer 1. Inputglitch filter (10 ns) capable.All information provided in this document is subject to legal disclaimers.Rev. 4 — 30 October 2012 NXP B.V. 2012. All rights reserved.18 of 84
LPC11AxxNXP Semiconductors32-bit ARM Cortex-M0 microcontrollerTable 4.LPC11Axx pin description tableSymbolPin/BallType Reset DescriptionstatePIO0 23/RTS/ACMP O/CT32B0 CAP0/SCLKPIO0 24/SCL/CLKIN/CT16B1 CAP0PIO0 25/SDA/SSEL1/CT16B1 MAT0PIO0 26/TXD/MISO1/CT16B1 CAP1/CT32B0 CAP2PIO0 27/MOSI1/ACMP I1/CT32B1 MAT1/CT16B1 CAP2PIO0 28/DTR/SSEL1/CT32B0 CAP0PIO0 29/DSR/SCK1/CT32B0 CAP1LPC11AXXProduct data sheetWLCSP20HVQFN33LQFP48[1]45 30 -97-17 12 -11-43 28 -2-13 ---[3][3][3][3][9][3][3]I/OI; PUPIO0 23 — General purpose digital input/output pin.O-RTS — Request To Send output for USART.O-ACMP O — Analog comparator output.I-CT32B0 CAP0 — Capture input 0 for 32-bit timer 0.I/O-SCLK — Serial clock for USART.I/OI; PUPIO0 24 — General purpose digital input/output pin.I/O-SCL — I2C-bus clock input/output. This is not an I2C-busopen-drain pin[10].I-CLKIN — External clock input.I-CT16B1 CAP0 — Capture input 0 for 16-bit timer 1.I/OI; PUPIO0 25 — General purpose digital input/output pin.I/O-SDA — I2C-bus data input/output. This is not an I2C-busopen-drain pin[10].I/O-SSEL1 — Slave Select for SSP1.O-CT16B1 MAT0 — Match output 0 for 16-bit timer 1.I/OI; PUPIO0 26 — General purpose digital input/output pin.O-TXD — Transmitter data output for USART.I/O-MISO1 — Master In Slave Out for SSP1.I-CT16B1 CAP1 — Capture input 1 for 16-bit timer 1.I-CT32B0 CAP2 — Capture input 2 for 32-bit timer 0.I/OI; PUPIO0 27 — General purpose digital input/output pin. Inputglitch filter (10 ns) capable.I/O-MOSI1 — Master Out Slave In for SSP1. Input glitch filter(10 ns) capable.I-ACMP I1 — Analog comparator input 1.O-CT32B1 MAT1 — Match output 1 for 32-bit timer 1.I-CT16B1 CAP2 — Capture input 2 for 16-bit timer 1. Inputglitch filter (10 ns) capable.I/OI; PUPIO0 28 — General purpose digital input/output pin.O-DTR — Data Terminal Ready output for USART.I/O-SSEL1 — Slave Select for SSP1.I-CT32B0 CAP0 — Capture input 0 for 32-bit
Product data sheet Rev. 4 — 30 October 2012 3 of 84 NXP Semiconductors LPC11Axx 32-bit ARM Cortex-M0 microcontroller Single 3.3 V power supply (2.6 V to 3.6 V). Temperature range 40 C to 85 C. Available as LQFP48 package, HVQFN33 (7 7) and HVQFN33 (5 5) packages
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Power Supply Design for NXP i.MX 6 Using the TPS65023 Application Report SLVA943-February 2018 Power Supply Design for NXP i.MX 6 Using the TPS65023 ABSTRACT This document details the design considerations of a power management unit solution for the NXP i.MX 6Solo and 6DualLite processors using the TPS65023 power management IC (PMIC).
For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors UM10375 LPC13xx User manual 3 20110614 LPC1311/13/42/43 user manual Modifications: Parts LPC1311/01 and LPC1313/01 added. Modifications to the user manual applicable to parts LPC1311/01 and LPC1313/01 only:
NXP Semiconductors LPCXpresso804 User Manual Follow the steps below to build and run a simple example from the LPC804 Code Bundles provided by NXP. 1. Code Bundles for the LPC8xx family are included in the MCUXpresso IDE installation. These can also be downloaded from nxp.com (in case of any updates between IDE
– e200z2 core:NDI per IEEE-ISTO 5001-2008 Class3 – e200z4 core: NDI per IEEE-ISTO 5001-2008 Class 3 NXP Semiconductors Document Number MPC5746C Data Sheet: Technical Data Rev. 6, 11/2018 NXP reserves the right to change the production detail specifications as may be requi
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