NXP Semiconductors ADC Conversions With A Timer Event From .
NXP SemiconductorsData Sheet: Technical DataDocument Number MPC5746CRev. 6, 11/2018MPC5746CMPC5746C MicrocontrollerDatasheetFeatures 1 160 MHz Power Architecture e200z4 Dual issue,32-bit CPU– Single precision floating point operations– 8 KB instruction cache and 4 KB data cache– Variable length encoding (VLE) for significant codedensity improvements 1 x 80 MHz Power Architecture e200z2 Single issue,32-bit CPU– Using variable length encoding (VLE) forsignificant code size footprint reduction End to end ECC– All bus masters, for example, cores, generate asingle error correction, double error detection(SECDED) code for every bus transaction– SECDED covers 64-bit data and 29-bit address Memory interfaces– 3 MB on-chip flash memory supported with theflash memory controller– 3 x flash memory page buffers (3-port flash memorycontroller)– 384 KB on-chip SRAM across three RAM ports Clock interfaces– 8-40 MHz external crystal (FXOSC)– 16 MHz IRC (FIRC)– 128 KHz IRC (SIRC)– 32 KHz external crystal (SXOSC)– Clock Monitor Unit (CMU)– Frequency modulated phase-locked loop (FMPLL)– Real Time Counter (RTC) System Memory Protection Unit (SMPU) with up to 32region descriptors and 16-byte region granularity 16 Semaphores to manage access to shared resources Interrupt controller (INTC) capable of routinginterrupts to any CPU 32-channel eDMA controller with multiple transferrequest sources using DMAMUX Boot Assist Flash (BAF) supports internal flashprogramming via a serial link (SCI) Analog– Two analog-to-digital converters (ADC), one 10-bitand one 12-bit– Three analog comparators– Cross Trigger Unit to enable synchronization ofADC conversions with a timer event from theeMIOS or from the PIT Communication– Four Deserial Serial Peripheral Interface (DSPI)– Four Serial Peripheral interface (SPI)– 16 serial communication interface (LIN) modules– Eight enhanced FlexCAN3 with FD support– Four inter-IC communication interface (I2C)– ENET complex (10/100 Ethernet) that supportsMulti queue with AVB support, 1588, and MII/RMII– Dual-channel FlexRay controller Audio– Synchronous Audio Interface (SAI)– Fractional clock dividers (FCD) operating inconjunction with the SAI Configurable I/O domains supporting FlexCAN,LINFlexD, Ethernet, and general I/O Supports wake-up from low power modes via theWKPU controller On-chip voltage regulator (VREG) Debug functionality– e200z2 core:NDI per IEEE-ISTO 5001-2008Class3 – e200z4 core: NDI per IEEE-ISTO 5001-2008 Class3 Crossbar switch architecture for concurrent access toperipherals, flash memory, and RAM from multiplebus mastersNXP reserves the right to change the production detail specifications as may berequired to permit improvements in the design of its products.
Timer– 16 Periodic Interrupt Timers (PITs)– Two System Timer Modules (STM)– Three Software Watchdog Timers (SWT)– 64 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels Device/board boundary Scan testing supported with Joint Test Action Group (JTAG) of IEEE 1149.1 and IEEE 1149.7(CJTAG) Security– Hardware Security Module (HSMv2)– Password and Device Security (PASS) supporting advanced censorship and life-cycle management– One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts Functional Safety– ISO26262 ASIL-B compliance Multiple operating modes– Includes enhanced low power operationMPC5746C Microcontroller Datasheet, Rev. 6, 11/20182NXP Semiconductors
Table of Contents1Block diagram. 42Family comparison.43Ordering parts.86.3.3Flash memory module life specifications. 403.1Determining valid orderable parts .86.3.4Data retention vs program/erase cycles. 403.2Ordering Information . 96.3.5Flash memory AC timing specifications. 41General. 96.3.6Flash read wait state and address pipeline control4566.3.2Flash memory Array Integrity and Margin Readspecifications. 394.1Absolute maximum ratings. 9settings . 424.2Recommended operating conditions. 114.3Voltage regulator electrical characteristics. 136.4.1DSPI timing. 434.4Voltage monitor electrical characteristics. 176.4.2FlexRay electrical specifications. 494.5Supply current characteristics. 186.4.2.1FlexRay timing.494.6Electrostatic discharge (ESD) characteristics. 226.4.2.2TxEN. 494.7Electromagnetic Compatibility (EMC) specifications. 226.4.2.3TxD. 50I/O parameters.236.4.2.4RxD. 516.4Communication interfaces.435.1AC specifications @ 3.3 V Range.236.4.3Ethernet switching specifications. 525.2DC electrical specifications @ 3.3V Range.246.4.4SAI electrical specifications . 535.3AC specifications @ 5 V Range.255.4DC electrical specifications @ 5 V Range.256.5.1JTAG interface timing . 555.5Reset pad electrical characteristics.266.5.2Nexus timing.585.6PORST electrical specifications.286.5.3WKPU/NMI timing. 60Peripheral operating requirements and behaviours. 286.5.4External interrupt timing (IRQ pin). 616.1Analog. 286.1.1ADC electrical specifications. 286.1.2Analog Comparator (CMP) electrical6.57specifications. 336.2Clocks and PLL interfaces modules.34Dimensions.658.19Thermal attributes. 61Obtaining package dimensions .65Pinouts.666.2.1Main oscillator electrical characteristics.346.2.232 kHz Oscillator electrical specifications . 3610 Reset sequence. 666.2.316 MHz RC Oscillator electrical specifications.3610.1 Reset sequence. 666.2.4128 KHz Internal RC oscillator Electrical10.1.1Reset sequence duration.66specifications . 3710.1.2BAF execution duration.66PLL electrical specifications .3710.1.3Reset sequence description. 676.2.56.3Thermal attributes. 617.18Debug specifications. 55Memory interfaces.386.3.1Flash memory program and erase specifications. 389.1Package pinouts and signal descriptions. 6611 Revision History.6911.1 Revision History.69MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018NXP Semiconductors3
Block diagram1 Block diagram80 MHz e200z2160 MHz e200z4System bus masters64-bit AHB8 KB i-cache 4 KB d-cacheSPFP-APUNexus 3 E2 E-ECC64-bit AHBSystemE2 E-ECCNexus 3 64-bit dataE2 E-ECCFlash Memory2xRAME2 E-ECCE2 E-ECC3 x SA-PF buffers64-bit wide RAMTriple ported256 KB array3 MB array (inc EEE)256 KB ridgeE2 E-ECCWKPU2 x STMBAFPMCFMPLL16 MHz FIRCRTC/APIDEBUG/JTAG2 x SWTsFCCU16 x SEMA42PASS16 x PIT-RTISSCM32 KHzSXOSCMC CGM,MC PCU,MC ME,MC RGM128 KHzSIRCSIUL8–40 MHzFXOSCSTCU(MBIST)MEMUCMUPadkeepersupportTDMLow powerunit interface(LPU)Peripheral clusters68 ch 10-bit ADC0 31 ch 12-bit ADC1 1 x FlexCAN(PN)*(mix int and ext)7 x FlexCAN*16 x LINFlexD4 x I2C3 x analogcomparator (CMP)4 x DSPI4 x SPI3 x SAI3 x FCD2 x eMIOS BCTU2-core INTCDMA and2 x channel mux1 x CRCRegisterprotection* All FlexCANs optionally supportCAN FDFigure 1. MPC5746C block diagram2 Family comparisonThe following table provides a summary of the different members of the MPC5746Cfamily and their proposed features. This information is intended to provide anunderstanding of the range of functionality offered by this family. For full details of all ofthe family derivatives please contact your marketing representative.MPC5746C Microcontroller Datasheet, Rev. 6, 11/20184NXP Semiconductors
Family comparisonNOTEAll optional features (Flash memory, RAM, Peripherals) startwith lowest number or address (e.g., FlexCAN0) and end athighest available number or address (e.g., MPC574xB/C have 6CAN, ending with FlexCAN5).Table 1. MPC5746C Family 4e200z4e200z4MaximumOperatingFrequency2160MHz (Z4)160MHz (Z4)160MHz (Z4)160MHz (Z4)160MHz (Z4)160MHz (Z4)80MHz (Z2)80MHz (Z2)80MHz (Z2)Flash memory2 MB1.5 MB2 MB3 MBEEPROMsupportRAM1.5 MB3 MBEmulated up to 64K256 KB192 KBEmulated up to 128K384 KB(Optional512KB)3192 KBECCEnd to EndSMPU16 entryDMA32 channels10-bit ADC36 Standard channels256 KB384 KB(Optional512KB)332 External channels12-bit ADC15 Precision channels16 Standard channelsAnalogComparator3BCTU1SWT1, SWT[0]STM1, STM[0]PIT-RTI24216 channels PIT1 channels RTIRTC/APITotal Timer1I/O564 channels16-bitsLINFlexDFlexCANDSPI/SPI11Master and Slave (LINFlexD[0], 11 Master(LINFlexD[1:11])Master and Slave (LINFlexD[0], 15 Master(LINFlexD[1:15])6 with optional CAN FD support (FlexCAN[0:5])8 with optional CAN FD support (FlexCAN[0:7])4 x DSPI4 x SPITable continues on the next page.MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018NXP Semiconductors5
Family comparisonTable 1. MPC5746C Family Comparison1 I2C4444SAI/I2S3333FXOSC8 - 40 MHzSXOSC32 KHzFIRC16 MHzSIRC128 KHzFMPLL1Low Power Unit(LPU)YesMPC5745CFlexRay 2.1(dual channel)Yes, 128 MBYes, 128 MBYes, 128 MBYes, 128 MBEthernet (RMII,MII 1588, Mutiqueue onalCensorshipYesFCCU1Safety levelSpecific functions ASIL-B certifiableUser MBISTYesI/O Retention inStandbyYesGPI1 (100 BGA), 17 (176 LQFP-EP), 18 (256 BGA), 18 (324 BGA)GPIO65 (100 BGA), 129 (176 LQFP-EP), 178 (256 BGA), 246 (324 BGA)DebugJTAGC,MPC5746CcJTAGNexusZ4 N3 (Only available on 324BGA (development only) )Z2 N3 (Only available on 324BGA (development only) )Packages176 LQFP-EP176 LQFP-EP176 LQFP-EP176 LQFP-EP176 LQFP-EP176 LQFP-EP256 BGA256 BGA256 BGA256 BGA256 BGA256 BGA,100 BGA100 BGA100 BGA100 BGA100 BGA324 BGA(developmentonly)100 BGA1. Feature set dependent on selected peripheral multiplexing, table shows example. Peripheral availability is packagedependent.2. Based on 125 C ambient operating temperature and subject to full device characterization.3. Contact NXP representative for part number4. Additional SWT included when HSM option selectedMPC5746C Microcontroller Datasheet, Rev. 6, 11/20186NXP Semiconductors
Family comparison5. See device datasheet and reference manual for information on to timer channel configuration and functions.Table 2. MPC5746C Family Comparison - NVM Memory Map 1Start AddressEnd AddressFlash blockRWW 256 KB codeFlash block 56 KB codeFlash block 56 KB codeFlash block 56 KB codeFlash FFFF256 KB codeFlash block 46not availableavailableavailable0x011400000x0117FFFF256 KB codeFlash block 57not availableavailableavailable0x011800000x011BFFFF256 KB codeFlash block 67not availablenot availableavailable0x011C00000x011FFFFF256 KB codeFlash block 77not availablenot availableavailable0x012000000x0123FFFF256 KB codeFlash block 87not availablenot availableavailable0x012400000x0127FFFF256 KB codeFlash block 97not availablenot availableavailableTable 3. MPC5746C Family Comparison - NVM Memory Map 2Start AddressEnd AddressFlash blockRWW PC5746C0x00F9000010x00F93FFF16 KB data Flash2availableavailable10x00F940000x00F97FFF16 KB data Flash2availableavailable10x00F980000x00F9BFFF16 KB data Flash2availableavailable10x00F9C0000x00F9FFFF16 KB data Flash2availableavailable10x00FA00000x00FA3FFF16 KB data Flash3not availableavailable10x00FA40000x00FA7FFF16 KB data Flash3not availableavailable10x00FA80000x00FABFFF16 KB data Flash3not availableavailable10x00FAC0000x00FAFFFF16 KB data Flash3not availableavailable10x00FB00000x00FB7FFF32 KB data FlashReserved0x00FB80000x00FBFFFF32 KB data FlashReserved0x00FC00000x00FC7FFF32 KB data Flash0availableavailable0x00FC80000x00FCFFFF32 KB data Flash1availableavailable0x00FD00000x00FD7FFF32 KB data Flash1availableavailable0x00FD80000x00FDFFFF32 KB data Flash1availableavailable0x00FE00000x00FEFFFF64 KB data Flash0availableavailable0x00FF00000x00FFFFFF64 KB data Flash1availableavailableMPC5746C Microcontroller Datasheet, Rev. 6, 11/2018NXP Semiconductors7
Ordering parts1. Flexible patitions for boot and EEPROMTable 4. MPC5748G Family Comparison - NVM Memory Map 3Start AddressEnd AddressFlash C5746C0x006100000x0061FFFF64 KB HSM Codeblock 20availableavailable0x006200000x0062FFFF64 KB HSM Codeblock 31availableavailableHSM Data0x006300000x00F7FFFF9536 KBReservedHSM Data0x00F800000x00F83FFF16 KB HSM datablock 04availableavailable0x00F840000x00F87FFF16 KB HSM datablock 15availableavailable0x00F880000x00F8BFFF16 KBReservedSmall HSM Code Block0x00F8C0000x00F8FFFF16 KB Code Flashblock0availableavailableTable 5. MPC5746C Family Comparison - RAM Memory MapStart AddressEnd AddressAllocated 001FFF8 FFFF56 FFFF64 FFFF64 FFFF64 KBSRAM4not availableavailableavailable0x400400000x4004FFFF64 KBSRAM5not availablenot availableavailable0x400500000x4005FFFF64 KBSRAM6not availablenot availableavailable0x400600000x4006FFFF64 KBSRAM7not availablenot availableoptional0x400700000x4007FFFF64 KBSRAM8not availablenot availableoptional3 Ordering parts3.1 Determining valid orderable partsTo determine the orderable part numbers for this device, go to www.nxp.com andperform a part number search for the following device number: MPC5746C.MPC5746C Microcontroller Datasheet, Rev. 6, 11/20188NXP Semiconductors
General3.2 Ordering InformationPExample CodePC5746CSK0MMJ6RQualification StatusPower ArchitectureAutomotive PlatformCore VersionFlash Size (core dependent)ProductOptional fieldsFab and mask indicatorTemperature spec.Package CodeCPU FrequencyR Tape & Reel (blank if Tray)Product VersionB Single coreC Dual coreQualification StatusP Engineering samplesS Automotive qualifiedPC Power ArchitectureAutomotive Platform57 Power Architecture in 55nmCore Version4 e200z4 Core Version (highestcore version in the case of multiplecores)Flash Memory Size4 1.5 MB5 2 MB6 3 MBOptional fieldsBlank No optional featureS HSM (Security Module)Fab and mask version indicatorK TSMC Fab#(0,1,etc.) Version of themaskset, like rev. 0 0N65HPackage CodeKU 176 LQFP EPMJ 256 MAPBGAMNM 324 MAPBGAMH 100MAPBGATemperature spec.C -40.C to 85.C TaV -40.C to 105.C TaM -40.C to 125.C TaCPU FrequencyF CAN FDB HSM CAN FDR 512K RAMT HSM 512K RAMG* CAN FD 512K RAMH* HSM CAN FD 512K RAM* G and H for 5746 B/C only2 Z4 operates upto 120 MHz6 Z4 operates upto 160 MHzShipping MethodR Tape and reelBlank TrayNote: Not all part number combinations are available as production product4 General4.1 Absolute maximum ratingsNOTEFunctional operating conditions appear in the DC electricalcharacteristics. Absolute maximum ratings are stress ratingsonly, and functional operation at the maximum values is notguaranteed. See footnotes in Table 6 for specific conditionsMPC5746C Microcontroller Datasheet, Rev. 6, 11/2018NXP Semiconductors9
GeneralStress beyond the listed maximum values may affect devicereliability or cause permanent damage to the device.Table 6. Absolute maximum ratingsSymbolConditions1MinMaxUnit3.3 V - 5. 5V input/output supply voltage—–0.36.0V3.3 V flash supply voltage (when supplyingfrom an external source in bypass mode)—–0.33.63VDecoupling pin for low power regulators7—–0.31.32V3.3 V / 5.0 V ADC1 high reference voltage—–0.36V3.3 V to 5.5V ADC supply voltage—–0.36.0V3.3V to 5.5V ADC supply ground—–0.10.1VParameterVDD HV A, VDD HV B,VDD HV C2, 3VDD HV FLA4, 5VDD LP DEC68VDD HV ADC1 REFVDD HV ADC0VDD HV ADC1VSS HV ADC0VSS HV ADC1VDD LV9, 10, 11, 12Core logic supply voltage—–0.31.32VVINAVoltage on analog pin with respect toground (VSS HV)—–0.3Min (VDD HV x,VDD HV ADCx,VDD ADCx REF) 0.3VVINVoltage on any digital pin with respect toground (VSS HV)Relative toVDD HV A,VDD HV B,VDD HV C–0.3VDD HV x 0.3VAlways–55mAIINJPADInjected input current on any pin duringoverload conditionIINJSUMAbsolute sum of all injected input currentsduring overload condition—–5050mATrampSupply ramp rate—0.5 V / min100V/ms—TA13Ambient temperature—-40125 CTSTGStorage temperature—–55165 C1. All voltages are referred to VSS HV unless otherwise specified2. VDD HV B and VDD HV C are common together on the 176 LQFP-EP package.3. Allowed VDD HV x 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device inreset, TJ 150 C, remaining time at or below 5.5 V.4. VDD HV FLA must be connected to VDD HV A when VDD HV A 3.3V5. VDD HV FLA must be disconnected from ANY power sources when VDD HV A 5V6. This pin should be decoupled with low ESR 1 µF capacitor.7. Not available for input voltage, only for decoupling internal regulators8. 10-bit ADC does not have dedicated reference and its reference is bonded to 10-bit ADC supply(VDD HV ADC0) insidethe package.9. Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum TJ 150 C, remaining time as defined in footnotes 10and 11.10. Allowed 1.38 – 1.45 V– for 10 hours cumulative time at maximum TJ 150 C, remaining time as defined in footnote 11.11. 1.32 – 1.38 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.326 V atmaximum TJ 150 C.12. If HVD on core supply (VHVD LV x) is enabled, it will generate a reset when supply goes above threshold.13. TJ 150 C. Assumes TA 125 C Assumes maximum θJA for 2s2p board. See Thermal attributesMPC5746C Microcontroller Datasheet, Rev. 6, 11/201810NXP Semiconductors
General4.2 Recommended operating conditionsThe following table describes the operating conditions for the device, and for which allspecifications in the data sheet are valid, except where explicitly noted. The deviceoperating conditions must not be exceeded in order to guarantee proper operation andreliability. The ranges in this table are design targets and actual data may vary in thegiven range.NOTE For normal device operations, all supplies must be withinoperating range corresponding to the range mentioned infollowing tables. This is required even if some of thefeatures are not used. If VDD HV A is in 5.0V range, VDD HV FLA should beexternally supplied using a 3.3V source. If VDD HV A isin 3.3V range, VDD HV FLA should be shorted toVDD HV A. VDD HV A, VDD HV B and VDD HV C are allindependent supplies and can each be set to 3.3V or 5V.The following tables: 'Recommended operating conditions(VDD HV x 3.3 V)' and table 'Recommended operatingconditions (VDD HV x 5 V)' specify their ranges whenconfigured in 3.3V or 5V respectively.Table 7. Recommended operating conditions (VDD HV x 3.3 V)SymbolVDD HV AConditions1Min2MaxUnitHV IO supply voltage—3.153.6VHV flash supply voltage—3.153.6VHV ADC1 high reference voltage—3.05.5VHV ADC supply voltage—max(VDD HV A,VDD HV B,VDD HV C) - 0.053.6VHV ADC supply ground—-0.10.1VCore supply voltage—1.21.32VAnalog Comparator DAC reference voltage—3.153.6VInjected input current on any pin duringoverload condition—-3.03.0mAParameterVDD HV BVDD HV CVDD HV FLA3VDD HV ADC1 REFVDD HV ADC0VDD HV ADC1VSS HV ADC0VSS HV ADC1VDD LV4, 5VIN1 CMP REF6, 7IINJPADTable continues on the next page.MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018NXP Semiconductors11
GeneralTable 7. Recommended operating conditions (VDD HV x 3.3 V) 8Ambient temperature under biasfCPU 160MHz–40125 CTJJunction temperature under bias—–40150 C1. All voltages are referred to VSS HV unless otherwise specified2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to thepoint where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.3. VDD HV FLA must be connected to VDD HV A when VDD HV A 3.3V4. Only applicable when supplying from external source.5. VDD LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only beleft floating.6. VIN1 CMP REF VDD HV A7. This supply is shorted VDD HV A on lower packages.8. TJ 150 C. Assumes TA 125 C Assumes maximum θJA of 2s2p board. See Thermal attributesNOTEIf VDD HV A is in 5V range, it is necessary to use internalFlash supply 3.3V regulator. VDD HV FLA should not besupplied externally and should only have decoupling capacitor.Table 8. Recommended operating conditions (VDD HV x 5 V)SymbolConditions 1Min2MaxUnitHV IO supply voltage—4.55.5VHV flash supply voltage—3.153.6VHV ADC1 high reference voltage—3.155.5VHV ADC supply voltage—max(VDD HV A,VDD HV B,VDD HV C) - 0.055.5VHV ADC supply ground—-0.10.1VCore supply voltage—1.21.32VVParameterVDD HV AVDD HV BVDD HV CVDD HV FLA3VDD HV ADC1 REFVDD HV ADC0VDD HV ADC1VSS HV ADC0VSS HV ADC1VDD LV46VIN1 CMP REFIINJPADAnalog Comparator DAC reference voltage—3.155.55Injected input current on any pin duringoverload condition—-3.03.0mATA7Ambient temperature under biasfCPU 160MHz–40125 CTJJunction temperature under bias—–40150 C1. All voltages are referred to VSS HV unless otherwise specified2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to thepoint where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.3. When VDD HV is in 5 V range, VDD HV FLA cannot be supplied externally.This pin is decoupled with Cflash reg.MPC5746C Microcontroller Datasheet, Rev. 6, 11/201812NXP Semiconductors
General4. VDD LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only beleft floating5. VIN1 CMP REF VDD HV A6. This supply is shorted VDD HV A on lower packages.7. TJ 150 C. Assumes TA 125 C Assumes maximum θJA of 2s2p board. See Thermal attributes4.3 Voltage regulator electrical characteristicsThe voltage regulator is composed of the following blocks: Choice of generating supply voltage for the core area. Control of external NPN ballast transistor Generating core supply using internal ballast transistor Connecting an external 1.25 V (nominal) supply directly without the NPN ballast Internal generation of the 3.3 V flash supply when device connected in 5Vapplications External bypass of the 3.3 V flash regulator when device connected in 3.3Vapplications Low voltage detector - low threshold (LVD IO A LO) for VDD HV IO A supply Low voltage detector - high threshold (LVD IO A Hi) for VDD HV IO A supply Low voltage detector (LVD FLASH) for 3.3 V flash supply (VDD HV FLA) Various low voltage detectors (LVD LV x) High voltage detector (HVD LV cold) for 1.2 V digital core supply (VDD LV) Power on Reset (POR LV) for 1.25 V digital core supply (VDD LV) Power on Reset (POR HV) for 3.3 V to 5 V supply (VDD HV A)The following bipolar transistors1 are supported, depending on the device performancerequirements. As a minimum the following must be considered when determining themost appropriate solution to maintain the device under its maximum power dissipationcapability: current, ambient temperature, mounting pad area, duty cycle and frequency forIdd, collector voltage, etc1.BCP56, MCP68 and MJD31are guaranteed ballasts.MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018NXP Semiconductors13
GeneralLPPREGVDD LP DECVDD HV BALLASTULPPREGCLP/ULPREGVRC CTRLV SS HVFPREGCBE FPREGFlashvoltageregulatorV DD LVVDD HV FLACFLASH REGCFP REGVSS HVVSS HVDEVICEFigure 2. Voltage regulator capacitance connectionNOTEOn BGA, VSS LV and VSS HV have been joined on substrateand renamed as VSS.Table 9. Voltage regulator electrical specificationsSymbolCfp reg1Clp/ulp regCbe —0.03Ohm11.4µF—0.1OhmExternal decoupling / stabilitycapacitorMin, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.Combined ESR of externalcapacitor—External decoupling / stabilitycapacitor for internal low powerregulatorsMin, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.Combined ESR of externalcapacitor—Capacitor in parallel to baseemitterBCP68 and BCP563.3MJD314.70.0010.80.001nFTable continues on the next page.MPC5746C Microcontroller Datasheet, Rev. 6, 11/201814NXP Semiconductors
GeneralTable 9. Voltage regulator electrical specifications (continued)SymbolConditionsMinTypMaxUnitExternal decoupling / stabilitycapacitor for internal FlashregulatorsMin, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.1.322.23µFCombined ESR of externalcapacitor—0.001—0.03OhmCHV VDD AVDD HV A supply capacitor 5Min, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.1——µFCHV VDD BVDD HV B supply capacitor5Min, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.1——µFCHV VDD CVDD HV C supply capacitor5Min, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.1——µFCHV ADC0HV ADC supply decouplingcapacitancesMin, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.1——µFHV ADC SAR reference supplydecoupling capacitancesMin, max values shall be grantedwith respect to tolerance, voltage,temperature, and agingvariations.0.47——µFVDD HV BALL FPREG Ballast collector supply7voltageASTWhen collector of NPN ballast isdirectly supplied by an on boardsupply source (not shared withVDD HV A supply pin) withoutany series resistance, that is,RC BALLAST less than 0.01 Ohm.2.25—5.5VRC BALLAST Series resistor on collector ofFPREG ballastWhen VDD HV BALLAST isshorted to VDD HV A on theboard——0.1OhmStart-up time with externalballastafter main supply(VDD HV A) stabilizationCfp reg 3 μF—74—μstSU intStart-up time with internal ballastafter main supply (VDD HV A)stabilizationCfp reg 3 μF—103—μstrampLoad current transientIload from 15% to 55%Cflash reg4CHV ADC1CHV ADR6tSUParameter1.0µsCfp reg 3 µF1. Split capacitance on each pair VDD LV pin should sum up to a total value of Cfp reg2. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum andmaximum values.3. Ceramic X7R or X5R type with capacitance-temperature characteristics /-15% of -55 degC to 125degC isrecommended. The tolerance /-20% is acceptable.4. It is required to minimize the board parasitic inductance from decoupling capacitor to VDD HV FLA pin and the routinginductance should be less than 1nH.MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018NXP Semiconductors15
General5.1. For VDD HV x, 1µf on each side of the chipa. 0.1 µf close to each VDD/VSS pin pair.b. 10 µf near for each power supply sourcec. For VDD LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulationmode, this amount of capacitance will need to be subtracted from the total capacitance required by theregulator
– e200z2 core:NDI per IEEE-ISTO 5001-2008 Class3 – e200z4 core: NDI per IEEE-ISTO 5001-2008 Class 3 NXP Semiconductors Document Number MPC5746C Data Sheet: Technical Data Rev. 6, 11/2018 NXP reserves the right to change the production detail specifications as may be requi
DAC DAC ADC ADC. X19532-062819. Figur e 2: RF-ADC Tile Structure. mX0_axis Data Path ADC VinX0 mX1_axis Data Path ADC VinX1 mX2_axisData Path ADC VinX2 mX3_axis Data Path ADCVinX3 mX3_axis mX1_axis ADC mX0_axis Data Path ADC Data Path ADC VinX_23 VinX_01 Data Path Data Path Dual RF-ADC Tile Quad RF-ADC Tile. X23275-100919. Chapter 2: Overview
· ADC-20 or ADC-24 High-Resolution Data Logger · Quick Start Guide For detailed technical information, please refer to the ADC-20 and ADC-24 Data Sheet. An optional PP310 ADC-20/ADC-24 Terminal Board is designed for use with both data loggers. For simple applications, you can connect sensor wires to the screw terminals on the terminal board,
packages assembled at NXP and NXP's assembly and test vendors. Refer to Section Downloading package information from NXP website of this application note for step by step instructions for retrieving package information. For more details about NXP products, visit www.nxp.com or contact the appropriate product application team.
1 Introduction Semiconductors can be divided into two categories. 1.Intrinsic semiconductors 2.Extrinsic semiconductors This classi cation is related to the purity of the semiconductors. Intrinsic or pure semiconductors are those that are ideal, with no defects, and no ex-ternal impuriti
2. ADC Clock: Clock synthesis circuit to provide required clock frequency to the ADC 3. ADC Supply & Reference: Power supply circuits to provide analog and reference supplies to the ADC Designing for best possible performance MPC57xx SAR ADC Implementation and Use, Rev 0, 06/2014 Freescale Semiconductor, Inc. 5
The ADC-20 and ADC-24 are designed to measure voltages in the range 2.5 volts, but are protected against overvoltages of 30 volts. Any voltages outside the overvoltage protection range may cause permanent damage to the unit. Mains (line) voltages. The ADC-20 and ADC-24 data loggers are not designed for use with mains (line) voltages. Safety .
An ADC refers to a system that converts an analog signal into a digital signal. ADC architectures, notably the Flash ADC, Successive Approximation Register (SAR) ADC and the Pipeline ADC have evolved over the years, each offering one advantage over the other. High speed of operation while resolving a high number of bits with
An expert meeting was held to review the impact of animal nutrition on animal welfare. During the meeting, three major tasks were undertaken for both ruminant and monogastric species: 1) Identify feeding options for different livestock production systems (extensive, mixed crop-livestock, and intensive) that improve animal welfare while increas - ing profitability of the livestock producers and .
