UM10375 LPC1311/13/42/43 User Manual - NXP Semiconductors
UM10375LPC1311/13/42/43 User manualRev. 5 — 21 June 2012User manualDocument informationInfoContentKeywordsARM Cortex-M3, microcontroller, USB, LPC1311, LPC1313, LPC1342,LPC1343, LPC1311/01, LPC1313/01AbstractLPC1311/13/42/43 user manual
UM10375NXP SemiconductorsLPC13xx User manualRevision historyRevDateDescription520120621LPC1311/13/42/43 user manualModifications:420110928 Description of the IP xxx bits in the interrupt priority registers updated (Table 78 toTable 92). Description of the FUNC bits in register IOCON PIO2 11 updated (Table 123). SYSRESSTAT register access changed to R/W (Table 7).ISP Go command description updated (ARM mode not allowed). See Table 325.Description of interrupt use with IAP calls updated (Section 21.8.7).Figure 4 updated (RESET updated by internal reset).Frequency values for FREQSEL bits in the WDTOSCCTRL register corrected (seeTable 15).SRAM use by the bootloader explained in Section 21.2.Figure 9 “Standard I/O pin configuration” updated.LPC1311/13/42/43 user manualModifications:UM10375User manual PDSLEEPCFG register settings updated for parts LPC1311/01 and LPC1313/01 (seeSection 3.5.45. Figure 6 updated and power profile entry address updated in Section 5.4.Figure 19 updated.Description of UART modem interrupt added in Section 12.6.5.All information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.2 of 370
UM10375NXP SemiconductorsLPC13xx User manualRevision history 43 user manualModifications: Parts LPC1311/01 and LPC1313/01 added.Modifications to the user manual applicable to parts LPC1311/01 and LPC1313/01 only:– SSP1 added for part LPC1313FBD48/01 in Chapter 3 “LPC13xx Systemconfiguration” and Chapter 14 “LPC13xx SSP0/1”.– UART functions for part LPC1313FBD48/01 added in Table 128, Table 129, , andTable 138.– Use of IRC for entering deep power-down updated in Section 3.9.4.2.– Enable sequence for UART clock updated in Section 12.1.– Chapter 5 “LPC13xx Power profiles” added.– Register IOCON DSR LOC (Table 140), IOCON DCD LOC (Table 141),IOCON RI LOC (Table 142) added.– Programmable bit OD for pseudo open-drain mode added to IOCON registers inChapter 7.– Chapter 19 “LPC13xx Windowed WatchDog Timer (WWDT)” added. Editorial and formatting updates throughout the user manual. Description WDEN bit updated in Table 290 and Table 296 (WDMOD registers).Pull-up level for internal pull-ups specified in Section 7.3.2 and Section 8.4.1 andSection 8.4.2.Section 3.7 “Start-up behavior” added.NVIC priority register bit description updated in Section 6.6.Description of GPIO data register updated in Section 9.4.1.LPC1342FBD48 package added.220100707LPC1311/13/42/43 user manual120091106LPC1311/13/42/43 user manualContact informationFor more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: salesaddresses@nxp.comUM10375User manualAll information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.3 of 370
UM10375Chapter 1: LPC13xx Introductory informationRev. 5 — 21 June 2012User manual1.1 IntroductionThe LPC13xx are ARM Cortex-M3 based microcontrollers for embedded applicationsfeaturing a high level of integration and low power consumption. The ARM Cortex-M3 is anext generation core that offers system enhancements such as enhanced debug featuresand a higher level of support block integration.The LPC13xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPUincorporates a 3-stage pipeline and uses a Harvard architecture with separate localinstruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3CPU also includes an internal prefetch unit that supports speculative branching.The peripheral complement of the LPC13xx series includes up to 32 kB of flash memory,up to 8 kB of data memory, USB Device, one Fast-mode Plus (FM ) I2C interface, oneUART, four general purpose timers, and up to 42 general purpose I/O pins.1.2 How to read this manualThis user manual describes parts LPC1311, LPC1313, LPC1342, LPC1343. Part-specificfeatures and registers are listed at the beginning of each chapter.Remark: The LPC13xx series consists of the LPC1300 series (parts LPC1311/13/42/43)and the LPC1300L series (parts LPC1311/01 and LPC1313/01). The LPC1300L seriesfeatures the following enhancements over the LPC1300 series: Power profiles with lower power consumption in Active and Sleep modes.Four levels for BOD forced reset.Second SSP controller (LPC1313FBD48/01 only).Windowed Watchdog Timer (WWDT).Internal pull-up resistors pull up pins to full VDD level.Programmable pseudo open-drain mode for GPIO pins.1.3 Features ARM Cortex-M3 processor, running at frequencies of up to 72 MHz. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). 32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programmingmemory. 8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM. In-System Programming (ISP) and In-Application Programming (IAP) via on-chipbootloader software. Selectable boot-up: UART or USB (USB on LPC134x only). On LPC134x: USB MSC and HID on-chip drivers. Serial interfaces:UM10375User manualAll information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.4 of 370
UM10375NXP SemiconductorsChapter 1: LPC13xx Introductory information– USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43only).– UART with fractional baud rate generation, modem, internal FIFO, andRS-485/EIA-485 support.– SSP controller with FIFO and multi-protocol capabilities.– Additional SSP controller on LPC1313FBD48/01.– I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with adata rate of 1 Mbit/s with multiple address recognition and monitor mode. Other peripherals:– Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-downresistors.– Four general purpose counter/timers with a total of four capture inputs and 13match outputs.– Programmable WatchDog Timer (WDT).– Programmable Windowed Watchdog Timer (WWDT) on LPC1311/01 andLPC1313/01.– System tick timer. Serial Wire Debug and Serial Wire Trace port.High-current output driver (20 mA) on one pin.High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.Integrated PMU (Power Management Unit) to minimize power consumption duringSleep, Deep-sleep, and Deep power-down modes. Power profiles residing in boot ROM allowing to optimize performance and minimizepower consumption for any given application through one simple function call.(LPC1300L series, on LPC1311/01 and LPC1313/01 only.) Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.Single power supply (2.0 V to 3.6 V).10-bit ADC with input multiplexing among 8 pins.GPIO pins can be used as edge and level sensitive interrupt sources.Clock output function with divider that can reflect the system oscillator clock, IRCclock, CPU clock, or the watchdog clock. Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40of the functional pins. Brownout detect with four separate thresholds for interrupt and one threshold forforced reset (four thresholds for forced reset on the LPC1311/01 and LPC1313/01parts). Power-On Reset (POR). Integrated oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperatureand voltage range that can optionally be used as a system clock. Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.UM10375User manualAll information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.5 of 370
UM10375NXP SemiconductorsChapter 1: LPC13xx Introductory information System PLL allows CPU operation up to the maximum CPU rate without the need fora high-frequency crystal. May be run from the system oscillator or the internal RCoscillator. For USB (LPC1342/43), a second, dedicated PLL is provided.Code Read Protection (CRP) with different security levels.Unique device serial number for identification.Available as 48-pin LQFP package and 33-pin HVQFN package.1.4 Ordering optionsTable 1.Ordering informationType FN33HVQFN33: plastic thermal enhanced very thin quad flat package; noleads; 33 terminals; body 7 7 0.85 mmn/aLPC1311FHN33/01HVQFN33HVQFN33: plastic thermal enhanced very thin quad flat package; noleads; 33 terminals; body 7 7 0.85 mmn/aLPC1313FHN33HVQFN33HVQFN33: plastic thermal enhanced very thin quad flat package; noleads; 33 terminals; body 7 7 0.85 mmn/aLPC1313FHN33/01HVQFN33HVQFN33: plastic thermal enhanced very thin quad flat package; noleads; 33 terminals; body 7 7 0.85 mmn/aLPC1313FBD48LQFP48LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC1313FBD48/01LQFP48LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC1342FHN33HVQFN33HVQFN33: plastic thermal enhanced very thin quad flat package; noleads; 33 terminals; body 7 7 0.85 mmn/aLPC1342FBD48LQFP48LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2LPC1343FHN33HVQFN33HVQFN33: plastic thermal enhanced very thin quad flat package; noleads; 33 terminals; body 7 7 0.85 mmn/aLPC1343FBD48LQFP48LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mmSOT313-2Table 2.Ordering options for LPC13xxType Fast SSP ADCPinschannelsPackageLPC1311FHN338 kB4 kB-no111833HVQFN33LPC1311FHN33/018 kB4 kB-yes111833HVQFN33LPC1313FHN3332 kB8 kB-no111833HVQFN33LPC1313FHN33/0132 kB8 kB-yes111833HVQFN33LPC1313FBD4832 kB8 kB-no111848LQFP48LPC1313FBD48/0132 kB8 kB-yes112848LQFP48LPC1342FHN3316 kB4 kBDeviceno111833HVQFN33UM10375User manualAll information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.6 of 370
UM10375NXP SemiconductorsChapter 1: LPC13xx Introductory informationTable 2.Ordering options for LPC13xxType Fast SSP ADCPinschannelsPackageLPC1342FBD4816 kB4 kBDeviceno111848LQFP48LPC1343FHN3332 kB8 kBDeviceno111833HVQFN33LPC1343FBD4832 kB8 kBDeviceno111848LQFP48UM10375User manualAll information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.7 of 370
UM10375NXP SemiconductorsChapter 1: LPC13xx Introductory information1.5 Block diagramXTALINXTALOUTRESETUSB pinsSWDLPC1311/13/42/43USB PHY(1)TEST/DEBUGINTERFACEIRCCLOCKGENERATION,POWER odebusUSB DEVICECONTROLLER(1)systembusPORCLKOUTclocks andcontrolsslaveslaveROMAHB-LITE BUSGPIO portsPIO0/1/2/3slaveHIGH-SPEEDGPIORXDTXDDTR, DSR(2), CTS,DCD(2), RI(2), RTSCT32B0 MAT[3:0]CT32B0 CAP0CT32B1 MAT[3:0]CT32B1 CAP0CT16B0 MAT[2:0]CT16B0 CAP0CT16B1 MAT[1:0]CT16B1 CAP0slaveSRAM4/8 kBslaveslaveFLASH8/16/32 kBAHB TOAPBBRIDGEUARTAD[7:0]10-bit ADCSSP0SCK0,SSEL0MISO0, MOSI0SSP1(3)SCK1,SSEL1MISO1, MOSI0I2C-BUSSCLSDA32-bit COUNTER/TIMER 032-bit COUNTER/TIMER 116-bit COUNTER/TIMER 0WDT/WWDT(4)16-bit COUNTER/TIMER 1IOCONFIGSYSTEM CONTROL002aae722(1) LPC1342/43 only.(2) LQFP48 package only.(3) On LPC1313FBD48/01 only.(4) Windowed WatchDog Timer (WWDT) on LPC1311/01 and LPC1313/01 only.Fig 1.LPC13xx block diagramUM10375User manualAll information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.8 of 370
UM10375Chapter 2: LPC13xx Memory mappingRev. 5 — 21 June 2012User manual2.1 How to read this chapterSee Table 3 for LPC13xx memory configurations:Table 3.LPC13xx memory configurationPartFlash Address rangeSRAMAddress rangeLPC13118 kB0x0000 0000 - 0x0000 1FFF4 kB0x1000 0000 - 0x1000 0FFFLPC1311/018 kB0x0000 0000 - 0x0000 1FFF4 kB0x1000 0000 - 0x1000 0FFFLPC131332 kB0x0000 0000 - 0x0000 7FFF8 kB0x1000 0000 - 0x1000 1FFFLPC1313/0132 kB0x0000 0000 - 0x0000 7FFF8 kB0x1000 0000 - 0x1000 1FFFLPC134216 kB0x0000 0000 - 0x0000 3FFF4 kB0x1000 0000 - 0x1000 0FFFLPC134332 kB0x0000 0000 - 0x0000 7FFF8 kB0x1000 0000 - 0x1000 1FFF2.2 Memory mapFigure 2 shows the memory and peripheral address space of the LPC13xx.The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.On the LPC13xx, the GPIO ports are the only AHB peripherals. The APB peripheral areais 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of eithertype is allocated 16 kB of space. This allows simplifying the address decoding for eachperipheral.All peripheral register addresses are 32-bit word aligned regardless of their size. Animplication of this is that word and half-word registers must be accessed all at once. Forexample, it is not possible to read or write the upper byte of a word register separately.UM10375User manualAll information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.9 of 370
UM10375NXP SemiconductorsChapter 2: LPC13xx Memory mapping4 GBAHB peripheralsLPC1311/13/42/430x5020 00000xFFFF FFFFreserved0xE010 0000private peripheral bus16 - 127 reserved0xE000 00000x5004 000012-15GPIO PIO30x5020 00008-11GPIO PIO20x5000 00004-7GPIO PIO10-3GPIO PIO0reservedAHB peripherals0x5003 00000x5002 00000x5001 00000x5000 0000reservedAPB peripherals0x4008 000023 - 31 reserved0x4008 00001 GBAPB peripherals0x4005 C00022 SSP1 (LPC1313FBD48/01) 0x4005 800019 - 21 reserved0x4004 C0000x4000 0000reserved18system control17IOCONFIG1615SSP0flash controller14PMU0x4004 80000x4004 40000x4004 00000x4003 C0000x4003 80000x2000 00000.5 GB10 - 13 reservedreserved0x4002 80000x1FFF 400016 kB boot ROM0x1FFF 0000reserved0x1000 2000I-code/D-codememory space8 kB SRAM (LPC1313/1343)0x1000 10004 kB SRAM (LPC1311/1342)0x1000 0000reserved9reserved8USB (LPC1342/43 only)0x4002 00007ADC0x4001 C000632-bit counter/timer 10x4001 8000532-bit counter/timer 00x4001 4000416-bit counter/timer 10x4001 0000316-bit counter/timer 00x4000 C0002UART0x4000 800010WDT/WWDT0x4000 4000I2C-bus0x4000 00000x4002 40000x0000 800032 kB on-chip flash (LPC1313/43)0x0000 400016 kB on-chip flash (LPC1342)0 GB 256 words0x0000 20008 kB on-chip flash (LPC1311)active interrupt vectors0x0000 04000x0000 00000x0000 0000002aae723Fig 2.LPC13xx memory map2.3 Memory remappingFor details, see Table 8.UM10375User manualAll information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.10 of 370
UM10375Chapter 3: LPC13xx System configurationRev. 5 — 21 June 2012User manual3.1 How to read this chapterThe system configuration registers apply to all LPC13xx parts with the followingexceptions:USB clocking and power controlSince the USB block is available on the LPC1342 and LPC1343 only, the registers andregister bits listed in Table 4 are reserved for parts LPC1311 and LPC1313:Table 4.USB related registers and register bits reserved for LPC1311/13NameAccessAddress DescriptionoffsetRegister bitsreserved forLPC1311/13USBPLLCTRLR/W0x010USB PLL controlallUSBPLLSTATR0x014USB PLL statusallUSBPLLCLKSELR/W0x048USB PLL clock source selectallUSBPLLCLKUENR/W0x04CUSB PLL clock source update enableallSYSAHBCLKCTRL R/W0x080System AHB clock controlbit 14USBCLKSELR/W0x0C0USB clock source selectallUSBCLKUENR/W0x0C4USB clock source update enableallUSBCLKDIVR/W0x0C8USB clock source dividerallPDSLEEPCFGR/W0x230Power-down states in Deep-sleepmodebits 8 and 10PDAWAKECFGR/W0x234Power-down states after wake-up from bits 8 and 10Deep-sleep modePDRUNCFGR/W0x238Power-down configuration registerbits 8 and 10SSP1The SSP1 block is available on the LPC1313FBD48/01 only. SSP1 related registers andregister bits are reserved for the following parts: LPC1311/13/42/43 andLPC1311FHN33/01 and LPC1313FHN33/01.BOD controlThe number of programmable BOD levels for forced reset is different for the LPC1300 andthe LPC1300L series. See Table 5. The BOD trip levels for the LPC1300 and LPC1300Lseries are listed in the LPC1311/13/42/43 data sheet.Table 5.UM10375User manualBOD interrupt and reset levelsSeriesType numberInterrupt levelsReset levelsLPC1300LPC1311FHN334 (programmable)1 (fixed)LPC1300LPC1313FBD484 (programmable)1 (fixed)LPC1300LPC1313FHN334 (programmable)1 (fixed)LPC1300LPC1342FHN334 (programmable)1 (fixed)LPC1300LPC1343FBD484 (programmable)1 (fixed)All information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.11 of 370
UM10375NXP SemiconductorsChapter 3: LPC13xx System configurationTable 5.BOD interrupt and reset levelsSeriesType numberInterrupt levelsReset levelsLPC1300LPC1343FHN334 (programmable)1 (fixed)LPC1300LLPC1311FHN33/014 (programmable)4 (programmable)LPC1300LLPC1313FHN33/014 (programmable)4 (programmable)LPC1300LLPC1313FBD48/014 (programmable)4 (programmable)Input pins to the start logicFor HVQFN packages, the start logic control bits (see Table 44 to Table 51) are reservedfor port pins PIO2 1 to PIO2 11 and PIO3 0, PIO3 1, and PIO3 3.PIO reset status registersFor HVQFN packages, the reset status bits (see Table 40 and Table 41) are reserved forport pins PIO2 1 to PIO2 11 and PIO3 0 and PIO3 1, and PIO3 3.Entering Deep power-down modeStatus of the IRC before entering Deep power-down mode (see Section 3.9.4.2): IRC must be enabled for parts LPC1311/13/42/43. IRC status has no effect for parts LPC1311/01 and LPC1313/01.Enabling sequence for UART clockRequirements for enabling the UART peripheral clock: The UART pins must be configured in the IOCON block before the UART clock can be enabledin the in the SYSAHBCLKCTRL register (Table 25) for parts LPC1311/13/42/43. The sequence of configuring the UART pins and the UART clock has no effect forparts LPC1311/01 and LPC1313/01.Deep-sleep mode configurationRegister values configuring the Deep-sleep mode are different for the LPC1300 (partsLPC1311/13/42/43) and LPC1300L (parts LPC1311/01 and LPC1313/01) series (seeSection 3.5.45, the PDSLEEPCFG register).3.2 IntroductionThe system configuration block controls oscillators, the power management unit, andclock generation of the LPC13xx. Also included in this block are registers for setting thepriority for AHB access and a register for remapping flash, SRAM, and ROM memoryareas.UM10375User manualAll information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.12 of 370
UM10375NXP SemiconductorsChapter 3: LPC13xx System configuration3.3 Pin descriptionTable 6 shows pins that are associated with system control block functions.Table 6.Pin summaryPin nameUser manualPin descriptionCLKOUTOClockout pinPIO0 0 to PIO0 11IWake-up pins port 0PIO1 0 to PIO1 11IWake-up pins port 1PIO2 0 toPIO2 11[1]IWake-up pins port 2PIO3 0 toPIO3 3[1]IWake-up pins port 3[1]UM10375PindirectionFor HVQFN packages, applies to P2 0, P3 2, and P3 3 only.All information provided in this document is subject to legal disclaimers.Rev. 5 — 21 June 2012 NXP B.V. 2012. All rights reserved.13 of 370
UM10375NXP SemiconductorsChapter 3: LPC13xx System configuration3.4 Clocking and power controlSee Figure 3 for an overview of the LPC13xx Clock Generation Unit (CGU).The LPC131x include three independent oscillators. These are the system oscillator, theInternal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used formore than one purpose as required in a particular application.Following reset, the LPC131x will operate from the Internal RC oscillator until switched bysoftware. This allows systems to operate without any external crystal and the bootloadercode to operate at a known frequency.The SYSAHBCLKCTRL regis
For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors UM10375 LPC13xx User manual 3 20110614 LPC1311/13/42/43 user manual Modifications: Parts LPC1311/01 and LPC1313/01 added. Modifications to the user manual applicable to parts LPC1311/01 and LPC1313/01 only:
Rational Rational Rational Irrational Irrational Rational 13. 2 13 14. 0.42̅̅̅̅ 15. 0.39 16. 100 17. 16 18. 43 Rational Rational Rational Rational Rational Irrational 19. If the number 0.77 is displayed on a calculator that can only display ten digits, do we know whether it is rational or irrational?
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Common Sense Mathematics Extra Exercises Ethan D. Bolker Maura B. Mast Draft 2019-07-27 2019-07-27. Contents Extra Exercises 2 1 Calculating on the Back of an Envelope 3 2 Units and Unit Conversions 16 3 Percentages, Sales Tax and Discounts 26 4 Inflation 38 5 Average Values 42
