Design Rules MOSIS Scalable CMOS (SCMOS)
Vendor-independent, scalable rules (MOSIS SCMOS Rules)Design RulesMOSIS Scalable CMOS (SCMOS)(Revision 8.00)Updated: May 11, 20091. IntroductionThis document defines the official MOSIS scalable CMOS (SCMOS) layout rules. Itsupersedes all previous revisions.MOSIS Scalable CMOS (SCMOS) is a set of logical layers together with their design rules,which provide a nearly process- and metric-independent interface to many CMOSfabrication processes available through MOSIS. The designer works in the abstract SCMOSlayers and metric unit ("lambda"). He then specifies which process and feature size hewants the design to be fabricated in. MOSIS maps the SCMOS design onto that process,generating the true logical layers and absolute dimensions required by the processvendor. The designer can often submit exactly the same design, but to a differentfabrication process or feature size. MOSIS alone handles the new mapping.By contrast, using a specific vendor's layers and design rules ("vendor rules") will yield adesign which is less likely to be directly portable to any other process or feature size.Vendor rules usually need more logical layers than the SCMOS rules, even though bothfabricate onto exactly the same process. More layers means more design rules, a higherlearning curve for that one process, more interactions to worry about, more complexdesign support required, and longer layout development times. Porting the design to anew process will be burdensome.SCMOS designers access process-specific features by using MOSIS-provided abstractlayers which implement those features. For example, a designer wishing to use secondpoly would use the MOSIS-provided second-poly abstract layer, but must then submit to aprocess providing for two polysilicon layers. In the same way, designers may accessmultiple metals, or different types of analog structures such as capacitors and resistors,without having to learn any new set of design rules for the more standard layers such asmetal-1. SCMOS is there for portability and simplicity. It is NOT there for fine-tunedlayout.Vendor rules may be more appropriate when seeking maximal use of silicon area, moredirect control over analog circuit parameters, or for very large production runs, where the
added investment in development time and loss of design portability is clearly justified.However the advantages of using SCMOS rules may far outweigh such concerns, andshould be considered.1.1 SCMOS Design RulesIn the SCMOS rules, circuit geometries are specified in the Mead and Conway's lambdabased methodology [1]. The unit of measurement, lambda, can easily be scaled todifferent fabrication processes as semiconductor technology advances.Each design has a technology-code associated with the layout file. Each technology-codemay have one or more associated options added for the purpose of specifying either (a)special features for the target process or (b) the presence of novel devices in the design.At the time of this revision, MOSIS is offering CMOS processes with feature sizes from 1.5micron to 0.18 micron.2. Standard SCMOSThe standard CMOS technology accessed by MOSIS is a single polysilicon, double metal,bulk CMOS process with enhancement-mode n-MOSFET and p-MOSFET devices [3].2.1. Well TypeThe Scalable CMOS (SC) rules support both n-well and p-well processes. MOSISrecognizes three base technology codes that let the designer specify the well type of theprocess selected. SCN specifies an n-well process, SCP specifies a p-well process, and SCEindicates that the designer is willing to utilize a process of either n-well or p-well.An SCE design must provide both a drawn n-well and a drawn p-well; MOSIS will use thewell that corresponds to the selected process and ignore the other well. As a convenience,SCN and SCP designs may also include the other well (p-well in an SCN design or n-well inan SCP design), but it will always be ignored.MOSIS currently offers only n-well processes or foundry-designated twin-well processesthat from the design and process flow standpoints are equivalent to n-well processes.These twin-well processes may have options (deep n-well) that provide independentlyisolated p-wells. For all of these processes at this time use the technology code SCN. SCPis currently not supported, and SCE is treated exactly as SCN.
2.2. SCMOS OptionsSCMOS options are used to designate projects that use additional layers beyond thestandard single-poly, double metal CMOS. Each option is called out with a designator thatis appended to the basic technology-code. Please note that not all possible combinationsare available. The current list is shown in Table 1.MOSIS has not issued SCMOS design rules for some vendor-supported options. Forexample, any designer using the SCMOS rules who wants the TSMC Thick Top Metal mustdraw the top metal to comply with the TSMC rules for that layer. Questions about othernon-SCMOS layers should be directed to support@mosis.com.Table 1: SCMOS Technology OptionsDesignation Long FormDescriptionEElectrodeAdds a second polysilicon layer (poly2) that can serveeither as the upper electrode of a poly capacitor or (1.5micron only) as a gate for transistorsAAnalogAdds electrode (as in E option), plus layers for verticalNPN transistor pbase3M3 MetalAdds second via (via2) and third metal (metal3) layers4M4 MetalAdds 3M plus third via (via3) and fourth metal (metal4)layers5M5 MetalAdds 4M plus fourth via (via4) and fifth metal (metal5)layers6M6 MetalAdds 5M plus fifth via (via5) and sixth metal (metal6)layersLCLinearCapacitorAdds a cap well layer for linear capacitorsPCPoly CapAdds poly cap, a different layer for linear capacitorsSUBMSub-MicronUses revised layout rules for better fit to sub-micronprocesses (see section 2.4)DEEPDeepUses revised layout rules for better fit to deep submicron processes (see section 2.4)
For options available to specific processes, see Tables 2a and 2b.Table 2a: MOSIS SCMOS-Compatible MappingsFoundry ProcessLambda (micrometers)OptionsONSemiC5F/N (0.5 micron n-well)0.35SCN3M,SCN3METSMC0.35 micron 2P4M (4 Metal Polycided,3.3 V/5 V)0.25SCN4METSMC0.35 micron 1P4M (4 Metal Silicided, 3.3 0.25V/5 V)SCN4MTable 2b: MOSIS SCMOS SUBM-Compatible MappingsFoundry ProcessLambda (micrometers)OptionsONSemiC5F/N (0.5 micron n-well)0.30SCN3M SUBM,SCN3ME SUBMTSMC0.35 micron 2P4M (4 MetalPolycided, 3.3 V/5 V)0.20SCN4ME SUBMTSMC0.35 micron 1P4M (4 MetalSilicided, 3.3 V/5 V)0.20SCN4M SUBMTSMC0.25 micron 5 Metal 1 Poly (2.5 0.15V/3.3 V)SCN5M SUBMTSMC0.18 micron 6 Metal 1 Poly (1.8 0.10V/3.3 V)SCN6M SUBM
Table 2c: MOSIS SCMOS DEEP-Compatible MappingsFoundry ProcessLambda (micrometers)OptionsTSMC0.25 micron 5 Metal 1 Poly (2.5 V/3.3V)0.12SCN5M DEEPTSMC0.18 micron 6 Metal 1 Poly (1.8 V/3.3V)0.09SCN6M DEEP2.3. SCMOS-Compatible ProcessesMOSIS currently offers the fabrication processes shown above in Tables 2a, 2b, and 2c.For each process the list of appropriate SCMOS technology-codes is shown.2.4. SCMOS SUBM and SCMOS DEEP RulesThe SCMOS layout rules were historically developed for 1.0 to 3.0 micron processes. Totake full advantage of sub-micron processes, the SCMOS rules were revised to createSCMOS SUBM. By increasing the lambda size for some rules (those that didn't shrink asfast in practice as did the overall scheme of things), the sub-micron rules allow for use ofa smaller value of lambda, and better fit to these small feature size processes.The SCMOS SUBM rules were revised again at the 0.25 micron regime to better fit thetypical deep submicron processes, creating the SCMOS DEEP variant.Table 3a lists the differences between SCMOS and SCMOS sub-micron. Table 3b lists thedifferences between SCMOS sub-micron and SCMOS deep.Table 3a: SCMOS and SCMOS Sub-micron Differences DifferencesRuleDescriptionSCMOSSCMOSsub-micron1.1, 17.1Well width10121.2, 17.2Well space(different potential)9182.3Well overlap56
(space) to transistor3.2Poly space235.3, 6.3Contact space235.5bContact to Polyspace to Poly457.2Metal1 space237.4Minimum space(when metal line is wider than 10 lambda)468.5Via on flat2Unrestricted11.1Poly2 width3711.3Poly2 overlap2511.5Space to Poly2 contact3613.2Poly2 contact space2315.1Metal3 width(3 metal process only)6515.2Metal3 space(3 metal process only)4315.4Minimum space(when metal line is wider than 10 lambda)(3 metal process only)8617.3Minimum spacing to external Active5617.4Minimum overlap of Active56Table 3b: SCMOS Sub-micron and SCMOS Deep 3.2Poly spaceover field33
3.2.aPoly spaceover Active43.3Minimumgate extensionof Active22.53.4Active extensionbeyond Poly344.3Select overlapof Contact11.54.4Select width and space(p to p or n to n )245.3, 6.3Contact spacing348.1Via width239.2Metal2 space349.4Minimum space(when metal line is wider than 10 lambda)6814.1Via2 width2315.2Metal3 space3415.4Minimum space(when metal line is wider than 10 lambda)(for 4 metal processes)6821.1Via3 width2322.2Metal4 space(for 5 metal processes)3422.4Minimum space(when metal line is wider than 10 lambda)6825.1Exact size2x23x326.2Metal5 space3426.3Minimum overlap of Via412
(for 5 metal process only)26.4Via4 overlap6829.1Exact size3x34x430.3Minimum overlap of Via5123. CIF and GDS Layer SpecificationA user design submitted to MOSIS using the SCMOS rules can be in either Calma GDSIIformat [2] or Caltech Intermediate Form (CIF version 2.0) [1]. The two are completelyinterchangable. Note that all submitted CIF and GDS files have already been scaled beforesubmission, and are always in absolute metric units -- never in lambda units.GDSII is a binary format, while CIF is a plain ASCII text. For detailed syntax and semanticspecifications of GDS and CIF, refer to [2] and [1] respectively.In GDS format, a design layer is specified as a number between 0 and 255. MOSIS SCMOSnow reserves layer numbers 21 through 62, inclusive, for drawn layout. Layers 0 through20 plus layers 63 and above can be used by designers for their own purposes and will beignored by MOSIS.Users should be aware that there is only one contact mask layer, although severalseparate layers were defined and are retained for backward compatibility. A complete listof SCMOS layers is shown in Table 4, along with a list by technology code in Table 5.Table 4: SCMOS Layer MapLayerGDS CIFCIFRuleSynonym SectionNotesN WELL42CWN1P WELL41CWP1SCPxxCAP WELL59CWC17, 18SCN3MLCACTIVE43CAA2THICKACTIVE60CTA24SCN4M (TSMC only), SCN4ME,SCN5M, SCN6M
PBASE58CBA16SCNAPOLY CAP128CPC23SCNPCPOLY46CPG3SILICIDEBLOCK29CSB20N PLUSSELECT45CSN4P PLUSSELECT44CSP4POLY256CEL11, 12,13SCNE, SCNA, SCN3ME, SCN4MEHI P5Can be replaced by CONTACTACTIVECONTACT48CCA6Can be replaced by CONTACTPOLY2CONTACT55CCE13SCNE, SCNA, SCN3ME, SCN4MECan be replaced by VIA261CV2CVS14SCN3M, SCN3ME, SCN3MLC,SCN4M, SCN4ME, SCN5M,SCN6MMETAL362CM3CMT15SCN3M, SCN3ME, SCN3MLC,SCN4M, SCN4ME, SCN5M,SCN6MCCGSCN3M, SCN4M (TSMC only),SCN5M, SCN6M5, 6, 13
VIA330CV3CVT21SCN4M, SCN4ME, SCN5M,SCN6MMETAL431CM4CMQ22SCN4M, SCN4ME, SCN5M,SCN6MCAP TOPMETAL35CTM28SCN5M. SCN6MVIA432CV4CVQ25SCN5M, SCN6MMETAL533CM5CMP26SCN5M, SCN6MVIA536CV529SCN6MMETAL637CM630SCN6MDEEPN WELL38CDNW31SCN5M, SCN6MGLASS52COG10PADS26XPOptional non-fab layer used solelyto highlight the bonding pads.Comments--CXCommentsTable 5: Technology-code MapTechnologycodewith link tolayer mapLayersSCNEN well, Active, N select, P select, Poly, Poly2, Contact, Metal1, Via,Metal2, GlassSCNAN well, Active, N select, P select, Poly, Poly2, Contact, Pbase,Metal1, Via, Metal2, GlassSCNPCN well, Active, N select, P select, Poly cap, Poly, Contact, Metal1,Via, Metal2, GlassSCN3MN well, Active, N select, P select, Poly, Hi Res Implant, Contact,
Metal1, Via, Metal2, Via2, Metal3, GlassSCN3MEN well, Active, N select, P select, Poly, Poly2, Hi Res Implant,Contact, Metal1, Via, Metal2, Via2, Metal3, GlassSCN3MLCN well, Cap well, Active, N select, P select, Poly, Silicide block,Contact, Metal1, Via, Metal2, Via2, Metal3, GlassSCN4MN well, Active, Thick Active (TSMC only), N select, P select, Poly,Contact, Metal1, Via, Metal2, Via2, Metal3, Via3, Metal4, GlassSCN4MEN well, Active, Thick Active, N select, P select, Poly, Poly2,Contact, Metal1, Via, Metal2, Via2, Metal3, Via3, Metal4, GlassSCN5MN well, Active, Thick Active, N select, P select, Poly, Silicide block,Contact, Metal1, Via, Metal2, Via2, Metal3, Via3, Metal4,Cap Top Metal, Via4, Metal5, Deep N Well, GlassSCN6MN well, Active, Thick Active, N select, P select, Poly, Silicide block,Contact, Metal1, Via, Metal2, Via2, Metal3, Via3, Metal4, Via4,Metal5, Cap Top Metal, Via5, Metal6, Deep N Well, Glass4. Minimum Density RuleMany fine-featured processes utilize CMP (Chemical-Mechanical Polishing) to achieveplanarity. Currently, for MOSIS, the ON Semi 0.50 micron and all the 0.35 micron (andsmaller) processes are in this category. Effective CMP requires that the variations infeature density on layer be restricted.See the following for more details.5. Process-Induced Damage Rules (otherwise known as "AntennaRules"): General RequirementsThe "Antenna Rules" deal with process induced gate oxide damage caused when exposedpolysilicon and metal structures, connected to a thin oxide transistor, collect charge fromthe processing environment (e.g., reactive ion etch) and develop potentials sufficientlylarge to cause Fowler Nordheim current to flow through the thin oxide. Given the knownprocess charge fluence, a figure of exposed conductor area to transistor gate area ratio isdetermined which guarantees Time Dependent Dielectric Breakdown (TDDB) reliabilityrequirements for the fabricator. Failure to consider antenna rules in a design may lead toeither reduced performance in transistors exposed to process induced damage, or may
lead to total failure if the antenna rules are seriously violated.6. Support for Arbitrary Via Placement by Process and Technology CodesSome processes have restrictions on the placement of vias relative to contacts (rule 8.4)and/or relative to poly and active edges (rule 8.5). Other processes allow arbitraryplacement of vias over these lower features.The placement of vias directly over contacts or other, lower vias is known as "stackedvias."Table 6: Applicability of Rules 8.4 and 8.5Technology code with Processlink to layer map8.4 isWaived8.5 isWaivedSCN3MON Semi 0.50 (C5F/N)YesYesSCN3MEON Semi 0.50 (C5F/N)YesYesSCN4MTSMC 0.35YesYesSCN4METSMC 0.35YesYesSCN5MTSMC 0.25YesYesSCN6MTSMC 0.18YesYes7. Half-lambda grid submissionsMOSIS Scalable design rules require that layout is on a 1 2 lambda grid. Any other griddinginformation may change without warning. We will accept and process a design regardlessof its actual grid (as though it were completely design-rule legal) using the standard"recipe" for that design rule set.The fracture process puts all its data onto a grid. As an example, the mask grid size in thecase of the TSMC 0.35 micron process is 0.0125 micron on the critical layers and 0.025micron on the others, and all points in your layout that do not fall onto these grid pointsare "snapped" to the nearest grid point. Obviously, half a grid is the largest snap distance,applied to points that fall neatly in the middle. The 0.025 fracture grid is 1 8 lambda forSCN4ME SUBM and 1 10 lambda for SCN4ME.8. PADS Layer
MOSIS has defined an optional PADS layer to help users tell MOSIS which glass openingsare to be bonded and which are not. This optional layer lets you call out only those glasscuts that you want MOSIS to use in generating an automated bonding for your project.When used, PADS should match the glass cuts (or the larger metal pads underneath) forjust the selected glass cuts.Geometry on the PADS layer has absolutely no influence on chip fabrication.When the PADS layer is not present, MOSIS will analyze the glass cuts to determine whichappear to be bonding pads and which do not. For the vast majority of layouts, the PADSlayer is unnecessary.References[1] C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, 1980[2] Cadence Design Systems, Inc./Calma. GDSII Stream Format Manual, Feb. 1987,Release 6.0, Documentation No. B97E060[3] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A SystemPerspective, Addison-Wesley, 2nd edition, 1993
SCMOS Layout Rules - DEEP N WELLfor SCMOS DEEP (and SUBM)The DEEP N WELL layer provides access to the DNW layer in the TSMC 0.18and 0.25 processes. This provides a layering sometimes called "triple-well" inwhich an n-well sits in the p-substrate, and then a p-well sits fully inside ofthe n-well; it is then possible to construct NMOS devices inside of thatisolated p-well. The isolated p-well is surrounded by a fence of standardN WELL (around its periphery), and by DEEP N WELL underneath. TheN WELL fence makes direct electrical contact with the DEEP N WELL platebeneath it.DEEP N WELL is available in technology codes SCN5M SUBM, SCN5M DEEP,SCN6M SUBM and SCN6M DEEP but only where these are to be fabricated onTSMC foundry runs. To gain a better understanding of this layer, the TSMCvendor-rule design rule documentation should be studied.LambdaRuleDescriptionSCMOS SUBM DEEP31.1 Minimum Width, Deep N Welln/a303431.2 Minimum Spacing, Deep N Well to Deep N Welln/a505631.3 Minimum extension, N Well beyond Deep N Well edgen/a151731.4 Minimum overlap, N Well over Deep N Well edgen/a202331.5 Minimum spacing, Deep N Well to unrelated N Welln/a353931.6 Minimum spacing, N Active in isolated P-well, to N Welln/a5631.7 Minimum spacing, external N Active to Deep N Welln/a3034n/a101331.8Minimum spacing, P Active in N Well to itsDeep N Well
SCMOS Layout Rules - WellLambdaRuleDescriptionSCMOS SUBM DEEP1.1Minimum width1012121.2Minimum spacing between wells at different potential918181.3Minimum spacing between wells at same potential6661.4Minimum spacing between wells of different type (if both aredrawn)000
SCMOS Layout Rules - Capacitor WellThe capacitor well described in this and the next rule only apply to SCN3MLCand SCN3MLC SUBM technology codes manufactured on an Agilent/HPAMOS14TB inimum width17.2Minimum spacing918n/a17.3Minimum spacing to external active56n/a17.4Minimum overlap of active56n/a
SCMOS Layout Rules - Linear Capacitor(Linear Capacitor Option)These rules illustrate the construction of a linear capacitor in a capacitor well.The capacitor itself is the region of overlapped poly and active. The activearea is electrically connected to the cap wellLambdaRuleDescriptionSCMOSSUBMDEEP18.1Minimum width33n/a18.2Minimum poly extension of active22n/a18.3Minimum active overlap of poly33n/a18.4Minimum poly contact to active22n/a18.5Minimum active contact to poly66n/a
SCMOS Layout Rules - ActiveLambdaRuleDescriptionSCMOS SUBM DEEP2.1Minimum width3*3*32.2Minimum spacing3332.3Source/drain active to well edge5662.4Substrate/well contact active to well edge3332.5Minimum spacing between non-abutting active of differentimplant. Abutting active ("split-active") is illustrated underSelect Layout Rules.444* Note: For analog and critical digital designs, MOSIS recommends the following minimumMOS channel widths (active under poly) for ON Semiconductor designs. Narrower devices,down to design rule minimum, will be functional, but their electrical characteristics will notscale, and their performance is not predictable from MOSIS SPICE parameters.ProcessDesign TechnologyDesign Lambda(micrometers)Minimum Width(lambda)AMI C5F/NSCN3M, SCN3ME0.359AMI C5F/NSCN3M SUBM,SCN3ME SUBM0.3010
SCMOS Layout Rules - Thick ActiveTHICK ACTIVE is a layer used for those processes offering two differentthicknesses of gate oxide (typically for the layout of transistors that operateat two different voltage levels). The ACTIVE layer is used to delineate all theactive areas, regardless of gate oxide thickness. THICK ACTIVE is used tomark those ACTIVE areas that will have the thicker gate oxide; ACTIVE areasoutside THICK ACTIVE will have the thinner gate oxide. THICK ACTIVE byitself (not covering any ACTIVE polygon) is meaningless.LambdaRuleDescriptionSCMOSSUBMDEEP24.1 Minimum width44424.2 Minimum spacing44424.3 Minimum ACTIVE overlap44424.4 Minimum space to external ACTIVE44424.5 Minimum poly width in a THICK ACTIVE gate33324.6Every ACTIVE region is either entirely inside THICK ACTIVE or entirely outsideTHICK ACTIVE
SCMOS Layout Rules - Pbase (Analog Option)The pbase layer is an active area that is implanted with the pbase implant toform the base of the NPN bipolar transistor. The base contact is enclosed in pselect. The emitter is an n-select region within (and on top of) the base. Theentire pbase sits in an n-well that is the collector. The collector contact is awell contact, but the overlaps are larger. Active should not be used inside a16.1All active contact16.2Minimum emitter select overlap of contact3n/an/a16.3Minimum pbase overlap of emitter select2n/an/a16.4Minimum spacing between emitter selectand base select4n/an/a16.5Minimum pbase overlap of base select2n/an/a16.6Minimum base select overlap of contact2n/an/a16.7Minimum nwell overlap of pbase6n/an/a16.8Minimum spacing between pbase and collector active4n/an/a16.9Minimum collector active overlap of contact2n/an/a16.10Minimum nwell overlap of collector active3n/an/a16.11Minimum select overlap of collector active2n/an/a
SCMOS Layout Rules - SCNPC with POLY CAPThe two plates of an SCNPC capacitor are POLY and POLY CAP1. ThePOLY CAP1 must surround the POLY everywhere; the area of the capacitor isthe area of the POLY. POLY is physically on top of POLY CAP1, so that contactto the POLY CAP1 must be made in the region where it extends beyond thePOLY. The capacitor may be in the well or the substrate, but may not straddlea well boundary. The only metal that may cross over a capacitor is theconnecting METAL1 wires.LambdaRuleDescriptionSCMOS SUBM DEEP23.1Minimum POLY CAP1 width. This is lithographic; the minimumto build a real capacitor is greater than 12 lambda8n/an/a23.2Minimum spacing, POLY CAP1 to POLY CAP1 (neighboringcapacitor)4n/an/a23.3Minimum spacing, POLY CAP1 to ACTIVE (all capacitors must beover field)8n/an/a23.4 Minimum overlap, POLY CAP1 over POLY3n/an/a23.5 Minimum overlap, POLY CAP1 over CONTACT2n/an/a2n/an/a23.7 Minimum spacing, POLY to CONTACT-to-POLY CAP12n/an/a23.8 Minimum spacing, unrelated METAL1 to POLY CAP14n/an/a23.9 Minimum spacing, METAL2 to POLY CAP12n/an/a23.6Minimum overlap, POLY over CONTACT (in a capacitor only; still1 lambda elsewhere)
SCMOS Layout Rules - PolyLambdaRuleDescriptionSCMOSSUBMDEEP3.1Minimum width2223.2Minimum spacing over field2333.2.aMinimum spacing over active2343.3Minimum gate extension of active222.53.4Minimum active extension of poly3343.5Minimum field poly to active111
SCMOS Layout Rules - Silicide BlockLambdaRuleDescriptionSCMOSSUBMDEEP20.1Minimum SB width44420.2Minimum SB spacing44420.3Minimum spacing, SB to contact(no contacts allowed inside SB)22220.4Minimum spacing, SB to external active22220.5Minimum spacing, SB to external poly22220.6Resistor is poly inside SB; poly ends stick out for contactsthe entire resistor must be outside well and over field20.7Minimum poly width in resistor55520.8Minimum spacing of poly resistors(in a single SB region)77720.9Minimum SB overlap of poly or active22220.10Minimum poly or active overlap of SB33320.11Minimum spacing, SB to poly(in a single active region)355NOTE: Some processes do not support both silicide block over active andsilicide block over poly. Refer to the individual process description pages.
SCMOS Layout Rules - SelectLambdaRuleDescriptionSCMOS SUBM DEEP4.1Minimum select spacing to channel of transistor to ensureadequate source/drain width3334.2Minimum select overlap of active2224.3Minimum select overlap of contact111.54.4Minimum select width and spacing(Note: P-select and N-select may be coincident, but must notoverlap) (not illustrated)224
SCMOS Layout Rules - Poly2 for CapacitorThe poly2 layer is a second polysilicon layer (physically above the standard,or first, poly layer). The oxide between the two polys is the capacitordielectric. The capacitor area is the area of coincident poly and nimum width37n/a11.2Minimum spacing33n/a11.3Minimum poly overlap25n/a11.4Minimum spacing to active or well edge(not illustrated)22n/a11.5Minimum spacing to poly contact36n/a11.6Minimum spacing to unrelated metal22n/a
SCMOS Layout Rules - Poly2 for TransistorSame poly2 layer as for capsLambdaRuleDescriptionSCMOSSUBMDEEP12.1Minimum width22n/a12.2Minimum spacing33n/a12.3Minimum electrode gate overlap of active22n/a12.4Minimum spacing to active11n/a12.5Minimum spacing or overlap of poly22n/a12.6Minimum spacing to poly or active contact33n/a
SCMOS Layout Rules - Poly2 ContactThe poly2 is contacted through the standard contact layer, similar to the firstpoly. The overlap numbers are larger, however.Contacts must be drawn orthogonal to the grid of the layout. Non-Manhattancontacts are not a13.1Exact contact size13.2Minimum contact spacing23n/a13.3Minimum electrode overlap (on capacitor)33n/a13.4Minimum electrode overlap (not on capacitor)22n/a13.5Minimum spacing to poly or active33n/a
SCMOS Layout Rules - High ResLambdaRuleDescriptionSCMOSSUBMDEEP27.1 Minimum HR width44n/a27.2 Minimum HR spacing44n/aMinimum spacing, HR to contact(no contacts allowed inside HR)22n/a27.4 Minimum spacing, HR to external active22n/a27.5 Minimum spacing, HR to external poly222n/a27.327.6Resistor is poly2 inside HR; poly2 ends stick out for contacts, the entire resistor mustbe outside well and over field27.7 Minimum poly2 width in resistor27.8Minimum spacing of poly2 resistors(in a single HR region)27.9 Minimum HR overlap of poly255n/a77n/a22n/a
SCMOS Layout Rules - Contact to PolyOn 0.50 micron process (and all finer feature size processes), it is requiredthat all features on the insulator layers (CONTACT, VIA, VIA2) must be of thesingle standard size; there are no exceptions for pads (or logos, or anythingelse); large openings must be replaced by an array of standard sizedopenings. Contacts must be drawn orthogonal to the grid of the layout. NonManhattan contacts are not allowed.If your design cannot tolerate 1.5 lambda contact overlap in 5.2, use thealternative rules which reduce the overlap but increase the spacing tosurrounding features. Rules 5.1, 5.3, and 5.4, still apply and are unchanged.SimpleContact to PolyAlternativeContact to S SUBM DEEP5.1Exact contactsize2x22x22x25.2Minimum polyoverlap1.51.51.55.3Minimumcontact spacing2345.4Minimumspacing to gateof transistor222SCMOS SUBM DEEP5.2.bMinimum polyoverlap111Minimum5.5.b spacing to otherpoly455Minimumspacing to5.6.bactive (onecontact)222Minimumspacing to5.7.bactive (manycontacts)333
Simple Poly to ContactAlternative Contact to Poly
SCMOS Layout Rules - Contact to ActiveIf your design cannot handle the 1.5 lambda contact overlap in 6.2, use thealternative rules which reduce the overlap but increase the spacing tosurrounding features. Rules 6.1, 6.3, and 6.4, still apply and are unchanged.Contacts must be drawn orthogonal to the grid of the layout. Non-Manhattancontacts are not allowed.SimpleContact to ActiveAlternativeContact to MOS SUBM DEEP6.1Exact contactsize2x22x22x26.2Minimumactive spacing to gateof transistor26.42SCMOS SUBM DEEP6.2.bMinimum activeoverlap111Minimum6.5.b spacing todiffusion active555Minimumspacing to field6.6.bpoly (onecontact)222Minimumspacing to field6.7.bpoly (manycontacts)333Minimum6.8.b spacing to polycontact4442
Simple Contact to ActiveAlternative Contact to Active
SCMOS Layout Rules - Metal1LambdaRuleDescriptionSCMOS SUBM DEEP7.1Minimum width3337.2Minimum spacing2337.3Minimum overlap of any contact1117.4Minimum spacing when either metal line is wider than 10lambda466
SCMOS Layout Rules - ViaVias must be drawn orthogonal to the grid of the layout. Non-Manhattan viasare not allowed.LambdaRuleDescription2 Metal Process3 Metal ProcessSCMOS SUBM DEEP SCMOS SUBM DEEP8.1Exact size2x2n/an/a2x22x23x38.2Minimum via1 spacing3n/an/a3338.3Minimum overlap by metal11n/an/a1118.4Minimum spacing to contact fortechnology codes mapped to processesthat do not allow stacked vias (SCNA,SCNE, SCN3M, SCN3MLC)2n/an/a22n/aMinimum spacing to poly or active edgefor technology codes mapped toprocesses that do not allow stacked vias(NOTE: list is not same as for 8.4)2n/an/a22n/a8.5
SCMOS Layout Rules - Metal2LambdaRuleDescription2 Metal Process3 Metal ProcessSCMOS SUBM DEEP SCMOS SUBM DEEP9.1Minimum width3n/an/a3339.2Minimum spacing3n/an/a3349.3Minimum overlap of via11n/an/a1119.4Minimum spacing when either metal lineis wider than 10 lambda6n/an/a668
SCMOS Layout Rules - Via2Vias must be drawn orthogonal to the grid of the layout. Non-Manhattan viasare not allowed.LambdaRuleDescription3 Metal Process4 Metal 314.1Exact size14.2Minimum spacing33n/a33314.3Minimum overlap by metal211n/a11114.4Via2 may be placed over via114.5Via2 may be placed over contact
SCMOS Layout Rules - Metal3LambdaRuleDescription3 Metal Process4 Metal ProcessSCMOS SUBM DEEP SCMOS SUBM DEEP15.1 Minimum width65n/a33315.2 Minimum spacing to metal343n/a33415.3 Minimum overlap of via222n/a11186n/a66815.4Minimum spacing when either metal lineis wider than 10 lambda
SCMOS Layout Rules - Via3Vias must be drawn orthogonal to the grid of the layout. Non-Manhattan viasare not allowed.LambdaRuleDescription4 metal Process5 Metal ProcessSCMOS SUBM DEEP SCMOS SUBM DEEP21.1 Exact size2x22x
May 11, 2009 · special features for the target process or (b) the presence of novel devices in the design. At the time of this revision, MOSIS is offering CMOS processes with feature sizes from 1.5 micron to 0.18 micron. 2. Standard SCMOS The standard CMOS technology
CMOS Digital Circuits Types of Digital Circuits Combinational . – Parallel Series – Series Parallel. 15 CMOS Logic NAND. 16 CMOS Logic NOR. 17 CMOS logic gates (a.k.a. Static CMOS) . nMOS and pMOS are not ideal switches – pMOS passes strong 1 , but degraded (weak) 0
8. n-CH Pass Transistors vs. CMOS X-Gates 9. n-CH Pass Transistors vs. CMOS X-Gates 10. Full Swing n-CH X-Gate Logic 11. Leakage Currents 12. Static CMOS Digital Latches 13. Static CMOS Digital Latches 14. Static CMOS Digital Latches 15. Static CMOS Digital Latches . Joseph A. Elias, PhD 2
SOI CMOS technology has been used to integrate analog circuits. In this section, SOI CMOS op amp is discussed. Then, the performance comparison of op amps using bulk and SOI CMOS technologies is presented. 3.1 Analysis on SOI CMOS Op amp Figure 5 shows an SOI CMOS single stage op amp with a symmetrical topology. This circuit has a good .
CMOS Setup Procedure for Dispense System CPU Board PN 2025-0121 CMOS Setup Procedure Use this procedure to set computer CMOS parameters for dispense system CPU board (PN 2025-0121) with CPU, memory, and fan. 1. Activate BIOS/CMOS Setup Utility (pg 1) 2. Preset CPU board (pg 2) 3. Computer CMOS Parameters (pg 2) 4. Save Changes (pg 5) Revision .
Circuits-A CMOS VLSI Design Slide 2 Outline: Circuits Lecture A – Physics 101 – Semiconductors for Dummies – CMOS Transistors for logic designers Lecture B – NMOS Logic – CMOS Inverter and NAND Gate Operation – CMOS Gate Design – Adders – Multipliers Lecture C – P
Iineal circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C2MOS logic functions. Static CMOS functions can ;also be employed. Logic composition rules to mix dynamic CMOS, C 2MOS, and conventional CMOS will be presented. Different from
High-Speed CMOS Characteristics Table 1 compares the main characteristics of the high-speed CMOS family with those of standard TTL, LS, S, ALS, AS, and metal-gate CMOS. Table 1. Performance Comparison of High-Speed CMOS With Several Other Logic Families TECHNOLOGY† SILICON-GATE CMOS AHC METAL-GATE
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