AND9135 - LC Selection Guide For The DC-DC Synchronous .
AND9135/DLC Selection Guide for theDC-DC Synchronous BuckConverterIntroductionhttp://onsemi.comSwitched mode power converters are very prominent inindustry today, and provide high efficiency solutions for awide range of applications. Switched mode converters canbe found in power supplies and battery charging circuitry forcomputers, electric tools, televisions, media tablets, smartphones, automobiles, and countless other electronic devices.One of the most popular converters for the consumerelectronics industry is the DC:DC step down converter, alsoknown as the buck converter.The synchronous buck converter is used to step a voltagedown from a higher level to a lower level. With industrymoving to higher performance platforms, efficiency of thepower converter is critical. The design of the powerconverter must be optimized to maximize performance andto meet customer requirements. Because of this, it isimportant to understand the fundamentals of thesynchronous buck converter and how to appropriately selectthe circuit components.APPLICATION NOTEthis time, Q2 is off and the current through the inductorincreases, charging the LC filter. When Q1 turns off, Q2turns on and current is supplied to the load through the lowside MOSFET. During this time, the current through theinductor decreases, discharging the LC filter. The low sideMOSFET provides an additional function when bothMOSFETs are off. It clamps the switch node voltage via thebody diode to prevent VSW from going too far negativewhen the high side transistor first turns off.Synchronous Buck Converter BasicsThe synchronous buck converter is straightforward inconcept, and is used heavily in consumer electronics. Asynchronous buck converter produces a regulated voltagethat is lower than its input voltage, and can deliver highcurrents while minimizing power loss. As shown inFigure 1, the synchronous buck converter is comprised oftwo power MOSFETs, an output inductor and an outputcapacitor. This specific buck topology derives its name fromthe control method of the two power MOSFETs; the on / offcontrol is synchronized in order to provide a regulatedoutput voltage and to prevent the MOSFETs from turning onat the same time.Figure 2. Synchronous Buck ConverterWaveformsFigure 2 shows the basic waveforms for the synchronousbuck converter in continuous conduction mode. The totalchange in inductor current is known as the peak to peakinductor current, DIL. The switch node voltage is smoothedout by the LC output stage in order to produce a regulatedDC voltage at the output. The MOSFETs are controlledsynchronously to prevent shoot through. Shoot throughoccurs when the high side and low side MOSFET are bothon at the same time, providing a direct short to ground.Figure 1. Synchronous Buck ConverterQ1, the high side MOSFET, is connected directly to theinput voltage of the circuit. When Q1 turns on, current issupplied to the load through the high side MOSFET. During Semiconductor Components Industries, LLC, 2013April, 2013 Rev. 01Publication Order Number:AND9135/D
AND9135/Dand output voltage overshoot, but increases the time it takesthe output voltage feedback loop to respond to changes inload. Therefore, a minimum capacitance must be considered,in order to meet the ripple voltage and voltage overshootrequirements of the converter, while maintaining a feedbackloop that can respond quickly enough to load changes.Capacitors also have a parasitic series resistance, knownas the equivalent series resistance (ESR). The ESR impactsthe output voltage ripple and the overall efficiency of theconverter. Because of this, designers are moving to low ESRdesigns. Surface mount ceramic capacitors are becomingprevalent in systems that require high performance in asmall form factor. The use of multiple capacitors in parallelallows designers to achieve the necessary capacitance forthe system while greatly reducing the equivalent ESR.The high side MOSFET on time determines the dutycycle of the circuit, and is defined in Equation 1.D t ON,HSV OUTt ON,HS ) t OFF,HSV IN(eq. 1)If the duty cycle, D, is equal to 1 then the high sideMOSFET is on 100% of the time and the output voltageequals the input voltage. A duty cycle of 0.1 means that thehigh side MOSFET is on 10% of the time, producing anoutput voltage that is approximately 10% of the input voltage.Buck Converter Power LossThe buck converter power losses are influenced bymultiple factors, including the power MOSFETs, outputstage, controller / driver, feedback loop, and layout of theconverter itself. The duty cycle is less than 0.5 for most buckconverter designs, with a standard duty cycle of 0.1 to 0.2 inthe computing and server market. Design platforms aremoving to higher switching frequencies, providing theability to reduce converter size and form factors. At the sametime, converters must deliver greater performance and havehigher efficiency. The output stage performance greatlyimpacts the overall performance of the buck converter. Forthis reason, it is important to optimize the inductor andcapacitor selection for the specific application. The rest ofthis application note focuses on the output stage design.Basic LC DesignWhen designing the buck converter output stage, it isrecommended to begin with the inductor. The minimuminductance is calculated based on the target ripple current andother application circuit specifications. Once the inductor hasbeen selected, the minimum capacitance can be determined.Calculating Minimum InductanceLet’s begin with the basic inductor current / voltagerelationship, seen in Equation 2.VL L @The LC Output StagedI Ldt(eq. 2)Inductor current ripple is defined as the peak to peakchange in current during the converter on time. For thesynchronous buck converter, the change in inductor currentduring the high side MOSFET on time is equal to thechange during the high side MOSFET off time. In otherwords, the inductor current increase is equal to the inductorcurrent decrease (refer to Figure 2).The output stage of the synchronous buck converter iscomprised of an inductor and capacitor. The output stagestores and delivers energy to the load, and smoothes out theswitch node voltage to produce a constant output voltage.Inductor selection directly influences the amount ofcurrent ripple seen on the inductor current, as well as thecurrent capability of the buck converter itself. Inductorsvary from manufacturer to manufacturer in both materialand value, and typically have a tolerance of 20%.Inductors have an inherent DC resistance (known as theDCR) that impacts the performance of the output stage.Minimizing the DCR improves the overall performance ofthe converter. For applications that require a high loadcurrent, it is recommended to select an inductor with a lowDCR. The DCR is smaller for lower inductor values, butthere is a trade off between inductance and ripple current;the lower the inductance, the higher the ripple currentthrough the inductor. A minimum inductance must be met inorder to meet the ripple current requirements of the specificapplication circuit.The output capacitance directly affects the output voltageof the converter, the response time of the output feedbackloop, and the amount of output voltage overshoot that occursduring changes in load current. A ripple voltage exists on theDC output as the current through the inductor and capacitorincreases and decreases. Increasing the capacitance reducesthe amount of ripple voltage present. However, there is atradeoff between capacitance and the output response.Increasing the capacitance reduces the output voltage rippleDI L()) DI L(*)(eq. 3)For this reason, the inductor current ripple can simply bedefined as DIL and units are Amperes. The dIL/dt termduring the converter on time can be written as:dI LDI L tdtON,HS(eq. 4)Combining Equation 2 and Equation 4 and solving for theinductance yields Equation 5.L MIN V L(ON) @ t ON,HSDI L(eq. 5)In order to solve for inductance in terms of the applicationcircuit parameters, some additional terms must be defined first.During the converter on time, the high side MOSFET isconducting and the low side MOSFET is off. UsingKirkhoff’s voltage law, VL(ON) is defined asV L(ON) V IN * V HS * V OUT(eq. 6)where VHS is the voltage drop across the high side MOSFETand is defined as:V HS R DS(on)HS @ D @ I OUT,MAXhttp://onsemi.com2(eq. 7)
AND9135/DThe duty cycle is defined as the ratio of high sideMOSFET on time to the switching period of the converter.In other words,D t ON,HST SW t ON,HS @ f SWAs can be seen, there is a tradeoff between inductance andripple current. Lower target ripple current equates to higherminimum inductance. To optimize the output filterperformance it is recommended to target 20% 40%inductor ripple current, which translates to an LIR of 0.2 – 0.4.Calculating Maximum ESR and Minimum CapacitanceCapacitance is required to maintain a regulated outputvoltage while the high side MOSFET is off, and is necessaryto minimize the amount of ripple present on the outputvoltage. The output voltage ripple, DVPP, can be expressedas a peak to peak voltage or in terms of the CapacitorVoltage Ratio, or CVR.(eq. 8)And Equation 5 becomes:L MIN ǒV IN * VHS * VOUTǓ @ D(eq. 9)DI L @ f SWThe ripple current can also be expressed in terms of theinductor current ripple ratio, or LIR.DI L LIR @ I OUT,MAX(eq. 10)DV PP CVR @ V OUTSubstituting Equation 10 into Equation 9, the minimuminductance, LMIN, becomes:L MIN ǒV IN * VHS * VOUTǓ @ DLIR @ I OUT,MAX @ f SWA CVR of 0.05, for example, equates to an output ripplevoltage that is 5% of the DC output voltage.ESR and capacitance influence the response time of theoutput feedback loop. The larger the output capacitancevalue and ESR, the longer it takes for the output to respondto changes in load. ESR also influences the output voltageripple. The maximum ESR can be calculated using thespecified maximum voltage ripple, DVPP, and the maximumload current, as shown in Equation 23.(eq. 11)Equation 3 can be used to calculate the duty cycle, D usingDIL( ) and DIL( ) as defined in Equation 12 and 13 below.DI L()) DI L(*) V L ON,HSLV L OFF,HSL@ t ON,HS(eq. 12)@ t OFF,HS(eq. 13)ESR MAX where VL(ON) is defined in Equation 6 and VL(OFF) is:V L(OFF) V OUT ) V LSThe high side MOSFET tON and tOFF can also be writtenin terms of duty cycle.(eq. 15)t OFF,HS 1 * Df SW(eq. 16)Setting DIL( ) equal to DIL( ) and substituting Equations14, 15 and 16, the duty cycle becomes:D V OUT ) V LSV IN * V HS ) V LSCVR @ V OUTDV PP I OUT,MAXI OUT,MAX(eq. 23)Therefore, in order to have an output voltage ripple belowthe specified maximum, the ESR of the output capacitancemust be less than the value calculated using Equation 23.When the high side MOSFET is on, current through theinductor and capacitor is increasing, and the output voltageincreases. When the high side MOSFET is off, currentthrough the inductor and capacitor are decreasing, and theoutput voltage decreases. In order to achieve a constantoutput voltage, the amount of capacitor current increasemust be equal to the amount of capacitor current decrease.Therefore, the steady state current through the capacitor is0 A (Figure 3).(eq. 14)t ON,HS Df SW(eq. 22)(eq. 17)where VLS the voltage drop across the low side MOSFETwhen it is conducting, and is defined as:V LS R DS(on)LS @ (1 * D) @ I OUT,MAX(eq. 18)Therefore, the final inductance equation, LMIN, becomes:ǒL MIN ǓǒǓ(eq. 19)V IN * V HS * V OUTV OUT ) V LS@LIR @ I OUT,MAX @ f SWV IN * V HS ) V LSEquation 19 can be simplified by neglecting the high sideand low side MOSFET voltage drops, producing a minimuminductance ofL MIN (V IN * V OUT) @ DLIR @ I OUT,MAX @ f SW(eq. 20)where the duty cycle is estimated to beD V OUTV INFigure 3. Inductor and Capacitor Current(eq. 21)http://onsemi.com3
AND9135/DThe current through the capacitor is defined as:DV CIC C @Dt(eq. 24)Dt @ I C C @ DV C DQ C(eq. 25)Both Equations 31 and 34 must be taken intoconsideration when selecting the output capacitance. Thereis a tradeoff between the output voltage transient responseand output voltage ripple. These two must be balanced forthe needs of the specific application.and can be re written as:The area under the curve (shown in red in Figure 3) is thecapacitor charge, DQC, and is defined as:whereDQ C ǒ1Ǔ @ DI C @ Dt21ǒǓDt @ t ON ) ǒ1Ǔ @ t OFF221DǓ ) ǒ12Ǔ @ ǒ1f* DǓ ǒ Ǔ@ǒf212 @ f SW SWThis section walks through a design example applying theequations defined in the previous section. Table 1 lists thetarget application requirements for this example that must bemet by the converter design.(eq. 26)(eq. 27)Table 1. DESIGN EXAMPLE CIRCUIT REQUIREMENTSSWParameterǒ ǓǒǓDI LDI L1DQ C 1 @@ 28 @ f SW22 @ f SWDI L C MIN @ DV PP8 @ f SW(eq. 29)LIR @ I OUT,MAX8 @ f SW @ CVR @ V OUTǒǓDI L2(eq. 35)0.3Capacitor Voltage Ripple RatioCVR0.04Output Voltage Max OvershootVOV96 mVIOUT,MAX25 A1.2 V 0.112 V(eq. 36)(12 V * 1.2 V) @ 0.1 0.206 mH (eq. 37)0.3 @ 25 A @ (700 @ 10 3)Hz0.3 @ 25 A 28.75 A2(eq. 38)The saturation current of the inductor must be greater than28.75 A. A good rule of thumb is to select an inductor witha saturation current at least 20% higher than theapplication’s peak current.The minimum output capacitance is calculated usingEquations 31 and 34. The minimum capacitance needed tomeet the output voltage ripple ratio is:C MIN 0.3 @ 25 A 27.9 mF(eq. 39)8 @ (700 @ 10 3 Hz) @ (0.04 @ 1.2 V)The minimum output capacitance needed to achieve amaximum output voltage overshoot of 96 mV for theworst case load transient condition is:Solving for C, the equation becomes:I PEAK I OUT,MAX @LIRI PK 25 A )ǒǓwhere IPK is defined as:Inductor Current Ripple RatioTherefore, to obtain a ripple current that is less than 30%of the maximum output current, the inductor selected musthave an inductance value higher than 0.206 mH. Theinductor selected for this application must have a saturationcurrent that is higher than the peak current requirements ofthe application. For this example, IPK is2) 1 @ L@ I PK 2 1 @ C@ ǒV OV ) V OUTǓ22(eq. 34)700 kHzL MIN ǒǓL @ I PK 2(V OV ) V OUT) 2 * V OUT 21.2 VfSWNext, the minimum inductance is calculated usingEquation 20. For this example, LMIN is:(eq. 31)The total energy prior to the load transition must be equalto the total energy after the load transition. Therefore, (eq. 33)C MIN VOUTD E TOT E C ) E L 1 @ C @ V C 2 ) 1 @ L @ I L 2 (eq. 32)22ǒǓ12 VFirst, the duty cycle can be estimated, using Equation 21.For this example, the duty cycle is:The above equation only considers the affect of outputripple voltage and inductor ripple current on the outputcapacitance. The transient load response capability of theoutput stage must also be considered. The synchronous buckconverter must be able to respond to changes in load currentwhile maintaining a regulated output voltage. When the loadcurrent changes from a higher value to a lower value, theoutput voltage will temporarily increase until the converteris able to adjust the duty cycle to return the output voltageto its regulated value. This temporary output voltageincrease is known as output voltage overshoot, VOV. Theworst case overshoot will occur when the load transitionsfrom maximum load to no load. The output capacitor mustbe able to handle this transient condition.The total energy of the output stage is defined as:2VINSwitching FrequencyMaximum Output Current(eq. 30)The minimum output capacitance due to the outputripplve voltage can be derived by combining Equations 10,22 and 30 and solving for capacitance.ǒ12Ǔ@ C@ VOUTTargetOutput Voltage(eq. 28)And Equation 25 becomes:C MIN SymbolInput VoltageDIDI C L2andTherefore, Equation 26 can be re written as:ǒǓLC Design Examplehttp://onsemi.com4C MIN L @ I PK 2(V OV ) V OUT) 2 * V OUT 2C MIN 0.206 mH @ (28.75 A) 2 709.6 mF(0.096 V ) 1.2 V) 2 * (1.2 V) 2(eq. 40)
AND9135/DA good rule of thumb when selecting capacitance is tochoose an out capacitor value that is at least 20% higher thanthe minimum calculated capacitance, to account forcapacitor tolerance.Table 4 lists the output filter parameters tested in theopen loop configurations. All waveforms were measured ata load current of 25 A.Table 4. LC VALUES FOR OPEN LOOP EXPERIMENTSLC ExperimentsThe buck converter output filter design affects the outputcurrent ripple, output voltage ripple, output voltageovershoot, and the transient response of the feedback loop.Component selection also impacts the efficiency of theconverter. Open loop and closed loop experiments werecarried out to examine the effect of capacitance andinductance on the converter’s performance.Three inductors were selected for the experiments in orderto examine the impact of inductance value and DCR oncircuit performance. Two inductors with equivalent DCRbut different inductance were selected to examine the impactof inductance value on circuit performance. They differed incore size and inductance, but were made from the samematerial and by the same manufacturer. A third inductor wasselected to examine the impact of the DCR on circuitperformance. It was selected from the same manufacturer,but differed in core material.TestL Value (mH)12L DCR (mW)C Value (mH)0.30116000.820.93200Table 2. INDUCTORS USED IN EXPERIMENTSL (uH)DCRISAT (A)Core Size (mm)Figure 4. Ripple Current for 0.3 mH Inductor0.301.03510 x 100.820.93513 x 130.300.2932.59.6 x 6.4Figure 4 shows the ripple current for the 0.30 mH /1600 mF output filter. As can be seen, the measured outputripple current was 6 A.Table 2 lists the inductance, DCR, saturation current andcore size for the three surface mount inductors used in theexperiments.LC Filter Impact on Ripple Current and Ripple VoltageA buck converter was tested under the conditions listed inTable 3, in an open loop configuration, using a 5 VMOSFET driver. A signal generator was used to create thePWM pulse. The inductor current was measured using acurrent probe.Table 3. TEST CONDITIONS FOR EXPERIMENTSParameterSymbolValueVIN12 VVOUT1.2 VfSW700 kHzDrive VoltageVDRIVE5VLoad CurrentILOAD0 – 25 ALIR MaximumDIL0.3CVR MaximumDVPP0.04Input VoltageOutput VoltageSwitching FrequencyFigure 5. Ripple Current for 0.82 mH InductorFigure 5 shows the ripple current for the 0.82 mH /3200 mF output filter. At a 25 A load, the measured ripplecurrent was 2.5 A. According to the parameters specified inTable 3, the ripple current could not exceed 30% of themaximum load current (7 A). For both cases, thisrequirement was met. As can be seen from the experiment,using a higher inductance value reduced the measured ripplecurrent.http://onsemi.com5
AND9135/DTable 6. TEST CONDITIONS (Efficiency Experiments)ParameterInput VoltageOutput VoltageSwitching FrequencySymbolValueVIN12 VVOUT1.2 VfSW700 kHzDrive VoltageVDRIVE5VLoad CurrentILOAD1 – 25 AFirst, the effect of output capacitance was examined. A0.3 mH inductor with a 1 mW DCR was used for both tests.The output capacitances used were 1600 mF and 3200 mF. Ascan be seen in Figure 8, increasing the output capacitanceslightly lowered the circuit’s efficiency. In this example,doubling the output capacitance had minimal effect on theefficiency performance.Figure 6. Ripple Voltage for 1600 mF CapacitanceFigure 6 and 7 show the output ripple voltage measuredfor 1600 mF and 3200 mF capacitance respectively.As can be seen, the output ripple voltage is less for the3200 mF capacitance.Figure 8. Effect of Capacitance on EfficiencyNext, the effect of inductor DCR was examined. Two0.3 mH inductors, one with 1 mW and the other with0.29 mW, were paired with 1600 mF output capacitance. Ascan be seen in Figure 9, DCR has a significant effect on thecircuit performance, producing a 1.7% efficiencyimprovement at maximum load by using the inductor with0.29 mW DCR.Figure 7. Ripple Voltage for 3200 mF CapacitanceThe specified maximum ripple voltage requirement was4% (48 mV). For both 1600 mF and 3200 mF capacitances,the ripple voltage limit was not exceeded.LC Filter Impact on EfficiencyNext, closed loop experiments were run to see the effectof the output filter on efficiency. Table 5 lists the inductorand capacitor combinations used in the experiments.Table 5. LC VALUES FOR EFFICIENCY EXPERIMENTSTestL Value (mH)L DCR (mW)C Value (mF)10.301160020.301320030.300.291600Each experiment was run under the conditions listed inTable 6. The efficiency of the test circuit was then comparedbetween tests to see the effects of output filter on circuitperformance.Figure 9. Effect of Inductor DCR on Efficiencyhttp://onsemi.com6
AND9135/Ddesigning for the specific application criteria that it will beoperating in.From the experiment results, it was found that the inductorvalue played a significant role in the output ripple current,as well as in the converter’s efficiency performance. The0.82 mH inductor ripple current was a third of the 0.3 mHinductor ripple current. Similarly, the output voltage rippleimproved with a higher output capacitance.The efficiency of the converter was greatly impacted bythe DCR of the inductor. Holding the output capacitance andoutput inductance constant, the 0.29 mW DCR provided1.7% higher efficiency at maximum load compared with the1 mW DCR.There is a tradeoff between inductance and saturationcurrent for inductors. Therefore, to meet or exceed a ripplecurrent requirement, the inductance must be greater than theminimum calculated inductance, and the saturation currentof the inductor must be greater than the peak current of theconverter at maximum load.Capacitance also plays a significant role in theperformance of the synchronous buck converter. Outputcapacitance directly influences the amount of voltage rippleand voltage overshoot seen on the output. Experimentsshowed that the capacitance had minimal effect on theefficiency performance.Inductance and DCR both affect the converter’sefficiency. Figure 10 shows the efficiency results of fourdifferent inductors. At light load, the efficiency correlates toinductance value; the higher the inductance, the higher thelight load efficiency. As the load current increases, the DCRbegins to dominate. At heavy loads, the efficiency correlatesto the DCR value; the 0.29 mW DCR produced the highestefficiency, and the 1.56 mW DCR produced the lowestefficiency.Figure 10. Effect of Inductance on EfficiencyAs can be seen from the experiment, the efficiency wasmost impacted by the output inductor selection. Both theinductor value and DCR significantly affected the efficiencyof the converter.References1. “Buck Converter Design Demystified.” Articlefrom Power Electronics Technology. June 2006.www.powerelectronics.com.2. “Understanding the Output Current Capability ofDC DC Buck Converters”. Application note #AND8117/D. ON Semiconductor.3. “Basic Calculation of a Buck Converter’s PowerStage.” Application note # SLVA477A. TexasInstruments.4. “Selecting Inductors for Buck Converters.”Application note # AN 1197. NationalSemiconductor. Sanjaya ManiktalaConclusionThe output stage of the synchronous buck converter playsa significant role in the performance of the converter. Inorder to meet the target ripple current, output ripple voltage,and output voltage overshoot, a minimum inductance andcapacitance must be exceeded. Additional factors must alsobe considered when selecting an inductor and capacitor fora specific application. The output stage can be optimized byON Semiconductor andare registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent Marking.pdf. SCILLCreserves the right to make changes without further notice to any products herein. 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Buck Converter Power Loss The buck converter power losses are influenced by multiple factors, including the power MOSFETs, output stage, controller / driver, feedback loop, and layout of the converter itself. The duty cycle is less than 0.5 for most buck converter designs, with a standard dut
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