Introduction To The PCI Interface
Introduction to the PCI InterfaceIntroduction to the PCI InterfaceKarumanchi Narasimha NaiduInstructor:Prof. Girish P. SaraphIIT BombayMay 18, 2005Karumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceOutlineOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceOutlineOutlineMotivationBUS standardsPCI Technology OverviewPCI Local BusPCI protocolSpecial CasesElectrical and Mechanical SpecificationsOther TopicsReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceMotivationOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceMotivationInside a ComputerWhat is a BUS?Components - Processor, Memory etcPeripheralsInterconnectionMotivationData flowSpeedKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceMotivationLocal BusA set of parallel conductors, which allow devices attached to itto communicate with the CPU.The bus consists of three main parts:Control lines, Address lines , Data linesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceBus StandardsOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceBus StandardsBus ProtocolsRequirements of a BUS standardElectrical, Mechanical requirementsProtocol requirementsCommon BUS standardsISA and EISAMCA (Micro Channel Bus)VESA Local BUS (Video Electronic Standard Associations) :1-2 devices can be connected.PCI Local BUSKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceBus StandardsISA (Industry Std Arch.)Has a clock speed limit of 8 MHzHas a word length of 8 or 16 bits (8 or 16 data lines)Requires two clock ticks to transfer data (16 bit-transfers)Very slow for high performance disk accesses and highperformance video cardsKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceBus StandardsEISA (Enhanced Std Arch)Has a clock speed of 8.33 MHzMaximum of a 32-bit wide word length(32 data lines)Can support lots of devicesSupports older devices which have Slower or Smaller wordlengths(ISA)Transfers data every clock tick.Karumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceBus StandardsMCA (Micro-channel Bus)Has a clock speed of 10 MHzHas a 32 bit word length (32 data lines)Transfers data every clock tick.Karumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceBus StandardsVESA (Video Electronic Std Arch.)Has a clock speed limit of 33 MHz.Limited to a 32-Bit wide word length (32 data lines).Cannot take advantage of the Pentium’s 64 bit architecture.Limited support for Burst Transfers, thereby limiting theachievable throughputRestricted on the number of devices which can be connected (1 or 2 devices).Karumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Technology OverviewOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Technology OverviewPCI General Block DiagramKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Technology OverviewPCI - technology InformationPCI: Peripheral Component InterconnectConventional PCIPCI-X1.02.0PCI ExpressOtherKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Technology OverviewPCI-SIGPCI Special Interest GroupIndustry organization formed in 1992Over 900 membersPromotes PCI as an industry-wide standardFull ownership and management of the PCI specificationsMaintains the PCI specifications and forward-compatibility ofall PCI revisionsKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Technology OverviewPCI TechnologyConventional PCIInitial PCI 1.0 proposal by Intel in 1991Introduced by PCI-SIG as PCI 2.0 in 1993Version 2.1 approved in 1995Recent version 2.3 approved in March 2002PCI-XVersion 1.0 approved in September 1999Version 2.0 approved in July 2002PCI ExpressFormerly known as 3GIOVersion 1.0 approved in July 2002Karumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Technology OverviewConventional PCIPlug-and-Play FunctionalityStandard PCI is 32 bit and operates at 33 MHzThroughput 133 MB/secPCI 2.1 introducedUniversal PCI cards supporting both 3.3V and 5V64 Bit slots and 66 MHz capability32-Bit throughput @ 66 MHz: 266 MB/sec64-Bit throughput @ 66 MHz: 532 MB/secPCI 2.3 system no longer supports 5V-only adapters3.3V and Universal PCI products are still fully supportedKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Technology OverviewPCI-X 1.0Based on existing PCI architecture64-Bit slots with support for 3.3V and Universal PCINo support for 5V-only boards!Fully backwards-compatibleConventional 33/66 MHz PCI adapters can be used in PCI-XslotsPCI-X adapters can be used in conventional PCI slotsProvides two speed grades: 66 MHz and 133 MHzThe slowest board dictates the maximum speed on a particularbus !Targeted at high-end data networking and storage networkapplicationsKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Technology OverviewPCI-X 2.0Based on PCI-X 1.0Still fully backwards-compatibleIntroduces ECC (Error Correction Codes mechanism toimprove robustness and data integrityProvides two additional speed gradesPCI-X 266: 266 MHz (2.13 GB/sec)PCI-X 533: 533 MHz (4.26 GB/sec)Bandwidth sufficient to support new breed of cutting-edgetechnologies10 Gigabit Ethernet / Fiber Channel4X/12X infiniBandKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Technology OverviewPCI-X Speed LimitationsPCI-X supports point-to-point and multi-drop loadsHighest speed grades are supported exclusively withpoint-to-point loadsPCI-X 133PCI-X 266PCI-X 533Two PCI-X 133 loads operate at 100 MHzFour loads operate at a maximum of 66 MHzOEMs can build connector-less systems with multiple loadsutilizing high speed gradesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Technology OverviewPCI ExpressHigh-speed point-to-point architecture that is essentially aserialized, packetized version of PCIGeneral purpose serial I/O bus for chip-to-chipcommunication, USB 2.0 / IEEE 1349b interconnects, andhigh-end graphicsviable AGP replacementBandwidth 4 Gigabit/second full duplex per laneUp to 32 separate lanes 128 Gigabit/secondSoftware-compatible with PCI device driver modelExpected to coexist with and not displace technologies likePCI-X in the foreseeable futureKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI Local BusBus Width: 32 or 64 bitsOperating frequency: 0-66 MHzCan support many more devices then VESA64 bit extension for Pentium proc.Greater Variety of Expansion cards available.Multiplexed Address and DataPCI SIG (Special Interest Group)Karumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI Local Bus Revisions1.0 - 1992.2.0 - connector and expansion board specification2.1 - 66MHz operation2.2 - protocol, electrical and mechanical specsKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusOverview of Speeds of busesBus TypeISAEISAVL-busVI-busPCIPCIPCIPCIBus Width16 bits32 bits32 bits32 bits32 bits64 bits64 bits64 bitsKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceBus Speed8 MHz8 MHz25 MHz33 MHz33 MHz33 MHz66 MHz133 MHzMB/sec16 MBps32 MBps100 MBps132 MBps132 MBps264 MBps512 MBps1 GBpsIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI Local Bus FeaturesPerformance Burst Transfer at 528 m bps peak (64 bit- 66 MHz)Fully concurrent with Processor-Memory subsystemAccess time is as fast as 60ns.Hidden central arbitration.Low cost- multiplexedLow Pin count- 47 pin for target; 49 pin as initiator.Ease of Use- full auto configurationFlexibility- processor independent, accommodates otherprotocolsGreen Machine ‘CMOS drivers low powerKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI devices and PCI coresEvery device on the PCI bus is eitherPCI compliant -has the same signals as the PCI busConnected via a PCI core- this piece of hardware does theinterfacingCommon devicesAudio/Video cardsLAN cardsSCSI controllersKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI Core - 9656BAKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI Interface SignalsKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI System SignalsCLK : clean signal derived from the clock generator (33MHz ,66MHz)RST : Active Low Asynchronous resetPAR : Parity Signal to ensure the parity across the AD busand C/BE.Karumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI Bus Protocol - Signal DefinitionAD- Multiplexed address and data linesC/BE - Command and Byte EnablesFRAME - Master indicating start/end of transferIRDY - Master (initiator) readyTRDY - Target readyDEVSEL - Target device selectedREQ - Request for busGNT - Bus GrantKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI control signals contd.STOP [I/0]: Target asserts to stop the transaction inProgress.IDSEL [I]: Used as chip selectLOCK [I/0] : During semaphore currentlyaccessed target locked by initiatorDEVSEL [I/0] :Asserted by target when the target asserts hasdecoded its address. (if by 6 clk not asserted ¿ master abort.Karumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI Configuration RegisterDevice IDVendor IDStatus / Command regBase Address [0,1,2,3,4,5]Maximum LatencyMinimum GNTSubsystem ID, Subsystem Vendor IDKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI Command Types [C/BE]0000 INTR ack0010 I/O Read0011 I/O Write0110 Memory Read0111 Memory Write1010 Configuration read1011 Configuration writeKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusJTAG boundary scanTest Access PortTestTestTestTestTestClockData inData outMode selectResetIEEE standard 1149.1 compliantKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusInterruptsAsynchronous events4 interrupt lines for multi-functional devices.Interrupt lines goes to the interrupt controller to execute theISRKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusPCI Bus Protocol-Transfer mechanismConfiguration read/writeIO read/writeBurstBasic form of data transferIncludes one address phaseOne or more data phaseKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusBurst Transfer MechanismAssert REQGNT grantedWait for current transaction to endAssert FRAMETransfer data when both TRDY and IRDY are assertedDe-assert FRAME during last data phaseKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusTiming Diagram for a basic Read operationKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusVarious read transactionSingle cycle ReadBurst data readRead with no wait statesByte Enables can be changed for every data cycleData Cycle with NO byte enables.Karumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusBasic Write OperationKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusTransaction terminationLast data phase completes when!FRAME and TRDY (normal - master)!FRAME and STOP (target termination)!FRAME and Device Select Timer expires (Master abort)!DEVSEL and STOP (Target abort)Karumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfacePCI Local BusMultiple busPCI to PCI bridgeConcept of LOCKAll on one levelKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceReferencesOutline1Outline2Motivation3Bus Standards4PCI Technology Overview5PCI Local Bus6ReferencesKarumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
Introduction to the PCI InterfaceReferencesReferencesPCI System Architecture Tom Shanley and Don rumanchi Narasimha Naidu Instructor: Prof. Girish P. SaraphIntroduction to the PCI InterfaceIIT Bombay
PCI Express Formerly known as 3GIO . PCI 2.3 system no longer supports 5V-only adapters . Introduction to the PCI Interface. Introduction to the PCI Interface PCI Technology Overview PCI-X 1.0 Based on existing
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