LESSON PLAN - LBRCE
CSE/LP/7/18.07.02LESSON PLANDate: 25.07.13Sub Name : DIGITAL LOGIC DESIGN LABBranch: CSETo 09.11.13Semester:IIICS351: DIGITAL LOGIC DESIGN LABLecture: 3 Periods/weekInternal Marks: 25TutorialExternal Marks: 75Credits: 2External Examination: 3 -------------CYCLE 11.a) Basic Gates Function Verification using truth tables.i) AND Gate using 7408 ICii) OR Gate using 7432 ICiii) NOT Gate using 7404 ICb) Universal Gates Functional Verificationi) NAND Gate using 7400 ICii) NOR Gate using 7402 ICc) Special Gates Functional verificationi) XOR Gate using 7486 ICii) XNOR Gate using XOR followed by NOT Gate2. Realization of following gates using universal gates and its functional verification.AND, OR, XOR, NOT3. a) Design Half-adder and Full-adder circuits and verify its functionality.b) Verify the functionality of four bit ripple carry adder for signed and unsigned integers withthe verification of overflow condition.4. Design a four bit comparator and verify its functionality(using logic gates or IC’s)5. Design a BCD to Excess-3 code converter and verify its functionality by using gates.6. Design a BCD to Gray code converter and verify its functionality by using gates.7. Design and verify the functionality of Decoders and multiplexers of different inputs.CYCLE 28. Verify the functionality of following Flip-Flops.a) SR Flip-Flopb) JK Flip-Flopc) D Flip-Flopd) T Flip-Flop9. a) Design a UP-Counter using JK/T Flip-Flop.b) Design a MOD-3 Counter.10. Design a DOWN-Counter using JK/T Flip-Flop.11. Design a Bi-directional Counter using JK/T Flip-Flop.12. Design a Synchronous Counter for 100-110-111-011-001
CSE/LP/7/18.07.02LAB PLANDate: 25.07.13Sub Name : DIGITAL LOGIC DESIGN LABBranch: CSE (sec-A)To 09.11.13Semester:IIICOURSE OBJECTIVE:The course will provide the student with a firm foundation of the principles of digitaldesign by building a working knowledge of digital electronics and its applications. By the end ofthe semester, the student shall have acquired the basic skill in using the digital design kit; Use of prototyping board. Use of basic gates, decoders and multiplexers. Use of PLDs Use of flip-flops, counters and shift registers. Use of logic probe.COURSE OUTCOMES:A student who successfully fulfills the course requirements will have demonstrated:1. An ability to operate laboratory equipment.2. An ability to construct, analyzes, and troubleshoots simple combinational and sequentialcircuits.3. An ability to design and troubleshoot a simple state machine.4. An ability to measure and record the experimental data, analyze the results, and prepare aformal laboratory report.
CSE/LP/7/18.07.02LAB PLANDate: 25.07.13Sub Name : DIGITAL LOGIC DESIGN LABTo 09.11.13Branch: CSE (sec-A)Semester:IIILesson Plan For CSE(SEC-A)CYCLE-ISessionNoTopics to be coveredDate12Introduction to logisim softwareBasic gates verification29-07-201305-08-20133Realization of AND, OR, NOT, XORgatesHalf adder, Full adder, Half subtractorFull subtractor, Ripple carry adderFour bit comparatorBCD to Excess-3 code converterBCD to Gray code converterDecoders, MultiplexerFlip-flopsUP counterMod-3 counterDown counterBidirectional counterDown counterInternal BBBBBBBBBBBRemarks
CSE/LP/7/18.07.02LESSON PLANDate: 25.07.13Sub Name : DIGITAL LOGIC DESIGN LABBranch: CSETo 09.11.13Semester:IIICS351: DIGITAL LOGIC DESIGN LABLecture: 3 Periods/weekInternal Marks: 25TutorialExternal Marks: 75Credits: 2External Examination: 3 -------------CYCLE 11.a) Basic Gates Function Verification using truth tables.i) AND Gate using 7408 ICii) OR Gate using 7432 ICiii) NOT Gate using 7404 ICb) Universal Gates Functional Verificationi) NAND Gate using 7400 ICii) NOR Gate using 7402 ICc) Special Gates Functional verificationi) XOR Gate using 7486 ICii) XNOR Gate using XOR followed by NOT Gate2. Realization of following gates using universal gates and its functional verification.AND, OR, XOR, NOT3. a) Design Half-adder and Full-adder circuits and verify its functionality.b) Verify the functionality of four bit ripple carry adder for signed and unsigned integers withthe verification of overflow condition.4. Design a four bit comparator and verify its functionality(using logic gates or IC’s)5. Design a BCD to Excess-3 code converter and verify its functionality by using gates.6. Design a BCD to Gray code converter and verify its functionality by using gates.7. Design and verify the functionality of Decoders and multiplexers of different inputs.CYCLE 28. Verify the functionality of following Flip-Flops.a) SR Flip-Flopb) JK Flip-Flopc) D Flip-Flopd) T Flip-Flop9. a) Design a UP-Counter using JK/T Flip-Flop.b) Design a MOD-3 Counter.10. Design a DOWN-Counter using JK/T Flip-Flop.11. Design a Bi-directional Counter using JK/T Flip-Flop.12. Design a Synchronous Counter for 100-110-111-011-001
CSE/LP/7/18.07.02LAB PLANDate: 25.07.13Sub Name : DIGITAL LOGIC DESIGN LABBranch: CSE (sec-A)To 09.11.13Semester:IIICOURSE OBJECTIVE:The course will provide the student with a firm foundation of the principles of digitaldesign by building a working knowledge of digital electronics and its applications. By the end ofthe semester, the student shall have acquired the basic skill in using the digital design kit; Use of prototyping board. Use of basic gates, decoders and multiplexers. Use of PLDs Use of flip-flops, counters and shift registers. Use of logic probe.COURSE OUTCOMES:A student who successfully fulfills the course requirements will have demonstrated:1. An ability to operate laboratory equipment.2. An ability to construct, analyzes, and troubleshoots simple combinational and sequentialcircuits.3. An ability to design and troubleshoot a simple state machine.4. An ability to measure and record the experimental data, analyze the results, and prepare aformal laboratory report.
CSE/LP/7/18.07.02LAB PLANDate: 25.07.13Sub Name : DIGITAL LOGIC DESIGN LABTo 09.11.13Branch: CSE (sec-A)Semester:IIILesson Plan For CSE(SEC-A)CYCLE-ISessionNoTopics to be coveredDate12Introduction to logisim softwareBasic gates verification26-07-201302-08-20133Realization of AND, OR, NOT, XORgatesHalf adder, Full adder, Half subtractorFull subtractor, Ripple carry adderFour bit comparatorBCD to Excess-3 code converterBCD to Gray code converterDecoders, MultiplexerFlip-flopsUP counterMod-3 counterDown counterBidirectional counterDown counterInternal BBBBBBBBBBBRemarks
LESSON PLANDate:25.07.2013To 09.11.2013Sub Name : Digital Logic DesignBranch: B.Tech CSESemester& Section:II SEM –A SECUNIT - IBinary Systems: Digital Computers and Digital Systems, Binary Numbers, Number baseConversion, Octal and Hexadecimal Numbers, Complements, Binary Codes, Binary Storage andRegisters, Binary Logic, Integrated Circuits. Boolean Algebra And Logic Gates: BasicDefinitions, Axiomatic definition of Boolean Algebra, Basic theorems and Properties of BooleanAlgebra, Boolean functions, Canonical and Standard Forms, Other operations, Digital LogicGates.UNIT - IISimplification Of Boolean Expressions: Formulation of simplification problem, PrimeImplicants and irredundant disjunctive and conjunctive expression, Karnaugh Maps, MinimalExpressions for complete and incomplete Boolean functions. Five and Six Variable K-Maps,Quine-McCluskey Method, Prime Implicants and Implicate tables and irredundant expressions,and Table reductions.UNIT - IIICombinational Logic: Design Procedure, Adders, Subtractors, Code Conversion, AnalysisProcedure, multilevel NAND and NOR circuits. Combinational Logic with MSI And LSI:Binary Parallel Adder, Decimal Adder, Magnitude Comparator, Decoders, Multiplexers.UNIT - IVSequential Logic: Flip Flops, Triggering of Flip-Flops, Analysis of Clocked Sequential Circuits,State Reduction and Assignment, Flip-Flop Excitation tables, Design Procedure, Design ofCounters, Design with state equations Registers, Counters and Memory : Registers. Shiftregisters, Ripple Counters, Synchronous Counters, Timing sequences, the memory unit.UNIT - VProgrammable Logic: Read – Only Memory (ROM), PROM, Programmable Logic Device(PLD), Programmable Logic Array (PLA), Programmable Array Logic (PAL).
LESSON PLANDate:25.07.2013To 09.11.2013Sub Name : Digital Logic DesignBranch: B.Tech CSESemester& Section:II SEM –A SECCourse Description & Objectives:This course concerns the design of digital systems using integrated circuits. The mainemphasis is on the theoretical concepts and systematic synthesis techniques that can be applied tothe design of practical digital systems.Course Objectives:The objective of the course is to explain how digital circuit of large complexity can bebuilt in a methodological way, starting from Boolean logic and applying a set of rigoroustechniques. Numerous examples and case studies will be used to illustrate how the conceptspresented in the lectures are applied in practice, and how the need to accommodate differentpractically-motivated trade-offs can lead to alternative implementations. The students will applytheir knowledge in the labs by building increasingly more complex digital logic circuits.Course Outlines: First unit deals with the digital systems and various binary number systems. It deals withvarious methods for the conversion of numbers in one system to another. It coversvarious types of codes which includes codes for error correction and detection. Itintroduces the theory of Boolean algebra.Second unit introduces K-map method which is a straight forward graphical method forsimplification and quine-Mcclusky method is explained.Third unit explains the principles of various combinational logic circuits. These Includeadders, subtractors, multiplexer, demultiplexers, decoders, encoders and comparators.Fourth unit explains the basic theory behind various flip-flops. It also explain the designprocedure for various asynchronous counters, synchronous counters and sequencegenerators. It also explain the registers and memory unit.Fifth unit deals with the various types of memories like ROM, PROM, PLA and PAL’s.Student Learning Outcomes:1.2.3.4.5.6.Upon the successful completion of this course students will be able to:Solve basic binary math operations using the logic gates.Demonstrate programming proficiency using the various logical elements to designpractically motivated logical units.Design different units that are elements of typical computer’s CPU.Apply knowledge of the logic design course to solve problems of designing of controlunits of different input/output devices.Wiring different logical elements, to analyze and demonstrate timing diagrams of theunits modeled.Design electrical circuitry using logical elements realized on the base of differenttechnologies.
Date:LESSON PLAN25.07.2013To 09.11.2013Sub Name : Digital Logic DesignBranch: B.Tech r& Section:Topics to be coveredIntroduction to Digital SystemsDigital Systems, BinaryNumbersNumber base ConversionNumber base ConversionOctal and Hexadecimal NumbersComplementsBinary CodesBinary CodesBinary Storage and Registers,Binary LogicIntegrated CircuitsTutorialIntroduction to Boolean algebra,Basic Definitions, Axiomaticdefinition of Boolean AlgebraBasic theorems and Properties ofBoolean AlgebraBoolean functionsCanonical and Standard FormsCanonical and Standard FormsOther operations, Digital LogicGatesSlip test on UNIT-1Simplification Of BooleanExpressionsIntroduction to Karnaugh MapsOne Variable, Two variable,Three Variable mapsFour Variable MapTutorialFive Variable K-Map andExamplesSix Variable K-Maps ExamplesMinimal Expressions forincomplete Boolean functionsQuine-McCluskey MethodPrime implicants and EssentialPrime ImplicantsPertickson Method forirredundant expressionSlip Test on UNIT-2DateII SEM –A 13BB3-9-13BB4-9-135-9-13BBBBRemarks
Date:LESSON PLAN25.07.2013To 09.11.2013Sub Name : Digital Logic DesignBranch: B.Tech emester& Section:Introduction to CombinationalLogic, Design Procedure,Analysis ProcedureAddersSubtractorsCode ConversionMultilevel NAND circuitsMultilevel NOR circuitsTutorialIntoduction to CombinationalLogic with MSI And LSIBinary Parallel Adder, DecimalAdderDecimal AdderMagnitude ComparatorDecodersMultiplexersTutorialSlip test on UNIT-3Introduction to Sequential Logic,Flip FlopsTriggering of Flip-Flops,Analysis of Clocked SequentialCircuitsState Reduction and AssignmentFlip-Flop Excitation tablesDesign ProcedureDesign of CountersIntroduction to Registers, ShiftregistersRipple CountersSynchronous CountersTiming sequencesthe memory unitTutorialSlip test on Unit-4Read – Only Memory (ROM)Programmable Read OnlymemoryProgrammable Logic Device(PLD)II SEM –A SECBB7-9-13I MIDEXAMINATIONS (0309-2012 10-1323-10-1324-10-13BBBBBBBBBBBBBBBBBB
Date:LESSON PLAN25.07.2013To 09.11.2013Sub Name : Digital Logic DesignBranch: B.Tech CSE63.64.Semester& Section:Programmable Logic ArrayProgrammable Array Logic(PAL).TutorialSlip Test on tent beyond syllabus/ToolsContent beyond syllabus/ResearchpapersContent beyond syllabus/NewapplicationsContent beyond syllabus/R & DPracticePractice69.II SEM –A 6-11-137-11-139-9-13BBBBBBTEXT BOOKS :M.Morris Mano, ‘Digital Logic and Computer Design’, PHI.REFERENCES :1.M.Morris Mano, ‘Computer Engineering Hardware Design’, PHI2.Donald e Givone, Digital principles and Design, TMH (Unit II and V)Course Delivery Plan:WeekUnits1234511112Prepared bySignatureNameG. Naga LakshmiDesignation Asst. Professor6272839310113 4 4121314455 R RApproved byHOD/CSEProfessor1516R
LESSON PLANDate:25.07.2013To 09.11.2013Sub Name : Digital Logic DesignBranch: B.Tech CSESemester& Section:II SEM –B SECUNIT - IBinary Systems: Digital Computers and Digital Systems, Binary Numbers, Number baseConversion, Octal and Hexadecimal Numbers, Complements, Binary Codes, Binary Storage andRegisters, Binary Logic, Integrated Circuits. Boolean Algebra And Logic Gates: BasicDefinitions, Axiomatic definition of Boolean Algebra, Basic theorems and Properties of BooleanAlgebra, Boolean functions, Canonical and Standard Forms, Other operations, Digital LogicGates.UNIT - IISimplification Of Boolean Expressions: Formulation of simplification problem, PrimeImplicants and irredundant disjunctive and conjunctive expression, Karnaugh Maps, MinimalExpressions for complete and incomplete Boolean functions. Five and Six Variable K-Maps,Quine-McCluskey Method, Prime Implicants and Implicate tables and irredundant expressions,and Table reductions.UNIT - IIICombinational Logic: Design Procedure, Adders, Subtractors, Code Conversion, AnalysisProcedure, multilevel NAND and NOR circuits. Combinational Logic with MSI And LSI:Binary Parallel Adder, Decimal Adder, Magnitude Comparator, Decoders, Multiplexers.UNIT - IVSequential Logic: Flip Flops, Triggering of Flip-Flops, Analysis of Clocked Sequential Circuits,State Reduction and Assignment, Flip-Flop Excitation tables, Design Procedure, Design ofCounters, Design with state equations Registers, Counters and Memory : Registers. Shiftregisters, Ripple Counters, Synchronous Counters, Timing sequences, the memory unit.UNIT - VProgrammable Logic: Read – Only Memory (ROM), PROM, Programmable Logic Device(PLD), Programmable Logic Array (PLA), Programmable Array Logic (PAL).
LESSON PLANDate:25.07.2013To 09.11.2013Sub Name : Digital Logic DesignBranch: B.Tech CSESemester& Section:II SEM –B SECCourse Description & Objectives:This course concerns the design of digital systems using integrated circuits. The mainemphasis is on the theoretical concepts and systematic synthesis techniques that can be applied tothe design of practical digital systems.Course Objectives:The objective of the course is to explain how digital circuit of large complexity can bebuilt in a methodological way, starting from Boolean logic and applying a set of rigoroustechniques. Numerous examples and case studies will be used to illustrate how the conceptspresented in the lectures are applied in practice, and how the need to accommodate differentpractically-motivated trade-offs can lead to alternative implementations. The students will applytheir knowledge in the labs by building increasingly more complex digital logic circuits.Course Outlines: First unit deals with the digital systems and various binary number systems. It deals withvarious methods for the conversion of numbers in one system to another. It coversvarious types of codes which includes codes for error correction and detection. Itintroduces the theory of Boolean algebra.Second unit introduces K-map method which is a straight forward graphical method forsimplification and quine-Mcclusky method is explained.Third unit explains the principles of various combinational logic circuits. These Includeadders, subtractors, multiplexer, demultiplexers, decoders, encoders and comparators.Fourth unit explains the basic theory behind various flip-flops. It also explain the designprocedure for various asynchronous counters, synchronous counters and sequencegenerators. It also explain the registers and memory unit.Fifth unit deals with the various types of memories like ROM, PROM, PLA and PAL’s.Student Learning Outcomes:1.2.3.4.5.6.Upon the successful completion of this course students will be able to:Solve basic binary math operations using the logic gates.Demonstrate programming proficiency using the various logical elements to designpractically motivated logical units.Design different units that are elements of typical computer’s CPU.Apply knowledge of the logic design course to solve problems of designing of controlunits of different input/output devices.Wiring different logical elements, to analyze and demonstrate timing diagrams of theunits modeled.Design electrical circuitry using logical elements realized on the base of differenttechnologies.
Date:LESSON PLAN25.07.2013To 09.11.2013Sub Name : Digital Logic DesignBranch: B.Tech r& Section:Topics to be coveredIntroduction to Digital SystemsDigital Systems, BinaryNumbersNumber base ConversionNumber base ConversionOctal and Hexadecimal NumbersComplementsBinary CodesBinary CodesBinary Storage and Registers,Binary LogicIntegrated CircuitsTutorialIntroduction to Boolean algebra,Basic Definitions, Axiomaticdefinition of Boolean AlgebraBasic theorems and Properties ofBoolean AlgebraBoolean functionsCanonical and Standard FormsCanonical and Standard FormsOther operations, Digital LogicGatesSlip test on UNIT-1Simplification Of BooleanExpressionsIntroduction to Karnaugh MapsOne Variable, Two variable,Three Variable mapsFour Variable MapTutorialFive Variable K-Map andExamplesSix Variable K-Maps ExamplesMinimal Expressions forincomplete Boolean functionsQuine-McCluskey MethodPrime implicants and EssentialPrime ImplicantsPertickson Method forirredundant expressionSlip Test on UNIT-2DateII SEM –B 13BB3-9-13BB4-9-135-9-13BBBBRemarks
Date:LESSON PLAN25.07.2013To 09.11.2013Sub Name : Digital Logic DesignBranch: B.Tech emester& Section:Introduction to CombinationalLogic, Design Procedure,Analysis ProcedureAddersSubtractorsCode ConversionMultilevel NAND circuitsMultilevel NOR circuitsTutorialIntoduction to CombinationalLogic with MSI And LSIBinary Parallel Adder, DecimalAdderDecimal AdderMagnitude ComparatorDecodersMultiplexersTutorialSlip test on UNIT-3Introduction to Sequential Logic,Flip FlopsTriggering of Flip-Flops,Analysis of Clocked SequentialCircuitsState Reduction and AssignmentFlip-Flop Excitation tablesDesign ProcedureDesign of CountersIntroduction to Registers, ShiftregistersRipple CountersSynchronous CountersTiming sequencesthe memory unitTutorialSlip test on Unit-4Read – Only Memory (ROM)Programmable Read OnlymemoryProgrammable Logic Device(PLD)II SEM –B SECBB7-9-13I MIDEXAMINATIONS (0309-2012 10-1323-10-1324-10-13BBBBBBBBBBBBBBBBBB
Date:LESSON PLAN25.07.2013To 09.11.2013Sub Name : Digital Logic DesignBranch: B.Tech CSE63.64.Semester& Section:Programmable Logic ArrayProgrammable Array Logic(PAL).TutorialSlip Test on tent beyond syllabus/ToolsContent beyond syllabus/ResearchpapersContent beyond syllabus/NewapplicationsContent beyond syllabus/R & DPracticePractice69.II SEM –B 6-11-137-11-139-9-13BBBBBBTEXT BOOKS :M.Morris Mano, ‘Digital Logic and Computer Design’, PHI.REFERENCES :1.M.Morris Mano, ‘Computer Engineering Hardware Design’, PHI2.Donald e Givone, Digital principles and Design, TMH (Unit II and V)Course Delivery Plan:WeekUnits1234511112Prepared bySignatureNameG. Naga LakshmiDesignation Asst. Professor6272839310113 4 4121314455 R RApproved byHOD/CSEProfessor1516R
Date:Sub Name : DISCRETE MATHEMATICAL STRUCTURESFaculty Name: B.ShyamalaClass: II B.TechBranch: CSESemester: I25.07.2013To 09.11.2013Course Description:The Discrete Mathematical Structures subject gives the ability to solve the large logicalproblems which applicable in research area. In this subject each unit gives different types of problemswhich applied in different areas. This subject covers mathematical logic for statement calculus andpredicate calculus, normal forms, predicate logic, inference theory for statement calculus andpredicate calculus, set theory on relations and function, algebraic structures, permutations,combinations, binomial, multinomial theorems, directed & undirected graphs, trees, spanning trees, itsalgorithms, minimum spanning trees, its algorithms, and solving recurrence relations with differentprocedures.Course Key Points: First unit covers Mathematical logic for Statement calculus and Predicate calculus, inferencetheory for Statement calculus and Predicate calculus, Normal forms equivalences and logicalimplications. Second unit deals about set theory in all relations and functions. Third unit covers the graph theory about its types, properties, algorithms, and coloring. Fourth unit covers algebraic structures and Combinatorics. Fifth unit deals with recurrence relations using generating functions and characteristic roots.Outcomes:All undergraduates will have An ability to apply knowledge of mathematical logic for computer science and engineering. An ability to identify, formulates, and solves engineering problems. By using the graph theory the person can easily understands the network topologies in realtime applications. By using this subject the person get knowledge about the applications of discrete structuresand computing, combinatorics, and graph theory.
Date:SYLLABUS25.07.2012Sub Name : DISCRETE MATHEMATICAL STRUCTURESFaculty Name: B.ShyamalaClass: II B.TechTo 09.11.2012Branch: CSESemester: IUNIT I:Mathematical Logic: Propositional Calculus: Statements and Notations, Connectives, Truth Tables,Tautologies, Equivalence of Formulas, Duality law, Tautological Implications, Normal Forms, Theory ofInference for Statement Calculus, Consistency of Premises, Indirect Method of Proof. Predicate calculus:Predicative Logic, Statement Functions, Variables and Quantifiers, Free & Bound Variables, Inference theoryfor predicate calculus.UNIT II:Set Theory: Introduction, Operations on Binary Sets, Principle of Inclusion and ExclusionRelations: Properties of Binary Relations, Relation Matrix and Digraph, Operations on Relations, Partition andCovering, Transitive Closure, Equivalence, Compatibility and Partial Ordering Relations, Hasse Diagrams.Functions: Bijective Functions, Composition of Functions, Inverse Functions, Permutation Functions,Recursive FunctionsUNIT III:Graph Theory: Basic Concepts of Graphs, Sub graphs, Matrix Representation of Graphs: Adjacency Matrices,Incidence Matrices, Isomorphic Graphs, Paths and Circuits, Eulerian and Hamiltonian Graphs, Multigraphs,(Problems and Theorems without proofs), Graph Theory II: Planar Graphs, Euler’s Formula, Graph Colouringand Covering, Chromatic Number,( Problems and Theorems without proofs), Trees, Directed trees, BinaryTrees, Decision Trees, Spanning Trees: Properties, Algorithms for Spanning trees and Minimum SpanningTree.UNIT IV:Algebraic Structures: Algebraic Systems with one Binary Operation, Properties of Binary operations, Semigroups and Monoids: Homomorphism of Semi groups and Monoids, Groups: Abelian Group, Cosets,Subgroups ( Definitions and Examples of all Structures), Lattice: Properties. Algebraic Systems with twoBinary Operations: Rings. Combinatorics: Basic of Counting, Permutations, Derangements, Permutations withRepetition of Objects, Circular Permutations, Restricted Permutations, Combinations, Restricted Combinations,Pigeonhole Principle and its Application, Binomial Theorem, Binomial and Multinomial Coefficients.UNIT V: Recurrence Relation: Generating Function of Sequences, Partial Fractions, Calculating Coefficientof Generating Functions, Recurrence Relations, Formulation as Recurrence Relations, Solving linearhomogeneous recurrence Relations by substitution, generating functions and The Method of CharacteristicRoots. Solving Inhomogeneous Recurrence RelationsTEXT BOOKS:1. Discrete Mathematical Structures with Applications to Computer Science, Tremblay, Manohar, TMH2. Discrete Mathematics for Computer Scientists & Mathematicians, 2/e, Mott, Kandel, Baker, PHIREFERENCE BOOKS:1. Discrete Mathematics, S.Santha, Cengage2. Discrete Mathematics with Applications, Thomas Koshy, Elsevier3. Discrete Mathematics,2/e, JK Sharma ,Macmillan4. Discrete Mathematics,Chandrasekaran,Umaparvathi,2010,PHI5. Discrete and Combinational Mathematics, 5/e ,Ralph. P.Grimaldi, Ramana, Pearson6. Elements of Discrete Mathematics, CL Liu,Mahapatra,TMH
Date:LESSON PLAN25.07.2012Sub Name : DISCRETE MATHEMATICAL STRUCTURESFaculty Name: B.ShyamalaClass: II B.TechNo. 3.Topic to be CoveredTeaching AidUNIT-I3.4.9.UnitTo 09.11.2012Branch: CSE-ASemester: 324-8-1326-8-13UNIT-IIMathematical logic: PropositionalCalculus, Statements and NotationsConnectives, Truth TablesTautologies, Equivalence of FormulasDuality lawTautological ImplicationsNormal FormsNormal FormsTheory of Inference for StatementCalculusTheory of Inference for StatementCalculusTheory of Inference for StatementCalculusConsistency of Premises IndirectMethod of ProofPredicate calculus: Predicative LogicStatement Functions, Variables andQuantifiers Free & Bound VariablesInference theory for predicate calculusSet Theory: Introduction, Operations onBinary SetsPrinciple of Inclusion and ExclusionRelations: Properties of BinaryRelationsRelation Matrix and DigraphOperations on RelationsRelation Matrix and DigraphOperations on RelationsPartition and Covering, TransitiveClosureEquivalence RelationCompatibility RelationPartial Ordering Relation & HasseDiagramsBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack BoardBlack Board
354.7-10-135-10-13UNIT-VPartial Ordering Relation & HasseDiagramsFunctions: Bijective FunctionsComposition of Functions, tionsBasic Concepts of Graphs, Sub graphsMatrix Representation of c Graphs, Paths and CircuitsEulerian Graphs, Hamiltonian GraphsMultigraphs, Planar Graphs, Euler’sFormulaGraph Colouring and Covering,Chromatic NumberTrees, Directed treesBinary Trees, Decision TreesSpanning Trees: PropertiesAlgorithms for Spanning trees andMinimum Spanning TreesAlgorithms for Spanning trees andMinimum Spanning Trees
9 BCD to Excess-3 code converter 09-09-2013 BB 9 BCD to Gray code converter 16-09-2013 BB 10 Decoders, Multiplexer 23-09-2013 BB 11 Flip-flops 30-09-2013 BB 12 UP counter 07-10-2013 BB 13 Mod-3 counter 14-10-2013 BB 14 Down counter 21-10-2013 BB 14 Bidirectional counter 28-10-2013 BB .
4 Step Phonics Quiz Scores Step 1 Step 2 Step 3 Step 4 Lesson 1 Lesson 2 Lesson 3 Lesson 4 Lesson 5 Lesson 6 Lesson 7 Lesson 8 Lesson 9 Lesson 10 Lesson 11 Lesson 12 Lesson 13 Lesson 14 Lesson 15 . Zoo zoo Zoo zoo Yoyo yoyo Yoyo yoyo You you You you
The Intermediate Value Theorem Lesson Plan Functions and Number Sense Lesson Plan Limit Definition of the Definite Integral Lesson Plan The Derivative at a Point The Derivative Function Lesson Plan Local Linearity Lesson Plan The Quotient Rule Lesson Plan Implicit Differentiation Lesson Plan Related Rates .
Lesson Plan). The lesson plan (sometimes also called lesson note) is included both Type A and Type B. The format of the lesson plan is the same as the standard lesson plan that Ghana Education Service (GES) provides. The sample lesson plans of Type A also contain “lesson plan with teaching hints” on the next page of the standard lesson plan.
Participant's Workbook Financial Management for Managers Institute of Child Nutrition iii Table of Contents Introduction Intro—1 Lesson 1: Financial Management Lesson 1—1 Lesson 2: Production Records Lesson 2—1 Lesson 3: Forecasting Lesson 3—1 Lesson 4: Menu Item Costs Lesson 4—1 Lesson 5: Product Screening Lesson 5—1 Lesson 6: Inventory Control Lesson 6—1
Lesson 41 Day 1 - Draft LESSON 42 - DESCRIPTIVE PARAGRAPH Lesson 42 Day 1 - Revise Lesson 42 Day 1 - Final Draft Lesson 42 - Extra Practice LESSON 43 - EXPOSITORY PARAGRAPH Lesson 43 Day 1 - Brainstorm Lesson 43 Day 1 - Organize Lesson 43 Day 1 - Draft LESSON 44 - EXPOSITORY PARAGRAPH Lesson 44 Day 1 - Revise
iii UNIT 1 Lesson 1 I’m studying in California. 1 Lesson 2 Do you have anything to declare? 5 Lesson 3 From One Culture to Another 8 UNIT 2 Lesson 1 You changed, didn’t you? 13 Lesson 2 Do you remember . . . ? 17 Lesson 3 Women’s Work 20 UNIT 3 Lesson 1 We could have an international fall festival! 25 Lesson 2 You are cordially invited. 29 Lesson 3 Fall Foods 32 UNIT 4 Lesson 1 Excuses .
For Children 4-7 Years Old Series 6 Old Testament: Genesis From Creation to the Patriarchs Lesson 1 Creation Lesson 2 Adam and Eve Lesson 3 Cain and Abel Lesson 4 Noah and the Ark Lesson 5 Abraham’s Call Lesson 6 Isaac – The Son of Promise Lesson 7 Isaac and Rebekah Lesson 8 Jacob and Esau Lesson 9 Jacob Marries Rachel Lesson 10 Jacob is .
Contents Preface 4 Lesson 1 What Is Wisdom? 14 Lesson 2 Wisdom and Foolishness 27 Lesson 3 The Example of Wise Men 40 Lesson 4 Our Home Life 55 Lesson 5 Honoring Our Parents 71 Lesson 6 Freedom and Responsibility 85 Lesson 7 How Attitudes Affect Actions 102 Lesson 8 Right Attitudes About Myself 117 Lesson 9 Good Friends and Bad Friends 130 Lesson 10 Choosing the Right Friends 140
