NEPP ETW 2018: FPGA Assurance: From Radiation .

FPGA Assurance: from RadiationSusceptibility through Trust andSecurityMelanie Berg, AS&D Inc. in support of theNEPP Program and NASA/GSFCMelanie.D.Berg@NASA.govKenneth LaBel: NASA/GSFCMichael Campola: NASA/GSFCTo be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June18–21, 2018

�ME MCCSECUDCDCUDefinition1 MegabitThree DimensionalThree Dimensional Integrated CircuitsAbsolute Contacting EncoderAdvanced high performance busAnalog to Digital ConverterAutomotive Electronics CouncilAdvanced Encryption StandardAir ForceAir Force Research LaboratoryAdvanced Micro Devices IncorporatedAgile Mixed SignalAcorn Reduced Instruction Set Computer MachineAdvanced extensible interfaceBritish AerospaceBall Grid ArrayBlock Random Access MemoryBlock triple modular redundancyBrigham Young UniversityController Area NetworkConductive Bridging Random Access MemoryCorrect Coding InitiativeColumn Grid ArrayComplementary Metal Oxide SemiconductorXilinx ceramic flip-chip (CF and CN) packages are ceramic column grid array(CCGA) packagesCommercial Off The ShelfCyclic Redundancy CheckCosmic Ray Effects on Micro ElectronicsCosmic Ray Effects on Micro Electronics Monte CarloCrypto Security EngineerControl UnitDirect currentDistributed Control UnitDDRDouble Data Rate (DDR3 Generation 3; DDR4 Generation 4)DFFDMMDMADSPDSPIDTMRDual GPUGRCGSFCFlip-flopDigital MultimeterDirect Memory AccessDigital Signal ProcessingDynamic Signal Processing InstrumentDistributed triple modular redundancyDual ChannelDevice under testError-Correcting CodeError detection and correctionElectrical, Electronic, and ElectromechanicalEquipment Monitor And ControlMulti-die Interconnect BridgeExtended physical coding layerEuropean Space AgencyElectronics Technology WorkshopFramework for assessing security and trust in microelectronicsFluidized Catalytic Cracking UnitFerroelectric Random Access MemoryFin Field Effect TransistorFinite impulse response filterField Programmable Gate ArrayFloating Point UnitFiscal YearGigabitGigabit per secondGalactic Cosmic Raygeostationary equatorial orbitGlobal Industry ClassificationGovernment Microcircuit Applications and Critical Technology ConferenceGeneral purpose input/outputGeneral purpose interface busGraphics Processing UnitNASA Glenn Research CenterGoddard Space Flight EVHMCHOSTHP cronymsDefinitionGoal Structured NotationTransceiver TypeGlobal TMRHighly Accelerated Life TestHighly Accelerated Stress TestHigh Bandwidth MemoryHigh Density Digital Input/OutputHigh-Dynamic-RangeHigh Reliability Virtual Electronics CenterHybrid Memory CubeHardware Oriented Security and TrustHewlett-Packard LaboratoriesHigh Performance Input/OutputHigh Pressure SodiumHigh speed transceiver logicinterfaceKBinput/outputInter-Integrated CircuitMicrosemi second generation of Rad-Hard MOSFETIntegrated Circuitindependent cacheJoint Federated Assurance CenterJoint Photographic Experts GroupJet propulsion laboratoryJoint Test Action Group (FPGAs use JTAG to provideaccess to their programming debug/emulation functions)KilobyteL2 Cacheindependent caches organized as a hierarchy (L1, L2, etc.)LCDTNEPP low cost digital testerLEOLow Earth OrbitLETL-memLANLLPLUTLVCMOSLVDSLVTTLLTMRLW HPSM/L CMOSFETMPMPMPFEMPSoCMPUMsgMTTFNANDNASANASA STMDNavy CraneNEPPNGSPNORLinear energy transferLong-MemoryLos Alamos National LaboratoryLow PowerLook-up tableLow-voltage Complementary Metal Oxide SemiconductorLow-Voltage Differential SignalingLow –voltage transistor-transistor logicLocal triple modular redundancyLightwatt High Pressure SodiumMemory/Logic Built-In Self-TestMilitary standardMilitary Aerospace Programmable Logic DeviceModel-Based Missions AssuranceMean fluence to failureMicro programmable read-only memoryMicro SRAMMilitary/AerospaceMobile Industry Processor InterfaceMultiMediaCardMetal-Oxide-Semiconductor Field-Effect TransistorMicroprocessorMultiportMultiport Front-EndMultiprocessor System on a chipMicroprocessor UnitmessageMean time to failureNegated AND or NOT ANDNational Aeronautics and Space AdministrationNASA's Space Technology Mission DirectorateNaval Surface Warfare Center, Crane, IndianaNASA Electronic Parts and PackagingNext Generation Space ProcessorNot OR logic gateJTAGAcronymNRLNROOCMNaval Research LaboratoryNational Reconnaissance OfficeOn-chip RAMPCPCBPCIePersonal ComputerPrinted Circuit BoardPeripheral Component Interconnect ExpressPCIe Gen2Peripheral Component Interconnect Express Generation 2PconfigurationPfunctional logicSEU cross-section of configurationSEU cross-section of functional logicPHYPhysical SEESEFISELSERDESSETSEUSiSK HynixSMDsSMMUSNLSOASOCSPISSTLTBDTempTHD NTMRT-SensorTSMCUARTPhase Locked LoopPhysical Medium AttachmentPower on resetProcessingHigh Speed Bus InterfaceSEU cross-section from single event functional interruptsSystem SEU cross-sectionquad data rateQuad Flat Pack No LeadQualified manufactures listSerial Quad Input/OutputIEEE Radiation and its Effects on Components and SystemsResistor capacitorReliability and MaintainabilityRandom Access MemoryResistive Random Access MemoryRed, Green, and BlueRadiation HardenedRadiation TolerantSerial Advanced Technology AttachmentSecondary Control UnitSecure DigitalSecure Digital embedded MultiMediaCardSecure Digital High CapacitySpatial-Division-MultiplexingSingle Event EffectSingle Event Functional InterruptSingle event latchupSerializer/deserializerSingle event transientSingle event upsetSiliconSK Hynix Semiconductor CompanySelected Item DescriptionsSystem Memory Management UnitSandia National LaboratoriesSafe Operating AreaSystems on a ChipSerial Peripheral InterfaceSub series terminated logicTo Be DeterminedTemperatureTotal Harmonic Distortion Plus NoiseTriple Modular RedundancyTemperature-SensorTaiwan Semiconductor Manufacturing CompanyUniversal Asynchronous Receiver/TransmitterUltra Random Access MemoryUniversal Serial BusVertical NANDWatchdog TimerWindowed shift registerExtended 10 Gigabit Media Independent Interface10 Gigabit Ethernet Extended Sublayer10 Gigabit Media Independent Interface)Xilinx Security Working tionTo be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June18–21, 20182

Outline Field programmable gate array (FPGA) singleevent effect (SEE) test guidelines. Xilinx Kintex-UltraScale heavy-ion single eventupset (SEU). Upcoming heavy-ion testing. Proton SEE test results. Xilinx Kintex-UltraScale Deliverables. Challenges: Xilinx Kintex-UltraScale SEE testing. NEPP involvement with FPGA security and trust.NEPP Providing the following for FPGA drivenapplications: guidance, radiation SEE data andanalysis, mitigation strategies, and governmenttrust/security process development.To be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June18–21, 20183

FPGA SEU Test Guidelines Impact to community:DUT: device under test– It can be challenging to compare FPGA SEU data because ofdifferences in test vehicle and test methodology.– The FPGA SEU Test Guidelines Document createsstandardized test methodologies and provides a means fordata comparison across organizations and FPGA types.– The FPGA SEU Test Guidelines Document points out bestpractices for DUT test structures, monitoring DUT functionalresponse, visibility into DUT operation, DUT control, and DUTpower. Update of the test guideline best practices will beavailable by October 2018.– Additional test structures for SEU investigations.– Additional “do’s” and “should-not-do’s.”– Embedded processor testing techniques.https://nepp.nasa.gov/files/23779/fpga radiation test guidelines 2012.pdfTo be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June18–21, 20184

NEPP FPGA Radiation Testing IsDifferentiated From Most OtherOrganizations Low cost digital tester (LCDT) – board with FPGA that suppliesDUT stimulus and monitors DUT response.Custom built DUT board that connects via high speed interface tothe LCDT.Visibility of DUT response is significantly enhanced versusevaluation boards.LCDT is state machine based (not processor based). Providesfine grained monitoring and reporting (ns versus s).– Hak Kim and the NEPP engineering team built the LCDT board.– Custom test controls are designed into the LCDT FPGA.– Custom test structures are designed into the DUT FPGA. NEPP currently uses evaluation boards for memory testing.NEPP is investigating the use of evaluation boards for complexFPGA testing.To be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June18–21, 20185

SRAM: Static random access memorySRAM-based FPGA Mitigation Studyusing Xilinx Kintex-UltraScale(XCKU040-1LFFVA1156I)To be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June18–21, 20186

Impact to CommunityKintex-UltraScaleσSEU: SEU Cross-sectionSEFI: Single event functional interrupt Current generation of Xilinx FPGA devices targeted for spaceapplications. High-speed I/O interfaces are significantly more robust thanprevious generations. There are no embedded mitigation circuits in the user fabric.However, higher gate-count allows the user to more efficientlyinsert mitigation into the design. There is no embedded processor. However, the user can embed asoft-core.Design σSEUConfiguration σSEUFunctional logicσSEUSEFI σSEUNEPP performs an independent study to determine the levelof SEU susceptibility for the various FPGA components.To be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June18–21, 20187

Xilinx Kintex-UltraScale StudyObjectives This is an independent investigation that evaluates the singleevent destructive and transient susceptibility of the the XilinxKintex-UltraScale device.FPGA susceptibility is both design and device dependent.– There will be events that are unique to a design.– There will be events that are specifically due to device features. Design/Device susceptibility is determined by monitoring the DUTfor Single Event Transient (SET) and Single Event Upset (SEU)induced faults by exposing the DUT to a heavy ion beam.Potential Single Event Latch-up (SEL) is checked throughoutheavy-ion testing by monitoring device current and temperature.This device does not have embedded mitigation. Hence, userimplemented mitigation is investigated using Synopsysmitigation tools.FPGA part# XCKU040-1LFFVA1156I.Collaboration: Xilinx, Mentor Graphics, and Synopsys.To be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June18–21, 20188

Test Facility Conditions Facility: Texas A&M University Cyclotron SingleEvent Effects Test Facility, 25 MeV/amu tune. Flux: 1 x 102 to 5 x 105 particles/cm2·s Fluence: All tests were run to 1 x 107. 5 x 107particles/cm2 or until destructive or functional eventsoccurred.Room temperatureIon Test temperature:EnergyLET (MeV*cm2/mg) LET (MeV*cm2/mg)He(MEV/Nucleon)250 .0760 538.978.8We were unable to obtain Kr and Xe during our testingTo be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June18–21, 20189

Kintex-UltraScale DUT And TesterTo be presented by Melanie Berg at the NASA Electronics Parts and Packaging (NEPP) Electronics Technology Workshop (ETW), Greenbelt, MD, June18–21, 201810