R QPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAs
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —R123QPro Virtex-II 1.5V Radiation-HardenedQML Platform FPGAsDS124 (v2.0) April 7, 2014Product SpecificationSummary of Radiation-Hardened QPro Virtex-II FPGA Features Industry First Radiation-Hardened FPGA SolutionGuaranteed total ionizing dose to 200K Rad(Si)Latch-up immune to LET 160 MeV-cm2/mgSEU in GEO upsets 1.5E-6 per device dayachievable with recommended redundancyimplementationCertified to MIL-PRF-38535 (Qualified ManufacturerListing)Guaranteed over the full military temperature range(–55 C to 125 C)0.15 µm 8-Layer Metal Process with 0.12 µmHigh-Speed TransistorsCeramic and Plastic Wire-Bond and Flip-Chip GridArray PackagesIP-Immersion Architecture Densities from 1M to 6M system gates 300 MHz internal clock speed (Advance Data) 622 Mb/s I/O (Advance Data)SelectRAM Memory Hierarchy 2.5 Mb of dual-port RAM in 18 Kbit blockSelectRAM resources Up to 1 Mb of distributed SelectRAM resourcesHigh-Performance Interfaces to External Memory DRAM interfaces- SDR/DDR SDRAM- Network FCRAM- Reduced Latency DRAM SRAM interfaces- SDR/DDR SRAM- QDR SRAM CAM interfacesArithmetic Functions Dedicated 18-bit x 18-bit multiplier blocks Fast look-ahead carry logic chainsFlexible Logic Resources Up to 67,584 internal registers/latches with ClockEnable Up to 67,584 look-up tables (LUTs) or cascadable16-bit shift registers Wide multiplexers and wide-input function support Horizontal cascade chain and sum-of-productssupport Internal 3-state busing High-Performance Clock Management Circuitry Up to 12 DCM (Digital Clock Manager) modules- Precise clock de-skew- Flexible frequency synthesis- High-resolution phase shifting 16 global clock multiplexer buffersActive Interconnect Technology Fourth generation segmented routing structure Predictable, fast routing delay, independent offanoutSelectIO -Ultra Technology Up to 824 user I/Os 19 single-ended and six differential standards Programmable sink current (2 mA to 24 mA) per I/O Digitally Controlled Impedance (DCI) I/O: on-chiptermination resistors for single-ended I/O standards Differential Signaling- 622 Mb/s Low-Voltage Differential SignalingI/O (LVDS) with current mode drivers- Bus LVDS I/O- Lightning Data Transport (LDT) I/O with currentdriver buffers- Low-Voltage Positive Emitter-Coupled Logic(LVPECL) I/O- Built-in DDR input and output registers Proprietary high-performance SelectLink Technology- High-bandwidth data path- Double Data Rate (DDR) link- Web-based HDL generation methodologySupported by Xilinx Foundation Series and AllianceSeries Development Systems Integrated VHDL and Verilog design flows Compilation of 10M system gates designs Internet Team Design (ITD) toolSRAM-Based In-System Configuration Fast SelectMAP configuration IEEE 1532 support Partial reconfiguration Unlimited reprogrammability Readback capability1.5V (VCCINT) Core Power Supply, Dedicated 3.3VVCCAUX Auxiliary and VCCO I/O Power SuppliesIEEE 1149.1 Compatible Boundary-Scan Logic Support Copyright 2003–2014 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States andother countries. All other trademarks are the property of their respective owners.DS124 (v2.0) April 7, 2014Product Specificationwww.xilinx.com1
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsGeneral DescriptionThe QPro Virtex -II radiation-hardened family includesplatform FPGAs developed for high performance,high-density, aerospace designs that are based on IP coresand customized modules. The family delivers completesolutions for telecommunication, networking, video, andDSP applications, including PCI, LVDS, and DDR interfaces.The leading-edge 0.15 µm/0.12 µm CMOS 8-layer metalprocess and the Virtex-II architecture are optimized for highspeed with low power consumption. Combining a widevariety of flexible features and a large range of densities upto 6 million system gates, the Virtex-II family enhancesprogrammable logic design capabilities and is a powerfulalternative to mask-programmed gates arrays and otherone-time-programmable devices. As shown in Table 1, theQPro Virtex-II radiation hardened family comprises threemembers, ranging from 1M to 6M system gates.Table 1: Virtex-II Field-Programmable Gate Array Family MembersDeviceSystemGatesCLB(1 CLB 4 slices Max 128 bits)ArrayRow x Col.SlicesMaximumDistributedRAM KbitsSelectRAM BlocksMultiplierBlocks18 KbitBlocksMax RAM(Kbits)DCMsMax I/OPads(1)XQR2V10001M40 x 325,12016040407208432XQR2V30003M64 x 5614,33644896961,72812720XQR2V60006M96 x 8833,7921,0561441442,592121,104Notes:1.See details in Table 2.PackagingOfferings include ball grid array (BGA) packages with1.00 mm and 1.27 mm pitches. In addition to traditionalwire-bond interconnects, flip-chip interconnect is used insome of the CGA offerings. The use of flip-chip interconnectoffers more I/Os than is possible in wire-bond versions ofthe similar packages. Flip-chip construction offers thecombination of high pin count with high thermal capacity.Table 2 shows the maximum number of user I/Os available.The Virtex-II device/package combination table (Table 6,page 7) details the maximum number of I/Os for eachdevice and package using wire-bond or flip-chip technology.Table 2: Maximum Number of User I/O 00516–XQR2V6000–824DS124 (v2.0) April 7, 2014Product Specificationwww.xilinx.com2
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsRadiation AssuranceThe Virtex-II Radiation-Hardened Platform FPGAs areguaranteed for Total Ionizing Dose (TID) life and SingleEvent Latch-Up immunity (SEL).verified in a heavy ion environment under vacuum, andtested with an LET that exceeds Space environmentphenomenon, to a fluence that exceeds 1E7 particles/cm2.Total Ionizing DoseSingle Event UpsetEach Wafer Lot is sampled and tested per Method 1019.5 toassure that device performance meets or exceeds theguaranteed DC electrical specification requirements, aswell as AC and Timing parameters at maximum guaranteedtotal dose levels.Additional experiments are conducted in heavy ion, proton,and neutron environments in order to measure anddocument the susceptibility and consequence of SEU(s).An industry consortium oversees and validates the testmethods, empirical data collected, and resulting analysis.Conclusions are published on the website as well asInternational Conferences. The Single Event EffectsConsortium Reports can be found atSingle Event Latch-UpThe radiation-hardened Virtex-II technology incorporates athin epitaxial layer in the wafer manufacturing process forlatch-up immunity assurance. The qualified mask set ishttp://www.xilinx.com/products/hirel qml.htmRadiation Specifications(1)Table 3: Minimum Radiation TolerancesSymbolDescriptionMinMaxUnitsTIDTotal Ionizing DoseMethod 1019.5, Dose Rate 50.0 rad(Si)/sec200-krad(Si)SELSingle Event Latch-up ImmunityHeavy Ion Linear Energy Transfer (LET)160-(MeV-cm2/mg)SEFISingle Event Functional InterruptGEO 36,000km Typical Day1.5E-6Upsets/Device/DayNotes:1.For more information, refer to "Single Event Effects Consortium Report, Static SEU Response for the Rad Hard Virtex-II" athttp://www.xilinx.com/products/hirel qml.htm.DS124 (v2.0) April 7, 2014Product Specificationwww.xilinx.com3
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsArchitectureVirtex-II FPGA Array OverviewVirtex-II devices are user-programmable gate arrays withvarious configurable elements. The Virtex-II architecture isoptimized for high-density and high-performance logicdesigns. As shown in Figure 1, the programmable device iscomprised of input/output blocks (IOBs) and internalconfigurable logic blocks (CLBs).Programmable I/O blocks provide the interface betweenpackage pins and the internal configurable logic. Mostpopular and leading-edge I/O standards are supported bythe programmable IOBs.The internal configurable logic includes four major elementsorganized in a regular array: Configurable Logic Blocks (CLBs) provide functionalelements for combinatorial and synchronous logic,including basic storage elements. BUFTs (3-statebuffers) associated with each CLB element drivededicated segmentable horizontal routing resources. Multiplier blocks are 18-bit x 18-bit dedicatedmultipliers. DCM (Digital Clock Manager) blocks provideself-calibrating, fully digital solutions for clockdistribution delay compensation, clock multiplicationand division, coarse- and fine-grained clock phaseshifting.A new generation of programmable routing resources calledActive Interconnect Technology interconnects all of theseelements. The general routing matrix (GRM) is an array ofrouting switches. Each programmable element is tied to aswitch matrix, allowing multiple connections to the generalrouting matrix. The overall programmable interconnection ishierarchical and designed to support high-speed designs.All programmable elements, including the routingresources, are controlled by values stored in static memorycells. These values are loaded in the memory cells duringconfiguration and can be reloaded to change the functionsof the programmable elements.Block SelectRAM memory modules provide large18 Kbit storage elements of dual-port RAM.DCMDCMIOBGlobal Clock MuxConfigurable LogicProgrammable I/OsCLBBlock SelectRAMMultiplierDS031 28 100900Figure 1: Virtex-II Architecture OverviewDS124 (v2.0) April 7, 2014Product Specificationwww.xilinx.com4
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsVirtex-II FPGA FeaturesThe function generators F and G are configurable as 4-inputlook-up tables (LUTs), as 16-bit shift registers, or as 16-bitdistributed SelectRAM memory.This section briefly describes Virtex-II FPGA features.Input/Output Blocks (IOBs)IOBs are programmable and can be categorized as follows:Each CLB has internal fast interconnect and connects to aswitch matrix to access general routing resources. Input block with an optional single-data-rate ordouble-data-rate (DDR) register Output block with an optional single-data-rate or DDRregister, and an optional 3-state buffer, to be drivendirectly or through a single or DDR register Bidirectional block (any combination of input and outputconfigurations)These registers are either edge-triggered D-type flip-flopsor level-sensitive latches.IOBs support the following single-ended I/O standards: In addition, the two storage elements are eitheredge-triggered D-type flip-flops or level-sensitive latches.LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)PCI compatible (33 MHz) at 3.3VCardBus compliant (33 MHz) at 3.3VGTL and GTLPHSTL (Class I, II, III, and IV)SSTL (3.3V and 2.5V, Class I and II)AGP-2XBlock SelectRAM MemoryThe block SelectRAM memory resources are 18 Kb ofdual-port RAM, programmable from 16K x 1 bit to 512 x 36bits, in various depth and width configurations. Each port istotally synchronous and independent, offering three"read-during-write" modes. Block SelectRAM memory iscascadable to implement large embedded storage blocks.Supported memory configurations for dual-port andsingle-port modes are shown in Table 4.A multiplier block is associated with each SelectRAMmemory block. The multiplier block is a dedicated18 x 18-bit multiplier and is optimized for operations basedon the block SelectRAM content on one port. The 18 x 18multiplier can be used independently of the blockSelectRAM resource. Read/multiply/accumulate operationsand DSP filter structures are extremely efficient.The digitally controlled impedance (DCI) I/O featureautomatically provides on-chip termination for each I/Oelement.The IOB elements also support the following differentialsignaling I/O standards:Both the SelectRAM memory and the multiplier resourceare connected to four switch matrices to access the generalrouting resources.Table 4: Dual-Port And Single-Port Configurations16K x 1 bit2K x 9 bits LVDS8K x 2 bits1K x 18 bits BLVDS (Bus LVDS)4K x 4 bits512 x 36 bits ULVDS LDT LVPECLGlobal ClockingThe DCM and global clock multiplexer buffers provide acomplete solution for designing high-speed clocking schemes.Two adjacent pads are used for each differential pair. Two orfour IOB blocks connect to one switch matrix to access therouting resources.Configurable Logic Blocks (CLBs)CLB resources include four slices and two 3-state buffers.Each slice is equivalent and contains: Two function generators (F and G) Two storage elements Arithmetic logic gates Large multiplexers Wide function capability Fast carry look-ahead chain Horizontal cascade chain (OR gate)DS124 (v2.0) April 7, 2014Product SpecificationUp to 12 DCM blocks are available. To generate de-skewedinternal or external clocks, each DCM can be used toeliminate clock distribution delay. The DCM also provides90-, 180-, and 270-degree phase-shifted versions of itsoutput clocks. Fine-grained phase shifting offershigh-resolution phase adjustments in increments of 1/256 ofthe clock period. Very flexible frequency synthesis providesa clock output frequency equal to any M/D ratio of the inputclock frequency, where M and D are two integers. For theexact timing parameters, see "QPro Virtex-II FPGASwitching Characteristics," page 53.Virtex-II devices have 16 global clock MUX buffers with upto eight clock nets per quadrant. Each global clock MUXbuffer can select one of the two clock inputs and switchglitch-free from one clock to the other. Each DCM block isable to drive up to four of the 16 global clock MUX buffers.www.xilinx.com5
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsRouting ResourcesBoundary ScanThe IOB, CLB, block SelectRAM, multiplier, and DCMelements all use the same interconnect scheme and thesame access to the global routing matrix. Timing modelsare shared, greatly improving the predictability of theperformance of high-speed designs.Boundary-scan instructions and associated data registerssupport a standard methodology for accessing andconfiguring Virtex-II devices that complies with IEEEstandards 1149.1 — 1993 and 1532. A system mode and atest mode are implemented. In system mode, a Virtex-IIdevice performs its intended mission even while executingnon-test boundary-scan instructions. In test mode,boundary-scan test instructions control the I/O pins fortesting purposes. The Virtex-II Test Access Port (TAP)supports BYPASS, PRELOAD, SAMPLE, IDCODE, andUSERCODE non-test instructions. The EXTEST, INTEST,and HIGHZ test instructions are also supported.There are a total of 16 global clock lines with eight availableper quadrant. In addition, 24 vertical and horizontal long linesper row or column as well as massive secondary and localrouting resources provide fast interconnect. Virtex-II bufferedinterconnects are relatively unaffected by net fanout, and theinterconnect layout is designed to minimize crosstalk.Horizontal and vertical routing resources for each row orcolumn include: 24 long lines 120 hex lines 40 double lines 16 direct connect lines (total in all four directions)DS124 (v2.0) April 7, 2014Product Specificationwww.xilinx.com6
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsVirtex-II FPGA Device/Package Combinations and Maximum I/OWire-bond and flip-chip packages are available. Table 5shows the maximum possible number of user I/Os inwire-bond and flip-chip packages. Table 6 shows thenumber of available user I/Os for all device/packagecombinations. FG denotes wire-bond fine-pitch Plastic BGA (1.00 mmpitch). BG denotes wire-bond standard Plastic BGA (1.27 mmpitch). CG denotes wire-bond fine-pitch Hermetic CeramicColumn Grid Array (1.27 mm pitch). CF denotes flip-chip fine-pitch non-Hermetic CeramicColumn Grid Array (1.00 mm pitch).The number of I/Os per package include all user I/Os exceptthe 15 control pins (CCLK, DONE, M0, M1, M2, PROG B,PWRDWN B, TCK, TDI, TDO, TMS, HSWAP EN, DXN,DXP, and RSVD) and VBATT.Table 5: Package InformationPackageFG456BG575BG728 & CG717CF1144Pitch (mm)1.001.271.271.00Size (mm)23 x 2331 x 3135 x 3535 x 35Table 6: Virtex-II Device/Package Combinations and Maximum Number of Available I/OsPackageAvailable 24Notes:1.2.The BG728 and CG717 packages are pinout (footprint) compatible.The CF1144 is pinout (footprint) compatible with the FF1152.DS124 (v2.0) April 7, 2014Product Specificationwww.xilinx.com7
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsVirtex-II FPGA Ordering InformationExample:XQR2V3000 -4 CG 717 VDevice TypeProduct GradeSpeed Grade(1)Number of PinsPackage TypeDevice Ordering OptionsDevice 00FG456456-ball Plastic Fine Pitch BGA PackageMM-GradeXQR2V3000BG575575-ball Plastic BGA PackageVQPRO-PLUSXQR2V6000BG728728-ball Plastic BGA PackageHQPRO-FCCCG717717-column Hermetic Ceramic CGAPackageNClass NCF11441144-column Non-hermetic CeramicFlip-Chip PackageRQPRO PLUSPEMTemperatureRangeMilitary CeramicTC –55 C to 125 CMilitary PlasticTJ –55 C to 125 CNotes:1.2.-4 is the only supported speed grade.A detailed explanation of the Manufacturing and Test Flows is available at Valid Ordering 4M1XQR2V6000-4CF1144H1HNotes:1.CF1144 is non-Hermetic Ceramic.DS124 (v2.0) April 7, 2014Product Specificationwww.xilinx.com8
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsDetailed DescriptionInput/Output Blocks (IOBs)Table 7: Supported Single-Ended I/O Standards (Cont’d)Virtex-II FPGA I/O blocks (IOBs) are provided in groups oftwo or four on the perimeter of each device. Each IOB canbe used as an input and/or an output for single-ended I/Os.Two IOBs can be used as a differential pair. A differentialpair is always connected to the same switch matrix, asshown in Figure 2.IOB blocks are designed for high-performance I/Os,supporting 19 single-ended standards, as well asdifferential signaling with LVDS, LDT, Bus LVDS, andLVPECL.IOBPAD4Differential PairIOBPAD3SwitchMatrixIOBPAD2Differential ationVoltage (VTT)3.33.3N/AN/AGTLNote 1Note 10.81.2GTLPNote 1Note 11.01.5HSTL I1.5N/A0.750.75HSTL II1.5N/A0.750.75HSTL III1.5N/A0.91.5HSTL IV1.5N/A0.91.5HSTL I1.8N/A0.90.9HSTL II1.8N/A0.90.9HSTL III1.8N/A1.11.8HSTL IV1.8N/A1.11.8SSTL2 I2.5N/A1.251.25SSTL2 II2.5N/A1.251.25SSTL3 I3.3N/A1.51.5SSTL3 I-XDS031 30 101600Notes:Figure 2: Virtex-II FPGA Input/Output Tile1.Note: Differential I/Os must use the same clock.Supported I/O StandardsTable 8: Supported Differential Signal I/O StandardsVirtex-II FPGA IOB blocks feature SelectIO-Ultra inputs andoutputs that support a wide variety of I/O signalingstandards. In addition to the internal supply voltage(VCCINT 1.5V), output driver supply voltage (VCCO) isdependent on the I/O standard (see Table 7). An auxiliarysupply voltage (VCCAUX 3.3 V) is required, regardless ofthe I/O standard used. For exact supply voltage absolutemaximum ratings, see "DC Input and Output Levels,"page 51.Table 7: Supported Single-Ended I/O ionVoltage /APCI33 33.33.3N/AN/APCI66 33.33.3N/AN/AI/OStandardDS124 (v2.0) April 7, 2014Product SpecificationVCCO of GTL or GTLP should not be lower than the terminationvoltage or the voltage seen at the I/O pad.OutputVCCOInputVCCOInputVREFOutputVODLVPECL 333.3N/AN/A490 mV to 1.22VLDT 252.5N/AN/A0.430 - 0.670LVDS 333.3N/AN/A0.250 - 0.400LVDS 252.5N/AN/A0.250 - 0.400LVDSEXT 333.3N/AN/A0.330 - 0.700LVDSEXT 252.5N/AN/A0.330 - 0.700BLVDS 252.5N/AN/A0.250 - 0.450ULVDS 252.5N/AN/A0.430 - 0.670I/O StandardAll of the user IOBs have fixed-clamp diodes to VCCO and toground. As outputs, these IOBs are not compatible orcompliant with 5V I/O standards. As inputs, these IOBs arenot normally 5V tolerant, but can be used with 5V I/Ostandards when external current-limiting resistors are used.For more details, see the “5V Tolerant I/Os” Tech Topic athttp://www.xilinx.com.Table 9 lists supported I/O standards with DigitallyControlled Impedance. See "Digitally Controlled Impedancewww.xilinx.com9
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAs(DCI)," page 16.IOBTable 9: Supported DCI I/O rminationTypeLVDCI 33 (1)3.33.3N/ASeriesLVDCI DV2 33 (1)3.33.3N/ASeriesLVDCI 25 (1)2.52.5N/ASeriesLVDCI DV2 25 (1)2.52.5N/ASeriesLVDCI 18 (1)1.81.8N/ASeriesLVDCI DV2 18 (1)1.81.8N/ASeriesLVDCI 15 (1)1.51.5N/ASeriesLVDCI DV2 15 (1)1.51.5N/ASeriesGTL DCI1.21.20.8SingleGTLP DCI1.51.51.0SingleHSTL I DCI1.51.50.75SplitHSTL II DCI1.51.50.75SplitHSTL III DCI1.51.50.9SingleHSTL IV DCI1.51.50.9SingleHSTL I DCI1.8N/A0.9SplitHSTL II DCI1.8N/A0.9SplitHSTL III DCI1.8N/A1.1SingleHSTL IV DCI1.8N/A1.1SingleSSTL2 I DCI (2)2.52.51.25SplitSSTL2 II DCI (2)2.52.51.25SplitSSTL3 I DCI (2)3.33.31.5SplitSSTL3 II DCI (2)3.33.31.5Split2.LVDCI XX and LVDCI DV2 XX are LVCMOS controlledimpedance buffers, matching the reference resistors or half of thereference resistors.These are SSTL compatible.Logic ResourcesIOB blocks include six storage elements, as shown in Figure 3.Each storage element can be configured either as anedge-triggered D-type flip-flop or as a level-sensitive latch.On the input, output, and 3-state path, one or two DDRregisters can be used.Double data rate is directly accomplished by the tworegisters on each path, clocked by the rising edges (orfalling edges) from two different clock nets. The two clocksignals are generated by the DCM and must be 180degrees out of phase, as shown in Figure 4. There are twoinput, output, and 3-state data signals, each beingalternately clocked out.The DDR mechanism shown in Figure 4 can be used tomirror a copy of the clock on the output. This is useful forpropagating a clock along the data that has an identical delay.It is also useful for multiple clock generation, where there is aunique clock driver for every clock load. Virtex-II devices canproduce many copies of a clock with very little skew.DS124 (v2.0) April 7, 2014Product CK2DDR muxRegOCK1PADRegOCK2OutputDS031 29 100900Notes:1.DDR muxFigure 3: Virtex-II FPGA IOB BlockEach group of two registers has a clock enable signal (ICEfor the input registers, OCE for the output registers, andTCE for the 3-state registers). The clock enable signals areactive High by default. If left unconnected, the clock enablefor that storage element defaults to the active state.Each IOB block has common synchronous or asynchronousset and reset (SR and REV signals).SR forces the storage element into the state specified bythe SRHIGH or SRLOW attribute. SRHIGH forces a logic“1”. SRLOW forces a logic “0”. When SR is used, a secondinput (REV) forces the storage element into the oppositestate. The reset condition predominates over the setcondition. The initial state after configuration or globalinitialization state is defined by a separate INIT0 and INIT1attribute. By default, the SRLOW attribute forces INIT0, andthe SRHIGH attribute forces INIT1.For each storage element, the SRHIGH, SRLOW, INIT0,and INIT1 attributes are independent. Synchronous orasynchronous set/reset is consistent in an IOB block.All the control signals have independent polarities. Anyinverter placed on a control input is automatically absorbed.Each register or latch (independent of all other registers orlatches) (see Figure 5) can be configured as follows: No set or resetSynchronous setSynchronous resetSynchronous set and resetAsynchronous set (preset)Asynchronous reset (clear)Asynchronous set and reset (preset and clear)The synchronous reset overrides a set, and anasynchronous clear overrides a preset.www.xilinx.com10
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsDCM180 0 FDDRFDDRD1D1Q1CLOCKQ1CLK1CLK1QDDR MUXDDR MUXD2QD2Q2Q2CLK2CLK2(50/50 duty cycle clock)DS031 26 100900Figure 4: Double Data Rate Registers(O/T) 1FFLATCH(O/T) CE(O/T) CLK1D1Q1Attribute INIT1INIT0SRHIGHSRLOWCECK1SR REVSRSharedby allregisters REVFF1DDR MUXFF2(OQ or TQ)FFLATCHD2(O/T) CLK2Q2CECK2SR REVAttribute INIT1INIT0SRHIGHSRLOW(O/T) 2Reset TypeSYNCASYNCDS031 25 110300Figure 5: Register/Latch Configuration in an IOB BlockDS124 (v2.0) April 7, 2014Product Specificationwww.xilinx.com11
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsInput/Output Individual OptionsEach device pad has optional pull-up and pull-downresistors in all SelectIO-Ultra configurations. Each devicepad has an optional weak-keeper in LVTTL, LVCMOS, andPCI SelectIO-Ultra configurations, as illustrated in Figure 6.Values of the optional pull-up and pull-down resistors are inthe range 10 - 60 KΩ, which is the specification for VCCOwhen operating at 3.3V (from 3.0V to 3.6V only). The clampdiode is always present, even when power is not.The optional weak-keeper circuit is connected to eachoutput. When selected, this circuit monitors the voltage onthe pad and weakly drives the pin High or Low. If the pin isconnected to a multiple-source signal, the weak-keeperholds the signal in its last state if all drivers are disabled.Maintaining a valid logic level in this way eliminates buschatter. Pull-up or pull-down resistors override theweak-keeper circuit.LVTTL sinks and sources current up to 24 mA. The currentis programmable for LVTTL and LVCMOS SelectIO-Ultrastandards (see Table 10). Drive-strength and slew-ratecontrols for each output driver minimize bus transients. ForLVDCI and LVDCI DV2 standards, drive strength andslew-rate controls are not available.VCCOClampDiodeOBUFVCCOProgram CurrentWeakKeeper10-60KΩPADVCCO10-60KΩVCCAUX 3.3VVCCINT 1.5VProgramDelayIBUFDS031 23 011601Figure 6: LVTTL, LVCMOS, or PCI SelectIO-Ultra StandardsTable 10: LVTTL and LVCMOS Programmable Currents (Sink and Source)SelectIO-UltraProgrammable Current (Worst-Case Guaranteed Minimum)LVTTL2 mA4 mA6 mA8 mA12 mA16 mA24 mALVCMOS332 mA4 mA6 mA8 mA12 mA16 mA24 mALVCMOS252 mA4 mA6 mA8 mA12 mA16 mA24 mALVCMOS182 mA4 mA6 mA8 mA12 mA16 mAn/aLVCMOS152 mA4 mA6 mA8 mA12 mA16 mAn/aDS124 (v2.0) April 7, 2014Product Specificationwww.xilinx.com12
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —RQPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAsFigure 7 shows the SSTL2, SSTL3, and HSTL configurations.HSTL can sink current up to 48 mA. (HSTL IV).VCCOClampDiodeOBUFOutput PathThe output path includes a 3-state output buffer that drivesthe output signal onto the pad. The output and/or the 3-statesignal can be routed to the buffer directly from the internallogic or through an output/3-state flip-flop or latch, orthrough the DDR output/3-state registers.Each output driver can be individually programmed for awide range of low-voltage signaling standards. In mostsignaling standards, the output High voltage depends on anexternally supplied VCCO voltage. The need to supply VCCOimposes constraints on which standards can be used in thesame bank. See "I/O Banking," page 13 description below.PADI/O BankingVREFSome of the I/O standards described above require VCCOand VREF voltages. These voltages are externally suppliedand connected to device pins that serve groups of IOBblocks, called banks. Consequently, restrictions exist aboutwhich I/O standards can be combined within a given bank.VCCAUX 3.3VVCCINT 1.5VDS031 24 100900Bank 0Bank 1Bank 5Bank 4Bank 6Bank 7Prior to configuration, all outputs not involved inconfiguration are forced into their high-impedance state.The pull-down resistors and the weak-keeper circuits areinactive. The dedicated pin HSWAP EN controls the pull-upresistors prior to configuration. By default, HSWAP EN isdriven High, which disables the pull-up resistors on user I/Opins. When HSWAP EN is driven Low, the pull-up resistorsare activated on user I/O pins.Bank 2All pads are protected against damage from electrostaticdischarge (ESD) and from over-voltage transients. Virtex-IIdevices use two memory cells to control the configuration ofan I/O as an input. This is to reduce the probability of an I/Oconfigured as an input from flipping to an output whensubjected to a single event upset (SEU) in spaceapplications.Eight I/O banks result from dividing each edge of the FPGAinto two banks, as shown in Figure 8 and Figure 9. Eachbank has multiple VCCO pins, all of which must beconnected to the same voltage. This voltage is determinedby the output standards in use.Bank 3Figure 7: SSTL or HSTL SelectIO-Ultra StandardsAll Virtex-II IOBs support IEEE 1149.1 compatibleboundary-scan testing.ug002 c2 014 112900Input PathThe Virtex-II IOB input path routes input signals directly tointernal logic and/or through an optional input flip-flop orlatch, or through the DDR input registers. An optional delayelement at the D-input of the storage element eliminatespad-to-pad hold time. The delay is matched to the internalclock-distribution delay of the Virtex-II device, and whenused, ensures that the pad-to-pad hold time is zero.Figure 8: Virtex-II I/O Banks: Top View for Wire-BondPackages (CS, FG, & BG)Some input standards require a user-supplied thresholdvoltage (VREF), and certain user-I/O pins are automaticallyconfigured as V
QPro Virtex-II 1.5V Radiation-Hardened QML Platform FPGAs DS124 (v2.0) April 7, 2014 www.xilinx.com Product Specification 3 R — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — Radiation Assurance The Virtex-II Radiation-Hardened Platform FPGAs are guaranteed for Total Ionizing Dose (TID) life and Single Event Latch-Up immunity (SEL).
QPro Virtex-II 1.5V Platform FPGAs DS122 (v3.0) April 7, 2014 www.xilinx.com Product Specification 5 — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — Block SelectRAM Memory The block SelectRAM memory resources are 18 Kb of dual-port RAM, programmable from 16K x 1 bit to 512 x 36 bits, in various depth and width configurations.
Spartan-3 Spartan-3A Spartan-3ADSP Spartan-3AN Spartan-3E Spartan-3L CPLDDevices - CoolRunner XPLA3 XST User Guide for Virtex-4, Virtex-5, Spartan-3, and Newer CPLD Devices UG627 (v 12.4) December 14, 2010 w w w .x ilin x .c o m 11
Note: In case of Virtex-4, Virtex-5 and Virtex-6: If the SPLB_Clk is greater than 100 MHz, the ICAP_Clk should be connected to 100 MHz. If the SPLB_Clk is less than or equal to 100 MHz, the ICAP_Clk should be connected to the frequency equivalent to SPLB_clk frequency. Note: In case of Spartan
various synthesis tools; and targeted for XC4000, Spartan, Spartan-II, Spartan-XL, Virtex, Virtex-E, Virtex-II and XC5200 devices. Xilinx equally endorses both Verilog and VHDL. VHDL may be more diffi-cult to learn than Verilog and usually requires more explanation. This manua
UG533 (v1.5) October 20, 2011 Preface: About This Guide Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in all Virtex-6 FPGAs excep
R Virtex -II Platform FPGAs: Introduction and Overview DS031-1 (v2.0) August 1, 2003 www.xilinx.com Module 1 of 4 Product Specification 1-800-255-7778 2 General Description The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that
R Virtex-II Platform FPGAs: Introduction and Overview DS031-1 (v3.4) March 1, 2005 www.xilinx.com Module 1 of 4 Product Specification 2 General Description The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that
Engineering Mathematics – I, Reena Garg, Khanna Book Publishing . AICTE Recommended Books for Undergraduate Degree Courses as per Model Curriculum 2018 AICTE Suggested Books in Engineering & Technology w.e.f. 2018-19 BSC103 – Mathematics – II 1. Advanced Engineering Mathematics, Chandrika Prasad & Reena Garg, Khanna Book Publishing 2. Higher Engineering Mathematics, Ramana B.V., Tata .
