Principles Of Computer Architecture - Radford University
Chapter 3 - Arithmetic3-1Principles of Computer ArchitectureMiles Murdocca and Vincent HeuringChapter 3: ArithmeticDepartment of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-2Chapter Contents3.1 Overview3.2 Fixed Point Addition and Subtraction3.3 Fixed Point Multiplication and Division3.4 Floating Point Arithmetic3.5 High Performance Arithmetic3.6 Case Study: Calculator Arithmetic Using Binary CodedDecimalDepartment of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-3Computer Arithmetic Using number representations from Chapter 2, we will explorefour basic arithmetic operations: addition, subtraction,multiplication, division. Significant issues include: fixed point vs. floating pointarithmetic, overflow and underflow, handling of signednumbers, and performance. We look first at fixed point arithmetic, and then at floatingpoint arithmetic.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-4Number Circle for 3-Bit Two’sComplement Numbers Numbers can be added or subtracted by traversing thenumber circle clockwise for addition and counterclockwise forsubtraction. Overflow occurs when a transition is made from 3 to -4 whileproceeding around the number circle when adding, or from -4to 3 while subtracting.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-5Overflow Overflow occurs when adding two positive numbers produces anegative result, or when adding two negative numbers produces apositive result. Adding operands of unlike signs never producesan overflow. Notice that discarding the carry out of the most significant bitduring two’s complement addition is a normal occurrence, anddoes not by itself indicate overflow. As an example of overflow, consider adding (80 80 160)10, whichproduces a result of -9610 in an 8-bit two’s complement format:01010000 80 01010000 80---------10100000 -96 (not 160 because the sign bitis 1.)Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-6Ripple Carry Adder Two binary numbers A and B are added from right to left,creating a sum and a carry at the outputs of each full adder foreach bit position.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-7Constructing Larger Adders A 16-bit adder can be made up of a cascade of four 4-bit ripplecarry adders.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-8Full Subtractor Truth table and schematic symbol for a ripple-borrow subtractor:Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-9Ripple-Borrow Subtractor A ripple-borrow subtractor can be composed of a cascade of fullsubtractors. Two binary numbers A and B are subtracted from right to left,creating a difference and a borrow at the outputs of each fullsubtractor for each bit position.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-10Combined Adder/Subtractor A single ripple-carry adder can perform both addition andsubtraction, by forming the two’s complement negative for B whensubtracting. (Note that 1 is added at c0 for two’s complement.)Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-11One’s Complement Addition An example of one’s complement integer addition with an endaround carry: An example of one’s complement integer addition with an endaround carry:Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-12Number Circle (Revisited) Number circle for a three-bit signed one’s complementrepresentation. Notice the two representations for 0.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-13End-Around Carry for Fractions The end-around carry complicates one’s complement addition fornon-integers, and is generally not used for this situation. The issue is that the distance between the two representations of 0is 1.0, whereas the rightmost fraction position is less than 1.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-14Multiplication Example Multiplication of two 4-bit unsigned binary integers produces an 8bit result. Multiplication of two 4-bit signed binary integers produces only a7-bit result (each operand reduces to a sign bit and a 3-bitmagnitude for each operand, producing a sign-bit and a 6-bitresult).Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-15A Serial MultiplierDepartment of Information Technology, Radford UniversityITEC 352 Computer Organization
3-16Chapter 3 - ArithmeticExample of Multiplication Using SerialMultiplierDepartment of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-17Example of Base 2 Division (7 / 3 2)10 with a remainder R of 1. Equivalently, (0111/ 11 10)2 with a remainder R of 1.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-18Serial DividerDepartment of Information Technology, Radford UniversityITEC 352 Computer Organization
3-19Chapter 3 - ArithmeticDivision Example Using Serial DividerDepartment of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-20Multiplication of Signed Integers Sign extension to the target word size is needed for the negativeoperand(s). A target word size of 8 bits is used here for two 4-bit signedoperands, but only a 7-bit target word size is needed for theresult.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-21Carry-Lookahead Addition Carries are represented interms of Gi (generate) and Pi(propagate) expressions.Gi aibi and Pi ai bic0 0c1 G0c2 G1 P1G0c3 G2 P2G1 P2P1G0c4 G3 P3G2 P3P2G1 P3P2P1G0Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-22Carry Lookahead Adder Maximum gatedelay for the carrygeneration is only3. The full addersintroduce two moregate delays. Worstcase path is 5 gatedelays.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-23Floating Point Arithmetic Floating point arithmetic differs from integer arithmetic in thatexponents must be handled as well as the magnitudes of theoperands. The exponents of the operands must be made equal for additionand subtraction. The fractions are then added or subtracted asappropriate, and the result is normalized. Ex: Perform the floating point operation: (.101 23 .111 24)2 Start by adjusting the smaller exponent to be equal to the largerexponent, and adjust the fraction accordingly. Thus we have .101 23 .010 24, losing .001 23 of precision in the process. The resulting sum is (.010 .111) 24 1.001 24 .1001 25, androunding to three significant digits, .100 25, and we have lostanother 0.001 24 in the rounding process.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
3-24Chapter 3 - ArithmeticFloating Point Multiplication/Division Floating point multiplication/division are performed in a mannersimilar to floating point addition/subtraction, except that the sign,exponent, and fraction of the result can be computed separately. Like/unlike signs produce positive/negative results, respectively.Exponent of result is obtained by adding exponents formultiplication, or by subtracting exponents for division. Fractions aremultiplied or divided according to the operation, and thennormalized. Ex: Perform the floating point operation: ( .110 25) / ( .100 24)2 The source operand signs are the same, which means that the resultwill have a positive sign. We subtract exponents for division, and sothe exponent of the result is 5 – 4 1. We divide fractions, producing the result: 110/100 1.10. Putting it all together, the result of dividing ( .110 25) by ( .100 24)produces ( 1.10 21). After normalization, the final result is ( .110 22).Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-25The Booth Algorithm Booth multiplication reduces the number of additions forintermediate results, but can sometimes make it worse as we willsee. Positive and negative numbers treated alike.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-26A Worst Case Booth Example A worst case situation in which the simple Booth algorithmrequires twice as many additions as serial multiplication.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-27Bit-Pair Recoding (Modified BoothAlgorithm)Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-28Coding of Bit PairsDepartment of Information Technology, Radford UniversityITEC 352 Computer Organization
3-29Chapter 3 - nt of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-30Newton’s Iteration for Zero Finding The goal is to find where thefunction f(x) crosses the x axis bystarting with a guess xi and thenusing the error between f(xi ) andzero to refine the guess. A three-bit lookup table forcomputing x0: The division operation a/bis computed as a 1/b.Newton’s iterationprovides a fast method ofcomputing 1/b.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-31Residue Arithmetic Implements carryless arithmetic (thus fast!), but comparisonsare difficult without converting to a weighted position code. Representation of the first twenty decimal integers in the residuenumber system for the given moduli:Department of Information Technology, Radford UniversityITEC 352 Computer Organization
3-32Chapter 3 - ArithmeticExamples of Addition andMultiplication in the Residue NumberSystemDepartment of Information Technology, Radford UniversityITEC 352 Computer Organization
3-33Chapter 3 - Arithmetic16-bit Group Carry Lookahead Adder A16-bit GCLA is composed of four 4-bit CLAs, with additionallogic that generates the carries between the four-bit groups.GG0 G3 P3G2 P3P2G1 P3P2P1G0GP0 P3P2P1P0c4 GG0 GP0c0c8 GG1 GP1c4 GG1 GP1GG0 GP1GP0c0c12 GG2 GP2c8 GG2 GP2GG1 GP2GP1GG0 GP2GP1GP0c0c16 GG3 GP3c12 GG3 GP3GG2 GP3GP2GG1 GP3GP2GP1GG0 GP3GP2GP1GP0c0Department of Information Technology, Radford UniversityITEC 352 Computer Organization
3-34Chapter 3 - Arithmetic16-Bit Group Carry Lookahead Adder Each CLAhas alongest pathof 5 gatedelays. In the GCLL section, GG and GP signals are generated in 3 gatedelays; carry signals are generated in 2 more gate delays, resultingin 5 gate delays to generate the carry out of each GCLA group and10 gates delays on the worst case path (which is s15 – not c16).Department of Information Technology, Radford UniversityITEC 352 Computer Organization
3-35Chapter 3 - ArithmeticHP 9100 Series Desktop Calculator Source: http://www.teleport.com/ dgh/91003q.jpg. Uses binary coded decimal (BCD) arithmetic.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-36Addition Example Using BCD Addition is performed digit by digit (not bit by bit), in 4-bitgroups, from right to left. Example (255 63 318)10:Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-37Subtraction Example Using BCD Subtraction is carried out by adding the ten’s complementnegative of the subtrahend to the minuend. Ten’s complement negative of subtrahend is obtained by adding1 to the nine’s complement negative of the subtrahend. Consider performing the subtraction operation (255 - 63 192)10:Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-38Excess 3 Encoding of BCD Digits Using an excess3 encoding foreach BCD digit,the leftmost bitindicates thesign.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-39A BCD Full Adder Circuit adds twobase 10 digitsrepresented inBCD. Adding 5and 7 (0101 and0111) results in12 (0010 with acarry of 1, andnot 1100, whichis the binaryrepresentation of1210).Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-40Ten’s Complement Subtraction Compare: the traditional signed magnitude approach for addingdecimal numbers vs. the ten’s complement approach, for(21 - 34 -13)10:Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-41BCD Floating Point Representation Consider a base 10 floating point representation with a two digitsigned magnitude exponent and an eight digit signedmagnitude fraction. On a calculator, a sample entry might looklike:-.37100000 10-12 We use a ten’s complement representation for the exponent, anda base 10 signed magnitude representation for the fraction. Aseparate sign bit is maintained for the fraction, so that eachdigit can take on any of the 10 values 0–9 (except for the firstdigit, which cannot be zero). We should also represent theexponent in excess 50 (placing the representation for 0 in themiddle of the exponents, which range from -50 to 49) to makecomparisons easier. The example above now looks like this (see next slide):Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Chapter 3 - Arithmetic3-42BCD Floating Point Arithmetic The example in the previous slide looks like this:Sign bit:1Exponent: 0110 1011Fraction:0110 1010 0100 0011 0011 0011 0011 0011 0011 Note that the representation is still in excess 3 binary form, with atwo digit excess 50 exponent. To add two numbers in this representation, as for a base 2 floatingpoint representation, we start by adjusting the exponent andfraction of the smaller operand until the exponents of bothoperands are the same. After adjusting the smaller fraction, weconvert either or both operands from signed magnitude to ten’scomplement according to whether we are adding or subtracting,and whether the operands are positive or negative, and thenperform the addition or subtraction operation.Department of Information Technology, Radford UniversityITEC 352 Computer Organization
3-43Chapter 3 - Arithmetic16-bit Group Carry Lookahead Adder A16-bit GCLA is composed of four 4-bit CLAs, with additionallogic that generates the carries between the four-bit groups.GG0 G3 P3G2 P3P2G1 P3P2P1G0GP0 P3P2P1P0c4 GG0 GP0c0c8 GG1 GP1c4 GG1 GP1GG0 GP1GP0c0c12 GG2 GP2c8 GG2 GP2GG1 GP2GP1GG0 GP2GP1GP0c0c16 GG3 GP3c12 GG3 GP3GG2 GP3GP2GG1 GP3GP2GP1GG0 GP3GP2GP1GP0c0Department of Information Technology, Radford UniversityITEC 352 Computer Organization
Department of Information Technology, Radford University ITEC 352 Computer Organization Residue Arithmetic Implements carryless arithmetic (thus fast!), but comparisons are difficult without converting to a weighted position code. Representation of the first twenty decimal integers in the residue number system for the given moduli:
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