Introduction To Computer Aided Design (CAD) Dr. Lynn Fuller - Diyhpl
Computer Aided Design ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Introduction to Computer Aided Design (CAD) Dr. Lynn Fuller Webpage: http://www.rit.edu/ lffeee Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041 Email: LFFEEE@rit.edu MicroE Webpage: http://www.microe.rit.edu Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller 6-9-2014 Lec CAD.ppt Page 1
Computer Aided Design OUTLINE The need for Computer Aided Design The CAD Process Levels of Abstraction RIT’s Metal Gate PMOS Process Layout Design Rules Layout Vs Schematic Checking Resistor Design Inverter, NOR, NAND Design RS FF Design Ring Oscillator Maskmaking Design Project References Review Questions Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 2
Computer Aided Design THE NEED FOR CAD With millions of transistors per chip it is impossible to design with no errors without computers to check layout, circuit, process, etc. Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 3
Computer Aided Design COMPARISON OF DESIGN METHODOLOGIES Full Custom Design Direct control of layout and device parameters Longer design time but faster operation more dense Standard Cell Design Easier to implement Limited cell library selections Gate Array or Programmable Logic Array Design Fastest design turn around Reduced Performance Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 4
Computer Aided Design STAGES IN THE CAD PROCESS Problem Specification Behavioral Design Functional and Logic Design Circuit Design Physical Design (Layout) Fabrication Technology CAD (TCAD) Packaging Testing Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 5
Computer Aided Design DESIGN HEIRARCHY - LEVELS OF ABSTRACTION A B C if (A) then X: Y ALU Behavioral Model Block-Functional Model RAM Gate-Level Model Electrical Model (Transistor level Model) Geometric Model Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 6
Computer Aided Design RIT METAL GATE PMOS PROCESS PMOSFET P channel, Metal Oxide Semiconductor Field Effect Transistor The basic unit of distance in a scalable set of design rules is called Lambda, l For the current Metal Gate PMOS process l is ten microns (10 µm) The process has four mask layers, they are: Diffusion Thin Oxide Contact Cuts Metal The following rules are shown as top views (looking down on the mask layers) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 7
Computer Aided Design LAYOUT RULES Slight Overlay Not Fatal Perfect Overlay Misalignment Fatal Layout rules prevent slight misalignment from being fatal. Also, rules help make device performance consistent (minimum width for resistor will make values more consistent) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 8
Computer Aided Design RULES FOR THE DIFFUSION LEVEL Layer 1 - diffusion (green) Rule 1.1 Minimum Width Wd 1 l Rule 1.2 Minimum Spacing Sdd 2 l Wd 1 l (10 µm) Sdd 2 l (20 µm) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller 10 by 10 µm Page 9
Computer Aided Design RULES FOR THE THIN OXIDE LEVEL Layer 2 - Thin Oxide(red) Rule 2.1 Minimum Width Wo 1 l Rule 2.2 Minimum Spacing Soo 1l Wo 1 l (10 µm) Soo 1l (10 µm) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller 10 by 10 µm Page 10
Computer Aided Design RULES FOR THE CONTACT CUT LEVEL Layer 3 - Contact Cut (black) Rule 3.1 Minimum Width Wc 1 l Rule 3.2 Minimum Spacing Scc 1 l Wmin 1 l (10 µm) Smin 1 l (10 µm) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller 10 by 10 µm Page 11
Computer Aided Design RULES FOR THE METAL LEVEL Layer 4 - metal (blue) Rule 4.1 Minimum Width Wm 3 l Rule 4.2 Minimum Spacing Smm 1 l Wm 3 l (30 µm) Smm 1 l (10 µm) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller 10 by 10 µm Page 12
Computer Aided Design RULES FOR THE DIFFUSION, CONTACTS AND METAL LEVELS TOGETHER Layer 1,2,3 Overlay (Extension) Rule 3.3 Minimum Extension of metal beyond contact cut Emc 1 l Emc 1 l (10 µm) Rule 1.3 Minimum Extension of diffusion beyond contact cut Edc 1 l Edc 1 l (10 µm) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller 10 by 10 µm Page 13
Computer Aided Design RESISTOR DESIGN A resistor is a device with a linear relationship between current through and voltage across a device. (Also goes through the origin, that is if I 0 then V 0 ) The value of the resistance for a thin sheet of a material is given by: Schematic symbol I I V V I V/R - I-V characteristics R s L/W Metal where s is the sheet resistance given by the process (for us 100 ohms) SiO2 P-type Diffusion Silicon Cross section Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 14
Computer Aided Design DIFFUSED RESISTOR EXAMPLE ALL LAYERS W L R s L/W Metal SiO2 Diffusion Silicon Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 15
Computer Aided Design DIFFUSED RESISTOR EXAMPLE DIFFUSED LAYER W L R s L/W SiO2 Diffusion Silicon Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 16
Computer Aided Design DIFFUSED RESISTOR EXAMPLE CONTACT CUT LAYER W L R s L/W SiO2 Diffusion Silicon Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 17
Computer Aided Design DIFFUSED RESISTOR EXAMPLE METAL LAYER W L R s L/W Metal SiO2 Diffusion Silicon Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 18
Computer Aided Design LAYOUT VERSUS SCHEMATIC (LVS) CHECKING Desired resistor network 500 W 400 250 W Layout Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 19
Computer Aided Design LVS RESULTS Circuit Extracted from the Layout Layout 500 W 400 250 W Open circuit Missing contact Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 20
Computer Aided Design VARIATIONS ON THE BASIC RESISTOR LAYOUT R s (10 0.5 0.5) 1 2 3 0.5 4 4.5 5.5 6.5 7 8 9 10 0.5 Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 21
Computer Aided Design RESISTOR DESIGN DETAILS Target Value Sheet resistance of layers used variation L/W ratio variation Power Dissipation designed L and W values Other Physical Dimensions Terminal shape SiO2 Bends I I V V I V/R R Metal Diffusion Silicon Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller s L/W Page 22
Computer Aided Design RESISTOR TERMINATION DETAILS Field Mapping 0 squares 0.5 squares Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 23
Computer Aided Design METAL PROBE PAD LOCATIONS 100 µm 100 µm Design Space 500 µm Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 24
Computer Aided Design PMOS FIELD EFFECT TRANSISTORS SYMBOL Drain Gate Substrate Source PMOS FET The current the flows from the source to the drain is controlled by the gate voltage. Source and Drain are interchangeable. PMOS describes the structure as Metal Oxide Silicon with P-type drain and source. The width and length determine the gain of the transistor. Wider transistors give more gain (current flow). Longer transistors give more resistance (less current flow). Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 25
Computer Aided Design TRANSISTOR DESIGN L 2 l (20 µm) L 2l (20 µm) W l (10 µm) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller W 4l (40 µm) Page 26
Computer Aided Design INVERTERS TRUTH TABLE SYMBOL VIN VOUT VOUT VIN 0 1 V V V R R VIN VIN SWITCH VOUT VOUT VOUT VIN 1 0 RESISTOR LOAD Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller PMOSFET ENHANCEMENT LOAD Page 27
Computer Aided Design OTHER INVERTER TYPES - VOUT VS VIN V V 0 0 V 0 0 V 0 V 0 0 -V 0 VO VIN V 0 PMOS ENHANCEMENT LOAD Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller VIN V V V VIN CMOS 0 VO VO SWITCH V -V V V VIN -V VO VIN VO NMOS NMOS ENHANCEMENT DEPLETION LOAD LOAD Page 28
Computer Aided Design PMOS ENHANCEMENT INVERTER GAIN SYMBOL TRUTH TABLE VIN VOUT VOUT VIN 0 1 1 0 V Wu/Lu Inverter Gain Wd/Ld Wu/Lu VOUT VIN Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Wd/Ld PMOSFET ENHANCEMENT LOAD Page 29
Computer Aided Design GAIN OF 2 INVERTER Vdd Wu 2l (20 µm) Lu 4 l (40 µm) (80 µm) Vout Wd 4l (40 µm) Vin Ld 2l (50 µm) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller (20 µm) Gnd Page 30
Computer Aided Design NOR GATES TRUTH TABLE VA VB VOUT SYMBOL VA VB 0 0 1 1 VOUT V V 0 1 0 1 V V 1 0 0 0 R R VOUT VA VOUT VB VB VA SWITCH VOUT VB VA RESISTOR LOAD VOUT PMOS LOAD Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller VB VA CMOS Page 31
Computer Aided Design NOR GATE LAYOUT L 4 l (40 µm) L 2l W 2l (20 µm) (80 µm) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller W 2l (20 µm) (50 µm) Page 32 (20 µm)
Computer Aided Design NAND GATES TRUTH TABLE VA VB VOUT SYMBOL VA VB 0 0 1 1 VOUT V V V 0 1 0 1 1 1 1 0 V R R VOUT VA VOUT VA VB VA VOUT VB VB VOUT VA VB SWITCH RESISTOR LOAD Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller PMOS LOAD CMOS Page 33
Computer Aided Design NAND GATE LAYOUT L 2l (20 µm) L 4 l (40 µm) W 2l (20 µm) W 4l (40 µm) (80 µm) (50 µm) Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 34
Computer Aided Design RS FLIP FLOP R Q RS FLIP FLOP QBAR S R S Q 0 0 1 1 0 1 0 1 Qn-1 1 0 INDETERMINATE D FLIP FLOP Q DATA QBAR CLOCK Q DATA IF CLOCK IS HIGH IF CLOCK IS LOW Q PREVIOUS DATA VALUE Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 35
Computer Aided Design RING OSCILLATOR T 2 td N td is inverter gate delay N is number of stages T is period of oscillation Vout -V T t Vout Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 36
Computer Aided Design MEBES - Manufacturing Electron Beam Exposure System Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 37
Computer Aided Design PHOTOMASK Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 38
Computer Aided Design LABORATORY DESIGN PROJECTS 1- Resistor, L 200 µm, W 20 µm 2- Resistor, L 400 µm, W 40 µm 3- PMOS Transistor L 20 µm, W 100 µm 4- PMOS Transistor L 20 µm, W 200 µm 5- Inverter Gain of 2 6- Inverter Gain of 3 7- Inverter Gain of 4 8- Nine stage ring oscillator (using gain of 3 inverters) 9- RS Flip flop 10 – 2 input NAND 11 – 2 input NOR Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 39
Computer Aided Design EXAMPLE FROM PREVIOUS SHORTCOURSE Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 40
Computer Aided Design GETTING STARTED WITH LAYOUT EDITOR IC Usually the workstation screen will be blank, move the mouse to view a login window. Login: guest-name Password: ******** The screen background will change and your desktop will appear. On the top of the screen click on Applications then System Tools then Terminal. A window will appear that has a Unix prompt inside. Type the command ls at the prompt to see a list of directories and files, the account should be empty. Type ic ENTER , it will take a few seconds, then maximize the IC Station window by clicking the left mouse button on the large square in the upper right corner of the IC Station window. Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 41
Computer Aided Design STARTING A CELL DESIGN On the right hand panel of the IC Station window Layout then click on New to open the create Cell window. Fill in a cell name that was assigned to you. (so I can identify your cells from other students cells). For process browse to or type /tools/ritpub/process/ritpmos . This will select the correct level names, level numbers and colors for the PMOS process. The workspace should change to a black screen with dots. If you move the cursor around you can find different xy cursor locations as displayed at the top-center. On top banner select Setup Preferences Display Rulers/Grid Set the grid as shown 10 10 Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 42 10 1
Computer Aided Design ADDING PAD CELL AND LETTERS From the banner at the top of the page choose Add Instance. A tan pop-up window will appear at the bottom of the page. Type in the following cell name, all lower case, /tools/ritpub/padframes/ritpmos/ritpmos 12 pads and click the left mouse button on the location button. Then position the cursor at the origin 0,0 and click the left mouse button. Click the left mouse button on the cancel button on the tan pop-up box. Press SHIFT and F8 to View All. You should see a white box with ritpmos 12 pads written inside it. Hit space bar and type flatten and select, OK. Press F2 to unselect all. 100 µm 100 µm 500 µm Design Space ABCDEFGH IJKLMNOP QRSTUVWX YZ00.;: */- 1234567890 NPN PNP µM VDD VSS GND SUB V -V Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 43
Computer Aided Design DRAWING BOXES, CIRCLES AND OBJECTS Select easy edit, right click and select Scroll Bars, see the edit commands. DRAW BOXES by click and drag of mouse. Unselect by pressing F2 function key. The Notch command is useful to change the size of a selected box or merge rectangular shapes into more complex objects. The following command will draw a 3000 µm by 3000 µm box with layer 4 color/shading. add shape([[0,0],[3000,3000]],4) Location of lower left corner Location of upper right corner Box Color DRAW CIRCLES by typing set location mode(@arc) return. The following command will draw a 100µm radius circle centered at (0,0) using 300 straight line segments. add shape( get circle([0,0],[100,0],300),3) To reset to rectangles type set location mode(@line) return. SELECT OBJECTS by clicking or by click and drag. Selected objects will appear to have a bright outline. Selected objects can be moved (Move), copied (Copy), deleted (Del) or notched (Notc). To Unselect objects press F2. Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 44
Computer Aided Design ADJUSTING VIEW ZOOM IN OUT: pressing the or - sign on right key pad will zoom in or out. Also pressing shift F8 will zoom so that all objects are in the view area. Select view then area and click and drag a rectangle will zoom so that the objects in the rectangle are in the view area. MOVING VIEW CENTER: pressing the middle mouse button will center the view around the pointer. LASER PRINT OUTPUT: Select File and Print, OK. This gives a laser printer output of entire cell. Select printer prec10, clear width, len, pages, scale by using backspace so nothing is in those boxes. Say OK. PRINT PART OF LAYOUT: first create a panel. Under objects, select add a panel, name it and click on rectangle symbol. Then use the left mouse button to drag a rectangle around the objects you want in the panel to be printed. Then select File and Print and enter panel name, click on print set up, printer is prec10, clear width, len, pages, scale by using backspace so nothing isInstitute in those boxes. Say OK. Rochester of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 45
Computer Aided Design OTHER – ADDING TEXT ADDING TEXT: Add Polygon Text click on layout where you want it located. Select the text box and Edit Change Attributes, change pgtext, change scale to 3.0 ADDING TEXT: From the banner at the top of the page choose Objects add cell. A tan pop-up window will appear at the bottom of the page. Type in the following cell name, all lower case, /tools/ritpub/padframes/ritpmos/ritpmos 12 pads and click the left mouse button on the location button. Then position the cursor to the side of your layout and click the left mouse button. Click the left mouse button on the cancel button on the tan pop-up box. Press SHIFT and F8 to View All. You should see a white box with ritpmos 12 pads written inside it. Type flatten and select, OK. Press F2 to unselect all. Use select and copy to place letters you want. To change letters to a different layer use objects and set layers. Don’t forget to delete the extra letters and numbers you don’t want. Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 46
Computer Aided Design REFERENCES 1. Principles of CMOS VLSI Design, 2nd Ed., Neil H.E.Weste, Kmran Eshraghian, Addison Wesley, 1993. 2. Physical Design Automation of VLSI Systems, Bryan Preas, Michael Lorenzeti, Benjamin/Cummings, 1988. 3. VLSI Engineering, Thomas Dillinger, Prentice Hall, 1988. Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 47
Computer Aided Design HOMEWORK QUESTIONS: CAD 1. Why does the metal have to surround the contact opening by a certain distance? 2. What happens to the value of a resistor as its length is decreased relative to its width? 3. Give three reasons why resistors with the same value might have different layout geometry. 4. How do design rules reflect the process by which the devices are made? Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 48
Computer Aided Design VLSI DESIGN CENTER AT RIT The VLSI Design Center (room 17-2500) consists of AMD Athlon 64 FX-51 Gentoo LINUX workstations, file servers and printers. The workstations are primarily PC’s running LINIX operating system. The PC’s are fast, have lots of RAM and disk space. There are two file servers for user accounts and application software. The two main print devices are a HP laser printer and a HP 36 inch color plotter. There devices are connected through an Ethernet based network. The primary application software, on this network, is the very sophisticated and tightly integrated Mentor Graphics suite of EDA (Electronic Design Automation) tools. Accounts on the computers and access to the room are controlled by the computer engineering department. Currently Charles Gruener for computer accounts and Rick Tolleson for card swipe room access. Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 49
Computer Aided Design BASICS - DESKTOP A graphical interface that provides workspaces, windows, menus, controls, and a front panel to help you organize and manage your software applications. The Front Panel has a tool bar (usually at the bottom of the screen). The tool bar has a K-Gear icon which allows access to editors, graphics programs and the open office software package. The open office package has calculators, drawing programs, equation editor and word processing. You can change the settings for the look and feel of the desktop and the windows that are running. I suggest that you do not go too wild changing things , instead stick to getting the job done. There are four “desk tops” available to run programs on. The toolbar tells you which desktop you are looking at and what is running in each window on the desktop. Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 50
Computer Aided Design BASICS CONTINUED The Mouse: is a three button mouse. The left mouse button is used to select or “click” on something. The right mouse button is used for popup menus. The middle mouse button is typically defined for each application and does not have a common function. For example in the layout software “IC” the middle mouse button shifts the layout so that the clicked location is centered in the workspace. Log Out: click on K Gear icon, select Log Out , Select End Current Session Restore Session: If there is no activity for several minutes the screen will be locked and require the user to type his password to restore the session. Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 51
Computer Aided Design BASIC COMMANDS Command ls cd cd . mv rm pwd mkdir rmdir yppasswd Description list the files and directories in the current directory change directory go up one directory move a file (rename a file) remove a file (delete a file) display path of current directory create a new directory remove a directory change your password It is important to remember that since this is a UNIX operating system, the commands are case sensitive. Rochester Institute of Technology Microelectronic Engineering June 9, 2014 Dr. Lynn Fuller Page 52
Computer Aided Design Page 2 OUTLINE The need for Computer Aided Design The CAD Process Levels of Abstraction RIT's Metal Gate PMOS Process Layout Design Rules Layout Vs Schematic Checking Resistor Design Inverter, NOR, NAND Design RS FF Design Ring Oscillator Maskmaking Design Project References Review Questions
CAD/CAM Computer-Aided Design/Computer-Aided Manufacturing CADD Computer-Aided Design and Drafting CADDS Computer-Aided Design and Drafting System CADE Computer-Aided Design Equipment CADEX Computer Adjunct Data Evaluator-X CADIS Communication Architecture for Distributed Interactive Simulation CADMAT Computer-Aided Design, Manufacture and Test
Aided Machining became an acronym for Computer Aided Manufacturing (CAM). Earlier Computer Aided Manufacturing used to denote computer use in part-programming only. Today it means any non design function of manufacturing that is computer aided. In figure 2, CNC welding machine assisting in casting products. 1.3. Computer Aided Process Planning .
A. Computer-aided welding fixture design workflow and step Various computer-aided fixture design (CAFD) systems have been developed through the years to assist the designer during the various stages of fixture design. A welding fixture is a fixture [7-10]. There are several main stages within the computer-aided welding
The computer aided technologies investigated are; computer aided design, computer aided manufacturing, computer integrated manufacturing, electronic data interchange, electronic point of sale, and internet. Findings from the analysis show that the applications were not equally . to higher value-added specialised textiles and fashion garments .
integrating Computer-Aided Design (CAD) and Computer-Aided Manufacturing (CAM). Consequently, a great deal of research has been devoted for developing Computer-Aided Process Planning (CAPP) systems that can automatically perform the task of process planning. A CAPP system, depending on the
CE 418: Computer Aided Analysis and Design Preface In the field of Structural Engineering, computer aided design and drafting software plays an important role to assist in the modeling, analysis, design and documentation of structures. They improve the quality, efficiency of design through optimization which is time consuming by hand calculation.
Technological Studies Introduction to Computer Aided Manufacturing 1 . CAM is closely related to the computer-aided design (CAD) because the output information about the produc ts from the CAD can a ssist the composing of production program. Tests and productions can start immediately. This simplifies the procedures
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