Advanced MOSFET Modeling For RF IC Design - TechConnect
Advanced MOSFET Modeling for RF IC Design Yuhua Cheng Skyworks Solutions, 5221 California Ave. Irvine, CA 92612 ABSTRACT In this paper, advanced MOSFET modeling for radiofrequency (RF) integrated-circuit (IC) design is discussed. An introduction of the basics of RF modeling of MOSFET is given first. A simple sub-circuit model is then presented with comparisons of the data for both y parameter and fT characteristics. The high frequency (HF) noise and distortion modeling issues are also discussed by showing the validation results against measured data. The developed RF MOSFET model can be the basis of a predictive and statistical modeling approach for RF applications. such as Non-quasi-static (NQS) and induced gate noise are reviewed. 2 AC SMALL SIGNAL MODELING As shown in Fig. 1, a four terminal MOSFET contains many parasitic components. They will influence significantly the device performance at high frequency. G trench P B trench N RDS N- DSB 1 INTRODUCTION The down-scaling of CMOS technology has resulted in a significant improvement of RF performance of MOS devices [1]. Also, CMOS technology offers other advantages such as low power consumption, high integration and lower cost than III-V and SiGe RF technologies. With the fast growth of radio frequency (RF) wireless communications market, RF designers have begun to explore the use of CMOS in RF circuits. Accurate and efficient RF MOSFET models are required. Compared with the MOSFET modeling at low frequency, compact RF models are more complex to develop. Recently, work has been reported to model the RF performance of submicron MOS devices [2-8]. Basically, they are all developed with the subcircuit approach by adding parasitic components to a core intrinsic MOSFET model. They have demonstrated good accuracy up to 10GHz. However, there are still a lot of issues to be studied, and some examples are listed as follows: (1) The added parasitic components should be physics-based and linked to process and geometry information to ensure the scalability and prediction capability of the model; (2) Clear and efficient parameter extraction methodologies should be adopted to enable statistical modeling; (3) Efficient models to account for NQS effects are required; (4) Capability in predicting DC, AC, HF noise and distortion behavior should be ensured; and (5) Better model implementation to improve the simulation efficiency and convergence. In this paper, we discuss some issues that must be properly accounted for in modeling a MOSFET at RF and present some model prediction results by using a sub-circuit MOSFET model as an example. The model are verified by measured small signal AC, HF noise and distortion data over biases and frequency, while some important effects 90 D RG S B Keywords: mosfet modeling, rf modeling, hf mosfet modeling, rf ic design, rf cmos. CGDO RD CGSO RS N- N DDB trench P trench RBDS RSB P-SUB RDB Fig. 1 A MOSFET cross-section with parasitic components. 2.1 Modeling of Gate Resistance The gate resistance consists mainly of the poly-silicon sheet resistance. Signal delay at the gate due to the distributed transmission line effect at high frequency has been studied. A factor of 1/3 or 1/12 is introduced, depending on the layout structures of the gate connection, to account for the distributed RC effects when calculating the gate resistance at RF [9, 10]. This effect will become more severe as the gate width becomes wider and the operation frequency becomes higher. So multi-finger devices are used in the circuit design with narrow gate widths for each finger to reduce the influence of this effect. Complex numerical models for the gate delay have been proposed. However, a simple gate resistance model with the factor of 1/3 or 1/12 for the distributed effect has been found accurate up to ½ fT [8, 10], even though additional bias dependence of gate resistance may need to be included to account for the non-quasi-static effect (NQS) effect. The NQS effect or the distributed RC effect of the channel is another effect that should be accounted for in modeling the HF behavior of a MOSFET. It has been proposed that an additional component is added to the gate resistance to represent the channel distributed RC effect as shown in Fig. 2 [10]. When a MOSFET operates at high frequency, the contribution to the effective gate resistance is not only from the physical gate electrode resistance but also from the distributed channel resistance, which can be "seen" by the signal applied to the gate. Thus, the effective gate resistance NSTI-Nanotech 2004, www.nsti.org, ISBN 0-9728422-8-4 Vol. 2, 2004
Rg consists of two parts: the distributed gate electrode resistance (Rgeltd) and the distributed channel resistance seen from the gate (Rgch), which is a function of biases [10]. This bias dependent Rg model is one of the approaches to account for the NQS effect, as we will discuss again later. Analytical model equations can be found for the substrate resistance components Rsb, Rdsb, and Rdb respectively, which are functions of process and layout parameters such as substrate doping concentration, the space and depth of field (or trench) isolation, etc. YSUB Si (Intrinsic source) Di (Intrinsic drain) CJDB CJSB RBDS RSB B RDB Fig. 3 Proposed equivalent circuit for substrate network. Cjsb and Cjdb are capacitances of source/bulk and drain/bulk junctions [8]. Fig. 2 Illustration of gate electrode resistance Rgeltd, channel resistance Rch , and gate capacitance Cox [10]. 2.2 Modeling of Source/Drain Resistances The source and drain resistances consist of several parts in a MOSFET, such as the via resistance, the salicide resistance, the salicide-to-salicide contact resistance, and the sheet resistance in LDD region, etc. However, the total resistance is usually dominated by the contact and LDD sheet resistances. It has been known that the source/drain resistances are bias dependent. In some compact models such as BSIM3v3 [11, 12], these bias dependencies are included. However, these parasitic resistances are treated only as virtual components in the I-V expressions of BSIM3 to account for the DC voltage drop across these resistances and therefore they are invisible by signal in ac simulation. External components for these series resistances need to be added outside the intrinsic model to accurately describe noise characteristics and the input AC impedance of the device. 2.3 2.4 Modeling of Parasitic Capacitances The parasitic capacitances in a MOSFET can be divided into five components as shown in Fig. 4: 1) the outer fringing capacitance between the polysilicon gate and the source/ drain, CFO; 2) the inner fringing capacitance between the polysilicon gate and the source/drain, CFI; 3) the overlap capacitances between the gate and the heavily doped S/D regions (and the bulk region), CGSO & CGDO (CGBO), which are relatively insensitive to terminal voltages; 4) the overlap capacitances between the gate and lightly doped S/D region, CGSOL & CGDOL, which changes with biases; and 5) the source/drain junction capacitances, CJD & CJS. Most of them have been modeled for digital/analog circuit simulation. It would be preferred that these capacitance models are still applicable to RF simulation. For that purpose, an efficient and correct parameter extraction methodology considering the cases for both low frequency and RF is needed. However, additional parasitic capacitance models may have to be developed if the present models cannot meet the requirements at RF [8]. Modeling of Substrate Resistance The influence of the substrate resistance can be ignored in the compact model for digital and analog circuit simulation at low frequency. However, at high frequencies, the signal at the drain couples to the source and bulk terminals through the source/drain junction capacitance and the substrate resistance. The substrate resistance influences mainly the output characteristics, and can contribute as much as 20% or more of the total output admittance [4]. Recently, work on the modeling of substrate components are reported. Several different substrate networks have been proposed to account for the influence of substrate resistance at RF [2-8]. An equivalent circuit (EC) for the substrate network is proposed to describe the HF substrate-couplingeffect (SCE), as shown in Fig. 3, which has been used in RF modeling with good accuracy up to 10GHz [7, 8]. 2.5 Modeling of NQS Effects Most MOSFET models available in circuit simulators use the quasi-static (QS) approximation. In a QS model, the channel charge is assumed to be a unique function of the instantaneous biases: i.e. the charge has to respond a change in voltages with infinite speed. Thus, the finite charging time of the carriers in the inversion layer is ignored. In reality, the carriers in the channel do not respond to the signal immediately, and thus, the channel charge is not a unique function of the instantaneous terminal voltages (quasi-static) but a function of the history of the voltages (non-quasi-static). This problem may become pronounced in RF applications, where the input signals may have rise or fall times comparable to, or even smaller than, the channel transit time. For long channel devices, the channel transit NSTI-Nanotech 2004, www.nsti.org, ISBN 0-9728422-8-4 Vol. 2, 2004 91
time is roughly inversely proportional to (Vgs-Vth) and proportional to L2 [9]. Because the carriers in these devices cannot follow the changes of the applied signal, the QS models may give inaccurate or anomalous simulation results that cannot be used to guide circuit design. G O O S CFO CGSO n O CGSI CGDI CFI CGBI CFI CGDOL CGSOL D CFO n- CGDO xJ CJS xJ CJD The model has been examined at different bias conditions, and shows satisfactory agreement to experiments. As an example, Fig. 6 shows the comparison of the y-parameter characteristics between measurements and the model for a three finger device with Wf/Lf 12/0.36 at Vg Vd 1.5V. Good match between the model and data shows the simple EC model can work up to 10GHz, which is about half of fT for the given device. Fig.7 gives the comparison of fT-ID characteristics between the model and measurements for different devices. CGBO Csub 1.4x10-2 Solid lines: Model Sy mbols: Measure data 1.0x10-2 Lf 0.36um Wf 12um Nf 2 G Core/Intrinsic MOSFET RG C GSP S RS C GDP Si 4.0x10-3 2.0x10-3 D R SB B C DB Bi R DSB Substrate Network R DB B Fig.5 A subcircuit RF model [8]. 92 -1.0x10-3 Vd Vg 1V -1.5x10-3 Solid lines: Model Sy mbols: Measure data -2.0x10-3 Lf 0.36um Wf 12um Nf 2 -2.5x10-3 Im(Y12) Re(Y 11) -3.0x10-3 0.0 0 2 4 6 8 10 0 Frequenc y (GHz ) 2 4 6 8 10 F re q ue n c y (G Hz ) 8.0x10-3 4.0x10-3 Re(Y 21) 2.0x10-3 Lf 0.36um Wf 12um Nf 2 Vds Vgs 1V Solid lines: Model Sy mbols: Measure data Vbs 0V 0.0 Im(Y 21 ) -2.0x10-3 Solid lines: Model Sy mbols: Measure data Lf 0.36um Wf 12um Nf 2 6.0x10-3 Im(Y 22 ) 4.0x10-3 Vds Vgs 1V Vbs 0V 2.0x10-3 Re(Y 22 ) 0 2 4 6 8 0.0 10 0 2 F requenc y (G Hz ) 4 6 8 10 F re q u e n c y ( G H z ) Fig. 6 Comparison of the Y parameters for a two finger device with W/L 12/0.36 at Vg Vd 1.0V [18]. 30 : Vd 0.5V 25 20 o: Vd 1V 10fx12umx0.36um *: Vd 1.5V Solid lines: Model Symbols: Measured data 15 2fx12umx0.36um 10 5 10fx12umx0.56um -5 10 -4 10 -3 10 Id(A) -2 10 -1 10 0 10 Fig. 7 Comparison of fT-ID characteristics between the model and measurements for different devices [8]. 3 HF NOISE MODELING Different noise sources, associated with terminal resistances, and channel resistance, exist in a MOSFET. In this paper, we will validate the subcircuit model discussed above with the measured HF noise data. Also, we address the issue of induced-gate noise that has become one of the interesting topics in RF modeling. RD Di C SB Re(Y12)&Im(Y12) (A/V) Im(Y 11) 6.0x10-3 A Subcircuit RF Model Based on the above analysis, a complete subcircuit model for RF MOSFETs is given in Fig. 5. The core intrinsic model can be any MOSFET model that is used for analog applications, and here it is BSIM3v3 [11], which has included a bias-dependent overlap capacitance. Re(Y12) -5.0x10-4 8.0x10-3 0 -6 10 2.6 0.0 Vds Vgs 1V Vbs 0V Re(Y22)&Im(Y22) (siemens) The NQS effect can be modeled with different approaches for RF applications: (a) Rg approach in which a bias-dependent gate resistance is introduced to account for the distributed effects from the channel resistance as discussed earlier [10], (b) Ri approach in which a resistance Ri (well-used in modeling a MESFET) is introduced to account for the NQS effect [13], (c) transadmittance approach in which a voltage-control-current-source (VCCS) is connected in parallel to the intrinsic capacitances and transconductances to model the NQS effect [7], and (d) core model approach in which the NQS effect can be modeled in the core intrinsic model [8]. It should be pointed out that all of these approaches would have to deal with a complex implementation. Both Rg and Ri approaches will introduce additional resistance besides the existing physical gate and channel resistance, so the noise characteristics of the model using either Rg or Ri approach need to be examined. Ideally, the NQS effect should be included in the core intrinsic model if it can predict both NQS and noise characteristics without a large penalty in the model implementation and simulation efficiency. 1.2x10-2 fT (GHz) B Fig. 4 Capacitance components in a MOSFET. Re(Y21)&Im(Y21) (Siemens) O Re(Y11)&Im(Y11) (Siemens) P-sub 3.1 Thermal Noise Modeling The HF noise sources in a MOS transistor include the contributions from the terminal resistances at the gate, source and drain, the channel resistance, and the substrate resistances [14]. Fig. 8 shows a complete equivalent noise circuit model for a MOSFET operated at RF. NSTI-Nanotech 2004, www.nsti.org, ISBN 0-9728422-8-4 Vol. 2, 2004
G RG CGD RD D C GS V GS - iG2 C GB i 2g Ri gm V GS RDS id2 RDB i2 S CDB i 2 D conductance, cannot predict the channel thermal noise extracted from measured data. The noise prediction of this subcircuit RF model has much better accuracy at the given bias conditions. 2 iDB R S C SB S/B Fig. 8 Equivalent noise circuit model for a MOSFET [8]. 2 Fig. 9 Comparisons of measured data for minimum noise figure, NFmin, the magnitude of the optimized source reflection coefficient, Gopt, the phase of the optimized source reflection coefficient, *opt, the noise resistance normalized to 50:, rn, with simulations at different bias conditions [8]. 3.5 Nf 10 W 12Pm L 0.36Pm VDS 1V 3.0 2.5 id2 (10-22 Amp2/Hz) With the extracted parameters from the measured data for a 0.25um RF CMOS technology [14], we verify the noise characteristics of the RF model discussed above. The four noise parameters calculated by the correlation matrix technique (CMT) [15] from the simulated noise characteristics are given in Fig. 9 against the measured data for a 0.36um device at different bias conditions. In Fig. 9, the solid lines represent the simulation results of the RF model, and the symbols with solid squares and open circles are the measured data for VGS 1V and VDS 1V and for VGS 2V and VDS 1V, respectively. While the RF model with extracted parameters fits accurately the measured yparameters data as shown in previous section, it can also predict the HF noise characteristics of the device as given in Fig. 9. It has been found that the transconductance and trancapacitances are the key components determining the HF noise characteristics besides the resistive components. For a model to predict well the HF noise characteristics, the accuracy in both DC and AC fittings has to be ensured while the noise model itself is developed with the inclusion of important physical effects such as velocity saturation (VS) and hot carrier effects (HCE). In this RF model, the influence of the VS effect has been included in the core model; however, the contribution of the HCE to thermal noise is not considered even though the influence of impact ionization (and hence HCE) to the channel conductance has been incorporated in the DC model [12]. In Fig. 9, a discrepancy in Rn characteristics between the model and the measured data at VGS 2V has been found. The inaccuracy in either DC or AC models can result in this discrepancy and here we believe this was caused by the inaccurate capacitance prediction of the model at that bias condition since an obvious disagreement in the simulated and measured imaginary part of y12 was found and the contribution from capacitive components to Rn becomes comparable to that from the transconductance at HF. The noise characteristics of several noise models including the subcircuit RF model discussed above are verified with the extracted channel thermal noise with the discussed methodology to explore the physical nature and accuracy of the models. Fig. 10 shows the curves of the channel thermal noise vs. bias current, from the measured data, and simulations of the RF model and several other noise models. It shows that the calculated channel thermal noise based on the equation id 2 8kTGm / 3 , id 2 8kTGds / 3 , and id 8kT (Gm Gds) / 3 , where Gds is the channel Subcircuit RF model Extracted from measured data 8kT*(gm gds)/3 2.0 1.5 1.0 8kT*gm/3 8kT*gds/3 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 IDS (mA) Fig. 10 Power spectral densities of channel thermal noise vs. bias current of a 0.36 Pm n-channel MOSFET. They are extracted from the measured data and calculated from different channel thermal noise models [8]. 3.2 Induced-Gate Noise The concept of the induced-gate noise has been introduced for three decades [15]. But it is still an issue that many researchers are debating the existence of this noise source. At high-frequencies, it is believed that the local channel voltage fluctuations due to thermal noise couple to NSTI-Nanotech 2004, www.nsti.org, ISBN 0-9728422-8-4 Vol. 2, 2004 93
the gate through the oxide capacitance and cause an induced gate noise current to flow [16]. This noise current can be modeled by a noisy current source connected in parallel to the intrinsic gate-to-source capacitance Cgsi. Since the physical origin of the induced gate noise is the same as for the channel thermal noise at the drain, the two noise sources are partially correlated with a correlation factor [7]. As shown in Fig. 11, in a 0.18um technology, the devices with shorter channel length has negligible induced gate noise compared with the channel noise of the same devices shown in Fig. 12 [17]. However, the induced gate noise becomes comparable for devices with longer channel length at higher frequency. Fig. 11 Measured IGN of devices in a 0.18um process [17]. dependences of threshold voltage Vth, mobility and Id (and hence Gm) have to be precisely captured in the extraction. Besides, as for a properly tuned circuit operating at high power, the output voltage swing can be very large. Therefore, the voltage conductance Gout should also be precisely modeled. Furthermore, to be able to predict the distortion at RF, the capacitance and charge components, which in turn determine the transit times of the device, of the model have to be properly extracted. Fig. 13 Modeled (solid lines) and measured (symbols) Pout’s vs drain current Ids for the 10x12x0.36 device at different frequencies when Vds 0.5V and Pin -10dBm; (a) fin 50M, (b) fin 100M, (c) fin 900MHz, and (d) fin 1.8GHz [18]. Fig. 12 Measured channel noise of devices in Fig. 11 [17]. Currently, the induced gate noise and moreover its correlation to the thermal noise at the drain are not implemented completely in compact models yet. A further detailed investigation is needed to understand the inducedgate noise issue and model it correctly. 4 LINEARITY MODELING For a MOSEFT transistor, its distortion is primarily caused by the non-linearity of Id. As a first-order, the output power at the fundamental tune of the device is basically correlated to its transconductance Gm, while the second and the third harmonic tunes are correlated to the first- and second-order derivatives of Gm. Therefore, to ensure the model can predict the distortion behavior, the voltage 94 Fig. 14 Modeled (solid lines) and measured (symbols) Pout’s vs. Ids for the 10x12x0.36 device at different frequencies when Vds 1.0V and Pin 0dBm; (a) fin 50M, (b) fin 100M, (c) fin 900MHz, and (d) fin 1.8GHz [18]. Fig. 13 shows the fitting of the distortion simulations against measurements for a transistor operating at linear region, while Fig. 14 shows the fitting of the model for a transistor operating at saturation region [18]. The poor fitting in the region when Pout 0dBm results from the limited dynamic range of the measurement system. The NSTI-Nanotech 2004, www.nsti.org, ISBN 0-9728422-8-4 Vol. 2, 2004
model can accurately describe the fundamental, second and third harmonics over a wide range of bias conditions and frequencies. The model is generated based on DC and AC measurements without any extra tuning with regards to the large-signal distortion. This demonstrates that a model with good fittings in both DC (both current and the derivatives) and AC (both capacitance and s-parameters) characteristics can predict the distortion behavior of a transistor up to a operating frequency at which the device is still capable of delivering decent power gain. The modeling methodology presented is based on the quasi-static (QS) condition, which assumes that the smallsignal AC characteristics of a device can be derived from its DC/static characteristics. We have demonstrated that such an approach can yield an accurate model for distortion prediction up to a few GHz, although none of the nonquasi-static (NQS) effects are accounted. 5 SUMMARY In this paper, we have discussed some important issues in RF MOSFET modeling. The modeling of parasitic components in MOSFETs is necessary to describe the HF behavior of MOS devices at GHz frequency. An accurate RF MOSFET model with a simple substrate network is presented. The model has been verified by high frequency measurements for AC small signal, noise and distortion. Good model accuracy at different bias conditions has been found for devices with different channel length, width and fingers. The developed RF MOSFET model can be the basis of a predictive and statistical modeling approach for RF applications. The modeling approaches of NQS effects have been analyzed. A RF model including the NQS effect is desirable without introducing complex implementation and simulation time penalty. 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Keywords: mosfet modeling, rf modeling, hf mosfet modeling, rf ic design, rf cmos. 1 INTRODUCTION The down-scaling of CMOS technology has resulted in a significant improvement of RF performance of MOS devices [1]. Also, CMOS technology offers other advantages such as low power consumption, high integration and lower cost than III-V and SiGe RF
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SiC MOSFET is the optimal fit for High Power, High Frequency and High Temperature applications SiC MOSFET. SiC MOSFET Driving Requirements 14 Driving a SiC MOSFET is almost as easy as driving a silicon MOSFET: Just need V GS 20V to get the right R DS(on)
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A MOSFET is a MOS transistor and is essentially consist of a MOS capacitor and two diffused or implanted regions that serve as ohmic contacts to an inversion layer of free charge carriers with the semiconductor-silicon dioxide interface. Figure 5.4 illustrates the 2-D structure of an n-MOSFET. Figure 5.4: A 2-D structure of an n-MOSFET
Understanding power MOSFET data sheet parameters Power MOSFET single-shot and repetitive avalanche ruggedness rating Using RC Thermal models LFPAK MOSFET thermal design – part 1 LFPAK MOSFET thermal design – part 2 Using power MOSFETs in parallel Designing RC snubbers Failure signature of electrical overstress on power MOSFETs Abbreviations
Depletion-mode MOSFET Enhancement-mode MOSFET Both types of MOSFET devices have either an n-channel or a p-channel depending on their added impurities. Note that the MOSFET
a depletion/enhancement MOSFET. The n-channel MOSFET operates in the depletion mode when a negative gate-to-source voltage (V GS) is applied and in the enhancement mode when a positive gate-to-source voltage (V GS) is applied. D-MOSFET are generally operated in the depletion mo
MOSFET models are either p-channel or n-channel models; they are classified according to level, such as Level 1 or Level 50. This chapter covers the design model and simulation aspects of MOSFET models, parameters of each model level, and associated equations. MOSFET diode and MOSFET capacitor model parameters and equations are also described.
