PCA9509 Level Translating I2C-bus/SMBus Repeater
PCA9509Level translating I2C-bus/SMBus repeaterRev. 7 — 4 November 2014Product data sheet1. General descriptionThe PCA9509 is a level translating I2C-bus/SMBus repeater that enables processor lowvoltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O. While retainingall the operating modes and features of the I2C-bus system during the level shifts, it alsopermits extension of the I2C-bus by providing bidirectional buffering for both the data(SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBus maximumcapacitance of 400 pF on the higher voltage side. Port A allows a voltage range from1.35 V to VCC(B) 1.0 V and requires no external pull-up resistors due to the internalcurrent source. Port B allows a voltage range from 3.0 V to 5.5 V and is overvoltagetolerant. Both port A and port B SDA and SCL pins are high-impedance when thePCA9509 is unpowered.For applications where Port A VCC(A) is less than 1.35 V or Port B VCC(B) is less than 3.0 V,use drop-in replacement PCA9509A.The bus port B drivers are compliant with SMBus I/O levels, while port A uses a currentsensing mechanism to detect the input or output LOW signal which prevents bus lock-up.Port A uses a 1 mA current source for pull-up and a 200 pull-down driver. This results ina LOW on the port A accommodating smaller voltage swings. The output pull-down on theport A internal buffer LOW is set for approximately 0.2 V, while the input threshold of theinternal buffer is set about 50 mV lower than that of the output voltage LOW. When theport A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.This prevents a lock-up condition from occurring. The output pull-down on the port Bdrives a hard LOW and the input level is set at 0.3 of SMBus or I2C-bus voltage levelwhich enables port B to connect to any other I2C-bus devices or buffer.The PCA9509 drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above2.5 V. The enable (EN) pin can also be used to turn on and turn off the drivers undersystem control. Caution should be observed to change only the state of the EN pin whenthe bus is idle.2. Features and benefits Bidirectional buffer isolates capacitance and allows 400 pF on port B of the deviceVoltage level translation from port A (1.35 V to VCC(B) 1.0 V) to port B (3.0 V to 5.5 V)Requires no external pull-up resistors on lower voltage port AActive HIGH repeater enable inputOpen-drain inputs/outputsLock-up free operationSupports arbitration and clock stretching across the repeaterAccommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters
PCA9509NXP SemiconductorsLevel translating I2C-bus/SMBus repeater Powered-off high-impedance I2C-bus pins Operating supply voltage range of 1.35 V to VCC(B) 1.0 V on port A, 3.0 V to 5.5 V onport B 5 V tolerant port B SCL, SDA and enable pins 0 Hz to 400 kHz clock frequencyRemark: The maximum system operating frequency may be less than 400 kHzbecause of the delays added by the repeater. ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM perJESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: TSSOP8, SO8, XQFN83. Ordering informationTable 1.Ordering informationType CA9509DPCA9509SO8plastic small outline package; 8 leads; body width 3.9 mmSOT96-1PCA9509DP9509TSSOP8plastic thin shrink small outline package; 8 leads; body width 3 mmSOT505-1PCA9509GMP9X[1]XQFN8plastic, extremely thin quad flat package; no leads; 8 terminals;body 1.6 1.6 0.5 mmSOT902-2[1]‘X’ changes based on date code.3.1 Ordering optionsTable 2.Ordering optionsType numberOrderablepart numberPackagePacking methodPCA9509DPCA9509D,112SO8Standard marking *IC’s tube 2000- DSC bulk packTamb 40 C to 85 CPCA9509D,118SO8Reel 13” Q1/T1*standard mark SMD2500Tamb 40 C to 85 CPCA9509DPPCA9509DP,118TSSOP8Reel 13” Q1/T1*standard mark SMD2500Tamb 40 C to 85 CPCA9509GMPCA9509GM,125XQFN8Reel 7” Q3/T4*standard mark4000Tamb 40 C to 85 CPCA9509Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 7 — 4 November 2014MinimumorderquantityTemperature NXP Semiconductors N.V. 2014. All rights reserved.2 of 24
PCA9509NXP SemiconductorsLevel translating I2C-bus/SMBus repeater4. Functional diagramVCC(B)VCC(A)PCA9509VCC(A)1 mAA1B1VCC(A)1 mAA2B2EN002aac125GNDFig 1.PCA9509Product data sheetFunctional diagram of PCA9509All information provided in this document is subject to legal disclaimers.Rev. 7 — 4 November 2014 NXP Semiconductors N.V. 2014. All rights reserved.3 of 24
PCA9509NXP SemiconductorsLevel translating I2C-bus/SMBus repeater5. Pinning information5.1 ig 2.002aac127Pin configuration for TSSOP8Fig 3.Pin configuration for SO83& *09&& 9&& %WHUPLQDO LQGH[ DUHD% % (1*1' DDD 7UDQVSDUHQW WRS YLHZFig 4.Pin configuration for XQFN85.2 Pin descriptionTable 3.SymbolPinDescriptionVCC(A)1port A power supplyA1[1]2port A (lower voltage side)A2[1]3port A (lower voltage side)GND4ground (0 V)EN5enable input (active HIGH)B2[1]6port B (SMBus/I2C-bus side)B1[1]7port B (SMBus/I2C-bus side)VCC(B)8port B power supply[1]PCA9509Product data sheetPin descriptionPort A and port B can be used for either SCL or SDA.All information provided in this document is subject to legal disclaimers.Rev. 7 — 4 November 2014 NXP Semiconductors N.V. 2014. All rights reserved.4 of 24
PCA9509NXP SemiconductorsLevel translating I2C-bus/SMBus repeater6. Functional descriptionRefer to Figure 1 “Functional diagram of PCA9509”.The PCA9509 enables I2C-bus or SMBus translation down to VCC(A) as low as 1.35 Vwithout degradation of system performance. The PCA9509 contains 2 bidirectionalopen-drain buffers specifically designed to support up-translation/down-translationbetween the low voltage and 3.3 V SMBus or 5 V I2C-bus. The port B I/Os areover-voltage tolerant to 5.5 V even when the device is unpowered.The PCA9509 includes a power-up circuit that keeps the output drivers turned off untilVCC(B) is above 2.5 V and the VCC(A) is above 0.8 V. VCC(B) and VCC(A) can be applied inany sequence at power-up. After power-up and with the EN pin HIGH, a LOW level onport A (below approximately 0.15 V) turns on the corresponding port B driver (either SDAor SCL) and drives port B down to about 0 V. When port A rises above approximately0.15 V, the port B pull-down driver is turned off and the external pull-up resistor pulls thepin HIGH. When port B falls first and goes below 0.3VCC(B), the port A driver is turned onand port A pulls down to 0.2 V (typical). The port B pull-down is not enabled unless theport A voltage goes below VILc. If the port A low voltage goes below VILc, the port Bpull-down driver is enabled until port A rises above approximately 0.15 V (VILc), thenport B, if not externally driven LOW, continues to rise being pulled up by the externalpull-up resistor.Remark: Ground offset between the PCA9509 ground and the ground of devices onport A of the PCA9509 must be avoided.The reason for this cautionary remark is that a CMOS/NMOS open-drain capable ofsinking 3 mA of current at 0.4 V has an output resistance of 133 or less (R E / I). Sucha driver shares enough current with the port A output pull-down of the PCA9509 to beseen as a LOW as long as the ground offset is zero. If the ground offset is greater than0 V, then the driver resistance must be less. Since VILc can be as low as 90 mV at coldtemperatures and the low end of the current distribution, the maximum ground offsetshould not exceed 50 mV.Bus repeaters that use an output offset are not interoperable with the port A of thePCA9509 as their output LOW levels will not be recognized by the PCA9509 as a LOW. Ifthe PCA9509 is placed in an application where the VIL of port A of the PCA9509 does notgo below its VILc, it pulls port B LOW initially when port A input transitions LOW, but theport B returns HIGH, so it does not reproduce the port A input on port B. Such applicationsshould be avoided.Port B is interoperable with all I2C-bus slaves, masters and repeaters.6.1 EnableThe EN pin is active HIGH and allows the user to select when the repeater is active. Thiscan be used to isolate a badly behaved slave on power-up until after the system power-upreset. It should never change state during an I2C-bus operation because disabling duringa bus operation hangs the bus and enabling part way through a bus cycle could confusethe I2C-bus parts being enabled.The enable pin should only change state when the bus and the repeater port are in an idlestate to prevent system failures.PCA9509Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 7 — 4 November 2014 NXP Semiconductors N.V. 2014. All rights reserved.5 of 24
PCA9509NXP SemiconductorsLevel translating I2C-bus/SMBus repeater6.2 I2C-bus systemsAs with the standard I2C-bus system, pull-up resistors are required to provide the logicHIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).The size of these pull-up resistors depends on the system. Each of the port A I/Os has aninternal pull-up current source and does not require the external pull-up resistor. Port B isdesigned to work with Standard-mode and Fast-mode I2C-bus devices in addition toSMBus devices. Standard-mode I2C-bus devices only specify 3 mA output drive; thislimits the termination current to 3 mA in a generic I2C-bus system where Standard-modedevices and multiple masters are possible. Under certain conditions higher terminationcurrents can be used.7. Application design-in informationA typical application is shown in Figure 5. In this example, the CPU is running on a 1.35 VI2C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Masterdevices can be placed on either bus.1.35 V3.3 V10 kΩ10 kΩVCC(A)A1SDAA2SCLMASTERCPUVCC(B)1.35 VPCA9509B1SDAB2SCLSLAVE400 kHz10 kΩENbus AFig 5.bus B002aac128Typical applicationWhen port B of the PCA9509 is pulled LOW by a driver on the I2C-bus, a CMOShysteresis detects the falling edge when it goes below 0.3VCC(B) and causes the internaldriver on port A to turn on, causing port A to pull down to about 0.2 V. When port A of thePCA9509 falls, first a comparator detects the falling edge and causes the internal driveron port B to turn on and pull the port B pin down to ground. In order to illustrate whatwould be seen in a typical application, refer to Figure 6 and Figure 7. If the bus master inFigure 5 were to write to the slave through the PCA9509, waveforms shown in Figure 6would be observed on the B bus. This looks like a normal I2C-bus transmission.On the A bus side of the PCA9509, the clock and data lines are driven by the master andswing nearly to ground. After the eighth clock pulse, the slave replies with an ACK thatcauses a LOW on the A side equal to the VOL of the PCA9509, which the masterrecognizes as a LOW. It is important to note that any arbitration or clock stretching eventsrequire that the LOW level on the A bus side at the input of the PCA9509 (VIL) is belowVILc to be recognized by the PCA9509 and then transmitted to the B bus side.PCA9509Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 7 — 4 November 2014 NXP Semiconductors N.V. 2014. All rights reserved.6 of 24
PCA9509NXP SemiconductorsLevel translating I2C-bus/SMBus repeaterWK FORFN SXOVHDFNQRZOHGJH IURP VODYH RQ % VLGH6&/6' DDD Fig 6.Bus B SMBus/I2C-bus waveformWK FORFN SXOVHDFNQRZOHGJH IURP VODYH RQ % VLGH6&/6' 92/ RI 3& 92/ RI PDVWHUFig 7.DDD Bus A lower voltage waveform8. Limiting valuesTable 4.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).PCA9509Product data sheetSymbolParameterMinMaxUnitVCC(B)supply voltage port BConditions 0.5 6.0VVCC(A)supply voltage port A 0.5 6.0VVI/Ovoltage on an input/output pinport A 0.5 6.0Vport B; enable pin (EN) 0.5 6.0VII/Oinput/output current- 20mAIIinput current- 20mAPtottotal power dissipation-100mW 65 150 C 40 85 C- 125 C-300 CTstgstorage temperatureTambambient temperatureTjjunction temperatureTspsolder point temperatureoperating in free air10 s max.All information provided in this document is subject to legal disclaimers.Rev. 7 — 4 November 2014 NXP Semiconductors N.V. 2014. All rights reserved.7 of 24
PCA9509NXP SemiconductorsLevel translating I2C-bus/SMBus repeater9. Static characteristicsTable 5.Static characteristicsGND 0 V; Tamb 40 C to 85 C; unless otherwise specified.SymbolParameterTyp[1] MaxUnit3.0-5.5V1.35-VCC(B) 1V-VCC(B) 1VConditionsMinPCA9509GMPCA9509D andPCA9509DP1.0[2]SuppliesVCC(B)supply voltage port BVCC(A)supply voltage port AVCC(A)supply voltage port AICC(A)supply current port AICC(B)supply current port Ball port A static HIGH0.250.450.9mAall port A static LOW1.253.05mAall port B static HIGH0.50.91.1mAInput and output of port A (A1 to A2)VIHHIGH-level input voltageport AVILLOW-level input voltageport AVILccontention LOW-level input voltageVIKinput clamping voltageIL 18 mAILIinput leakage currentVI VCC(A)IILLOW-level input currentVOLLOW-level output voltageVOL VILcdifference between LOW-level outputand LOW-level input voltage contentionILOHHIGH-level output leakage currentCioinput/output capacitanceVCC(A) 1.35 V to(VCC(B) 1 V)0.7VCC(A)-VCC(A)V[3] 0.5- 0.3V[3] 0.5 0.15 - 1.5- 0.5VV-- 1 A[4] 1.5 1.0 0.45mA[5]-0.20.3V[6]-50-mV--10 A-67pFVVO 1.35 VInput and output of port B (B1 to B2)VIHHIGH-level input voltageport B0.7VCC(B)-VCC(B)VILLOW-level input voltageport B 0.5- 0.3VCC(B) VVIKinput clamping voltageIL 18 mA 1.5- 0.5ILIinput leakage currentVI 3.6 V 1.0- 1.0 AIILLOW-level input currentVI 0.2 V--10 AVOLLOW-level output voltageIOL 6 mA-0.10.2VILOHHIGH-level output leakage currentVO 3.6 V--10 ACioinput/output capacitance-35pFVILLOW-level input voltage 0.5- 0.1VCC(A) VVIHHIGH-level input voltage0.9VCC(A)-VCC(B)VIIL(EN)LOW-level input current on pin EN 1- 1 AILIinput leakage current 1- 1 ACiinput capacitance-23pFVEnable[1]VI 0.2 V, EN;VCC 3.6 VVI 3.0 V or 0 VTypical values with VCC(A) 1.35 V, VCC(B) 5.0 V.PCA9509Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 7 — 4 November 2014 NXP Semiconductors N.V. 2014. All rights reserved.8 of 24
PCA9509NXP SemiconductorsLevel translating I2C-bus/SMBus repeater[2]If the PCA9509 is not being enabled or disabled, the VCC(A) minimum is 0.95 V with a corresponding decrease in the IIL, which will dropbelow the minimum specification of 450 A at cold temperature (see Figure 8 and Figure 9). This will not significantly change the riseand fall times of the signals on port A since the IIL value represents the current source pull-up current, so a lower current into the samecapacitance results in a slower rise time and a longer transition time in general, however since the lower current is also associated witha lower voltage swing the delay is somewhat compensated. The key point of the graphs is that the current has a temperaturedependence, and the output driver will also have the same temperature dependency so that the output offset of 200 mV on port A isnearly temperature independent. Even though the IIL parameter indicates that at VCC(A) of 0.95 V the PCA9509 can only sink up to400 A instead of 450 A at cold temperature, the output is designed to be somewhat resistive such that under nominal conditions(1.1 V) the current source pull-up sources 1 mA and the output pull-down sinks the 1 mA at 200 mV, so as the current source currentdecreases the output pull-down resistance increases in order to maintain the offset.[3]VIL specification is for the falling edge seen by the port A input. VILc is for the static LOW levels seen by the port A input resulting inport B output staying LOW.[4]The port A current source has a typical value of about 1 mA, but varies with both VCC(A) and VCC(B). Below VCC(A) of about 0.7 V theport A current source current drops to 0 mA. The current source current dropping across the internal pull-down driver resistance ofabout 200 defines the VOL.[5]As long as the chip ground is common with the input ground reference the driver resistance may be as large as 120 . However, groundoffset will rapidly decrease the maximum allowed driver resistance.[6]Guaranteed by design.002aae7330IIL(mA)002aae7340IIL(mA) 0.4(2) 0.4(1)(1)(2)(3) 0.8(4)(3)(4) 0.8 1.2 1.2(5) 1.6 40(5)2585Tamb ( C) 1.6 40Pins under test An pins(1) High limit(2) Maximum(2) Maximum(3) Mean(3) Mean(4) Minimum(4) Minimum(5) Low limit(5) Low limitLOW-level input current as a function oftemperature; VCC(A) 1.0 VPCA9509Product data sheet85Tamb ( C)Pins under test An pins(1) High limitFig 8.25Fig 9.LOW-level input current as a function oftemperature; VCC(A) 0.95 VAll information provided in this document is subject to legal disclaimers.Rev. 7 — 4 November 2014 NXP Semiconductors N.V. 2014. All rights reserved.9 of 24
PCA9509NXP SemiconductorsLevel translating I2C-bus/SMBus repeater10. Dynamic characteristicsTable 6.Dynamic nitVCC(A) 1.35 V; VCC(B) 3.3 VLOW to HIGH propagation delaytPLHport B to port A[1]69109216nstPHLHIGH to LOW propagation delayport B to port A[1]6386140nstTLHLOW to HIGH output transition timeport A[1]142296nsport A[1]58.116nsport A to port B[1] 69 91 139ns91153226ns73122183ns-61-ns152440nsHIGH to LOW output transition timetTHLLOW to HIGH propagation delaytPLHtPLH2LOW to HIGH propagation delay 2port A to port B; measured fromthe 50 % of initial LOW on port A to1.5 V rising on port B[1]tPHLHIGH to LOW propagation delayport A to port B[1]tTLHLOW to HIGH output transition timeport B[1][2]tTHLHIGH to LOW output transition timeport B[1]tsuset-up timeEN HIGH before START condition100--nsthhold timeEN HIGH after STOP condition100--nsVCC(A) 1.9 V; VCC(B) 5.0 VLOW to HIGH propagation delaytPLHHIGH to LOW propagation delaytPHLLOW to HIGH output transition timetTLHport B to port A[1]69105216nsport B to port A[1]6386140nsport A[1]142796nstTHLHIGH to LOW output transition timeport A[1]5835nstPLHLOW to HIGH propagation delayport A to port B[1] 69 89 139nstPLH2LOW to HIGH propagation delay 2port A to port B; measured fromthe 50 % of initial LOW on port A to1.5 V rising on port B[1]91131226nstPHLHIGH to LOW propagation delayport A to port B[1]7399183ns-65-ns153140nsLOW to HIGH output transition timetTLHport B[1][2][1]tTHLHIGH to LOW output transition timeport Btsuset-up timeEN HIGH before START condition100--nsthhold timeEN HIGH after STOP condition100--ns[1]Load capacitance 50 pF; load resistance on port B 1.35 k .[2]Value is determined by RC time constant of bus line.PCA9509Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 7 — 4 November 2014 NXP Semiconductors N.V. 2014. All rights reserved.10 of 24
PCA9509NXP SemiconductorsLevel translating I2C-bus/SMBus repeater10.1 AC .5VCC(A)0.5VCC(A)0.1 VtPHLoutput70 %tPHLtPLH0.5VCC(A) 0.5VCC(A)30 %30 %VCC(A)70 %tTHLoutput70 %VOLtTLHtPLH0.5VCC(B) 0.5VCC(B)30 %30 %tTHLVCC(B)tTLH002aab646Fig 10. Propagation delay and transition times;port B to port A70 %002aab647Fig 11. Propagation delay and transition times;port A to port Binputport A50 % of initial value0.5VCC(B)outputport BtPLH2002aab648Fig 12. Propagation delay from the port A external driver switching off to port B LOW-to-HIGH transition;port A to port B11. Test UTCLRT002aab649RL load resistor; 1.35 k on port BCL load capacitance includes jig and probe capacitance; 50 pFRT termination resistance should be equal to Zo of pulse generatorsFig 13. Test circuit for open-drain outputsPCA
1. General description The PCA9509 is a level translating I2C-bus/SMBus repeater that enables processor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the dataFile Size: 301KB
I2C requires a mere two wires, like asynchronous serial, but those two wires can support up to 1008 peripheral devices.Also, unlike SPI, 2IC can support a multi-controller system, allowing more than one controller [1] to communicate with all peripheral [1] devices on the bus (although the controller devices can't talk to each other over the bus and must take turns using the bus lines).File Size: 356KBPage Count: 12Explore furtherBasics of I2C: The I2C Protocol - TI Trainingtraining.ti.comUnderstanding the I2C Bus - Texas Instrumentswww.ti.comWhat is I2C? Protocol Guide Microcontroller Tutorialswww.teachmemicro.comInter-Integrated Circuit (I2C)www.egr.msu.eduRS-232 INTERFACE - TSCMwww.tscm.comRecommended to you b
I2C Tutorial In this tutorial we will go through I2C Bus & Protocol. I2C was originally invented by Philips(now NXP) in 1982 as bi-directional bus to communicate with multiple devices using just 2 wires/lines. I2C stands for Inter-Integrated Circuit. I2C is sometimes also referred as TWI, which is short for Two Wire Interface, since
Dec 14, 2020 · hardware I2C buses with different clock and data line names. Once you have access to the I2C bus it’s easy to scan the bus to find the address of all devices connected to it. Call the busio.I2C.scan() (https://adafru.it/zcm) function. However before you make calls against the I2C bu
by 4). I2C Multiplexed-Side pins: SDx and SCx: There are 8 sets of SDx and SCx pins, from SD0/SC0 to SD7/SC7. These are the multiplexed pins. Each one is a completely seperate I2C bus set. So you have have 8 I2C devices with identical addresses, as long as they are on one I2C bus each.
User manual Rev. 6 — 4 April 2014 3 of 64 NXP Semiconductors UM10204 I2C-bus specification and user manual 1. Introduction The I2C-bus is a de facto world standard that is now implemented in over 1000 different ICs manufactured by more than 50 companies. Additionally, the versatile I2C-bus is used
Universal Serial Bus Revision 3.2 Specification Universal Serial Bus Revision 3.2 Specification. xxxx and xxxx xxxx and xxxx. Uni-versal Serial Bus Specification Universal Serial Bus Revision 3.2 Specification I2C-Bus Specification I2C-Bus Specification Sys-tem Management Bus Specification
Philips Semiconductors The I2C-bus and how to use it (including specifications) April 1995 5 The I2C-bus is a multi-master bus.This means that more than one device capable of File Size: 209KB
However, the machining of these typically difficult-to-cut materials poses a challenge for conventional manufacturing technologies due to the high tool wear. Abrasive water jet (AWJ) machining is a promising alternative manufacturing technology for machining difficult-to-cut materials,
