CMOS VLSI Design - Pearson
CMOS VLSI DesignA Circuits and Systems PerspectiveFourth Edition
CMOS VLSI DesignA Circuits and Systems PerspectiveFourth EditionNeil H. E. WesteMacquarie University andThe University of AdelaideDavid Money HarrisHar vey Mudd CollegeAddison-WesleyBoston Columbus Indianapolis New York San Francisco Upper Saddle RiverAmsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal TorontoDelhi Mexico City Sao Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo
Editor in Chief: Michael HirschAcquisitions Editor: Matt GoldsteinEditorial Assistant: Chelsea BellManaging Editor: Jeffrey HolcombSenior Production Project Manager: Marilyn LloydMedia Producer: Katelyn BollerDirector of Marketing: Margaret WaplesMarketing Coordinator: Kathryn FerrantiSenior Manufacturing Buyer: Carol MelvilleSenior Media Buyer: Ginny MichaudText Designer: Susan RaymondArt Director, Cover: Linda KnowlesCover Designer: Joyce Cosentino Wells/J Wells DesignCover Image: Cover photograph courtesy of Nick Knupffer—Intel Corporation.Copyright 2009 Intel Corporation. All rights reserved.Full Service Vendor: Gillian Hall/The Aardvark Group Publishing ServiceCopyeditor: Kathleen Cantwell, C4 TechnologiesProofreader: Holly McLean-AldisIndexer: Jack LewisPrinter/Binder: Edwards BrothersCover Printer: Lehigh-Phoenix Color/HagerstownCredits and acknowledgments borrowed from other sources and reproduced with permission in thistextbook appear on appropriate page within text or on page 838.The interior of this book was set in Adobe Caslon and Trade Gothic.Copyright 2011, 2005, 1993, 1985 Pearson Education, Inc., publishing as Addison-Wesley. Allrights reserved. Manufactured in the United States of America. This publication is protected byCopyright, and permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise. To obtain permission(s) to use material from this work,please submit a written request to Pearson Education, Inc., Permissions Department, 501 BoylstonStreet, Suite 900, Boston, Massachusetts 02116.Many of the designations by manufacturers and sellers to distinguish their products are claimed astrademarks. Where those designations appear in this book, and the publisher was aware of a trademark claim, the designations have been printed in initial caps or all caps.Cataloging-in-Publication Data ison file with the Library of Congress.Addison-Wesleyis an imprint of10 9 8 7 6 5 4 3 2 1—EB—14 13 12 11 10ISBN 10: 0-321-54774-8ISBN 13: 978-0-321-54774-3
To Avril, Melissa, Tamara, Nicky, Jocelyn,Makayla, Emily, Danika, Dan and SimonN. W.To Jennifer, Samuel, and AbrahamD. M. H.
ContentsPrefacexxvChapter 1 Introduction1.1A Brief History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2Preview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3MOS Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.4CMOS Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.4.1The Inverter 91.4.2The NAND Gate 91.4.3CMOS Logic Gates 91.4.4The NOR Gate 111.4.5Compound Gates 111.4.6Pass Transistors and Transmission Gates 121.4.7Tristates 141.4.8Multiplexers 151.4.9Sequential Circuits 161.5CMOS Fabrication and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.5.1Inverter Cross-Section 191.5.2Fabrication Process 201.5.3Layout Design Rules 241.5.4Gate Layouts 271.5.5Stick Diagrams 281.6Design Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291.6.1Design Abstractions 301.6.2Structured Design 311.6.3Behavioral, Structural, and Physical Domains 311.7Example: A Simple MIPS Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . 331.7.1MIPS Architecture 331.7.2Multicycle MIPS Microarchitectures 341.8Logic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381.8.1Top-Level Interfaces 381.8.2Block Diagrams 381.8.3Hierarchy 401.8.4Hardware Description Languages 401.9Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42vii
viiiContents1.10 Physical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451.10.1 Floorplanning 451.10.2 Standard Cells 481.10.3 Pitch Matching 501.10.4 Slice Plans 501.10.5 Arrays 511.10.6 Area Estimation 511.11 Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531.12 Fabrication, Packaging, and Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Summary and a Look AheadExercises5557Chapter 2 MOS Transistor Theory2.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612.2Long-Channel I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642.3C-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682.3.1Simple MOS Capacitance Models 682.3.2Detailed MOS Gate Capacitance Model 702.3.3Detailed MOS Diffusion Capacitance Model 722.4Nonideal I-V Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742.4.1Mobility Degradation and Velocity Saturation 752.4.2Channel Length Modulation 782.4.3Threshold Voltage Effects 792.4.4Leakage 802.4.5Temperature Dependence 852.4.6Geometry Dependence 862.4.7Summary 862.5DC Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872.5.1Static CMOS Inverter DC Characteristics 882.5.2Beta Ratio Effects 902.5.3Noise Margin 912.5.4Pass Transistor DC Characteristics 922.6Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Summary94Exercises95Chapter 3 CMOS Processing Technology3.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993.2CMOS Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003.2.1Wafer Formation 1003.2.2Photolithography 101
ell and Channel Formation 103Silicon Dioxide (SiO2) 105Isolation 106Gate Oxide 107Gate and Source/Drain Formations 108Contacts and Metallization 110Passivation 112Metrology 1123.3Layout Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133.3.1Design Rule Background 1133.3.2Scribe Line and Other Structures 1163.3.3MOSIS Scalable CMOS Design Rules 1173.3.4Micron Design Rules 1183.4CMOS Process Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193.4.1Transistors 1193.4.2Interconnect 1223.4.3Circuit Elements 1243.4.4Beyond Conventional CMOS 1293.5Technology-Related CAD Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303.5.1Design Rule Checking (DRC) 1313.5.2Circuit Extraction 1323.6Manufacturing Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333.6.1Antenna Rules 1333.6.2Layer Density Rules 1343.6.3Resolution Enhancement Rules 1343.6.4Metal Slotting Rules 1353.6.5Yield Enhancement Guidelines 1353.7Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363.8Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Summary 139Exercises 139Chapter 4 Delay4.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414.1.1Definitions 1414.1.2Timing Optimization 1424.2Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434.3RC Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464.3.1Effective Resistance 1464.3.2Gate and Diffusion Capacitance 1474.3.3Equivalent RC Circuits 1474.3.4Transient Response 1484.3.5Elmore Delay 150ix
xContents4.3.64.3.7Layout Dependence of Capacitance 153Determining Effective Resistance 1544.4Linear Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554.4.1Logical Effort 1564.4.2Parasitic Delay 1564.4.3Delay in a Logic Gate 1584.4.4Drive 1594.4.5Extracting Logical Effort from Datasheets 1594.4.6Limitations to the Linear Delay Model 1604.5Logical Effort of Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634.5.1Delay in Multistage Logic Networks 1634.5.2Choosing the Best Number of Stages 1664.5.3Example 1684.5.4Summary and Observations 1694.5.5Limitations of Logical Effort 1714.5.6Iterative Solutions for Sizing 1714.6Timing Analysis Delay Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734.6.1Slope-Based Linear Model 1734.6.2Nonlinear Delay Model 1744.6.3Current Source Model 1744.7Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744.8Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175Summary176Exercises176Chapter 5 Power5.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815.1.1Definitions 1825.1.2Examples 1825.1.3Sources of Power Dissipation 1845.2Dynamic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855.2.1Activity Factor 1865.2.2Capacitance 1885.2.3Voltage 1905.2.4Frequency 1925.2.5Short-Circuit Current 1935.2.6Resonant Circuits 1935.3Static Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1945.3.1Static Power Sources 1945.3.2Power Gating 1975.3.3Multiple Threshold Voltages and Oxide Thicknesses 199
Contents5.3.45.3.5Variable Threshold VoltagesInput Vector Control 2001995.4Energy-Delay Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2005.4.1Minimum Energy 2005.4.2Minimum Energy-Delay Product 2035.4.3Minimum Energy Under a Delay Constraint 2035.5Low Power Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2045.5.1Microarchitecture 2045.5.2Parallelism and Pipelining 2045.5.3Power Management Modes 2055.6Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2065.7Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Summary209Exercises209Chapter 6 Interconnect6.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2116.1.1Wire Geometry 2116.1.2Example: Intel Metal Stacks 2126.2Interconnect Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2136.2.1Resistance 2146.2.2Capacitance 2156.2.3Inductance 2186.2.4Skin Effect 2196.2.5Temperature Dependence 2206.3Interconnect Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2206.3.1Delay 2206.3.2Energy 2226.3.3Crosstalk 2226.3.4Inductive Effects 2246.3.5An Aside on Effective Resistance and Elmore Delay 2276.4Interconnect Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2296.4.1Width, Spacing, and Layer 2296.4.2Repeaters 2306.4.3Crosstalk Control 2326.4.4Low-Swing Signaling 2346.4.5Regenerators 2366.5Logical Effort with Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366.6Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Summary238Exercises238xi
xiiContentsChapter 7 Robustness7.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2417.2Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2417.2.1Supply Voltage 2427.2.2Temperature 2427.2.3Process Variation 2437.2.4Design Corners 2447.3Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2467.3.1Reliability Terminology 2467.3.2Oxide Wearout 2477.3.3Interconnect Wearout 2497.3.4Soft Errors 2517.3.5Overvoltage Failure 2527.3.6Latchup 2537.4Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2547.4.1Transistor Scaling 2557.4.2Interconnect Scaling 2577.4.3International Technology Roadmap for Semiconductors 2587.4.4Impacts on Design 2597.5Statistical Analysis of Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2637.5.1Properties of Random Variables 2637.5.2Variation Sources 2667.5.3Variation Impacts 2697.6Variation-Tolerant Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2747.6.1Adaptive Control 2757.6.2Fault Tolerance 2757.7Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2777.8Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278Summary284Exercises284Chapter 8 Circuit Simulation8.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2878.2A SPICE Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2888.2.1Sources and Passive Components 2888.2.2Transistor DC Analysis 2928.2.3Inverter Transient Analysis 2928.2.4Subcircuits and Measurement 2948.2.5Optimization 2968.2.6Other HSPICE Commands 298
Contents8.3Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2988.3.1Level 1 Models 2998.3.2Level 2 and 3 Models 3008.3.3BSIM Models 3008.3.4Diffusion Capacitance Models 3008.3.5Design Corners 3028.4Device Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3038.4.1I-V Characteristics 3038.4.2Threshold Voltage 3068.4.3Gate Capacitance 3088.4.4Parasitic Capacitance 3088.4.5Effective Resistance 3108.4.6Comparison of Processes 3118.4.7Process and Environmental Sensitivity 3138.5Circuit Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3138.5.1Path Simulations 3138.5.2DC Transfer Characteristics 3158.5.3Logical Effort 3158.5.4Power and Energy 3188.5.5Simulating Mismatches 3198.5.6Monte Carlo Simulation 3198.6Interconnect Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3198.7Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322Summary324Exercises324Chapter 9 Combinational Circuit Design9.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3279.2Circuit Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3289.2.1Static CMOS 3299.2.2Ratioed Circuits 3349.2.3Cascode Voltage Switch Logic 3399.2.4Dynamic Circuits 3399.2.5Pass-Transistor Circuits 3499.3Circuit Pitfalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3549.3.1Threshold Drops 3559.3.2Ratio Failures 3559.3.3Leakage 3569.3.4Charge Sharing 3569.3.5Power Supply Noise 3569.3.6Hot Spots 357xiii
inority Carrier Injection 357Back-Gate Coupling 358Diffusion Input Noise Sensitivity 358Process Sensitivity 358Example: Domino Noise Budgets 3599.4More Circuit Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3609.5Silicon-On-Insulator Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3609.5.1Floating Body Voltage 3619.5.2SOI Advantages 3629.5.3SOI Disadvantages 3629.5.4Implications for Circuit Styles 3639.5.5Summary 3649.6Subthreshold Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3649.6.1Sizing 3659.6.2Gate Selection 3659.7Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3669.8Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367Summary369Exercises370Chapter 10 Sequential Circuit Design10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37510.2 Sequencing Static Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37610.2.1 Sequencing Methods 37610.2.2 Max-Delay Constraints 37910.2.3 Min-Delay Constraints 38310.2.4 Time Borrowing 38610.2.5 Clock Skew 38910.3 Circuit Design of Latches and Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . 39110.3.1 Conventional CMOS Latches 39210.3.2 Conventional CMOS Flip-Flops 39310.3.3 Pulsed Latches 39510.3.4 Resettable Latches and Flip-Flops 39610.3.5 Enabled Latches and Flip-Flops 39710.3.6 Incorporating Logic into Latches 39810.3.7 Klass Semidynamic Flip-Flop (SDFF) 39910.3.8 Differential Flip-Flops 39910.3.9 Dual Edge-Triggered Flip-Flops 40010.3.10 Radiation-Hardened Flip-Flops 40110.3.11 True Single-Phase-Clock (TSPC) Latches and Flip-Flops 402WEBENHANCED10.4 Static Sequencing Element Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 40210.4.1 Choice of Elements 40310.4.2 Characterizing Sequencing Element Delays 405
.4.6State Retention Registers 408Level-Converter Flip-Flops 408Design Margin and Adaptive Sequential ElementsTwo-Phase Timing Types 41140910.5 Sequencing Dynamic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41110.6 Synchronizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41110.6.1 Metastability 41210.6.2 A Simple Synchronizer 41510.6.3 Communicating Between Asynchronous Clock Domains 41610.6.4 Common Synchronizer Mistakes 41710.6.5 Arbiters 41910.6.6 Degrees of Synchrony 41910.7 Wave Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42010.8 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422WEBENHANCED10.9 Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies . . . . . 423Summary423Exercises425Chapter 11 Datapath Subsystems11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42911.2 Addition/Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42911.2.1 Single-Bit Addition 43011.2.2 Carry-Propagate Addition 43411.2.3 Subtraction 45811.2.4 Multiple-Input Addition 45811.2.5 Flagged Prefix Adders 45911.3 One/Zero Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46111.4 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46211.4.1 Magnitude Comparator 46211.4.2 Equality Comparator 46211.4.3 K A B Comparator 46311.5 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS VLSI Design A Circuits and Systems Perspective. Fourth Edition Neil H. E. Weste Macquarie University and The University of Adelaide David Money Harris Harvey Mudd College CMOS VLSI Design A Circuits and Systems Perspective Addison-Wesley Boston Columb
Circuits-A CMOS VLSI Design Slide 2 Outline: Circuits Lecture A – Physics 101 – Semiconductors for Dummies – CMOS Transistors for logic designers Lecture B – NMOS Logic – CMOS Inverter and NAND Gate Operation – CMOS Gate Design – Adders – Multipliers Lecture C – P
CSCE 5730: Digital CMOS VLSI Design 29 IC Categories Functions Analog ICs Amplifiers Filters Digital ICs Boolean Gates Encoders/Decoders Multiplexers / Demultiplexers Flip-flops Counters . Digital IC Design Flow CSCE 5730: Digital CMOS VLSI Design 36. Technology Growth and Moore's Law CSCE 5730: Digital CMOS VLSI Design 37.
VL2114 RF VLSI Design 3 0 0 3 VL2115 High Speed VLSI 3 0 0 3 VL2116 Magneto-electronics 3 0 0 3 VL2117 VLSI interconnects and its design techniques 3 0 0 3 VL2118 Digital HDL Design and Verification 3 0 0 3 VL2119* Computational Aspects of VLSI 3 0 0 3 VL2120* Computational Intelligence 3 0 0 3
Module #3 CMOS Fabrication Agenda 1. CMOS Fabrication - Yield - Process Steps for MOS transistors - Inverter Example - Design Rules - Passive Components - Packaging Announcements 1. Read Chapter 2 Module #3 ECOM 5335 VLSI Design Page 2 CMOS Fabrication CMOS Fabrication - We have talked about
Rochester Institute of Technology Microelectronic Engineering CMOS VLSI DESIGN Page 8 RIT SUBµ CMOS RIT Subµ CMOS 150 mm wafers Nsub 1E15 cm-3 Nn-well 3E16 cm-3 Xj 2.5 µm Np-well 1E16 cm-3 Xj 3.0 µm LOCOS Field Ox 6000 Å Xox 150 Å Lmin 1.0 µm LDD/Side Wall Spacers Vdd 5
Principles of VLSI Design Introduction CMPE 315 Principles of VLSI Design Instructor Chintan Patel (Contact using email: cpatel2@cs.umbc.edu). Text CMOS VLSI Design: A Circuits and Systems Perspective, Third Edition. by Neil H.E. Weste and David Harris. ISBN: 0-321-14901-7, Addison Wesl
VLSI Design 2 Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.
Key words: Organization, Classical theory, Taylor, Fayol and Weber. Introduction The society we belong is an organizational society. Modern society has retained high morale value of rationality, efficiency and effectiveness in contrast to previous society (Etzioni, 1964). There are relationships between individuals and organizations. It is
