Computer Organization And Architecture Instruction Set
Computer Organization and ArchitectureInstruction Set DesignChapter 11Instruction Sets: Addressing Modes andFormats One goal of instruction set design is tominimize instruction length Another goal (in CISC design) is to maximizeflexibility Many instructions were designed withcompilers in mind Determining how operands are addressedmodes is a key component of instruction setdesignAddressing ModesImmediate Addressing Different types of addresses involve tradeoffsbetween instruction length, addressingflexibility and complexity of addresscalculation Common Addressing Modes Operand value is part of instruction Operand is one address field e.g. ADD eax,5— Immediate— Direct— Indirect— Register— Register Indirect— Displacement (Indexed)— Implied (Stack, and a few others)— Add 5 to contents of accumulator No memory reference to fetch data Fast Can have limited range in machines with fixedlength instructionsImmediate Addressing and Small OperandsDirect Addressing A great many immediate mode instructions usesmall operands (8 bits) In 32 or 64 bit machines with variable lengthinstructions space is wasted if immediateoperands are required to be the same as theregister size Some instruction formats include a bit thatallows small operands to be used in immediateinstructions ALU will zero-extend or sign-extend theoperand to the register size Address field contains address of operand Effective address (EA) address field (A) e.g. add ax, count or add ax,[10FC]— Look in memory at address for operand Single memory reference to access data No additional calculations to work outeffective address1
Direct Addressing in x86 architectureMemory-Indirect Addressing Intel x86 is a segmented architecture, so asegment register is involved in EA computationeven if using the flat memory model Example Intel direct address instructions Memory cell pointed to by address fieldcontains the address of (pointer to) theoperand EA (A)mov [0344], bxadd [00C018A0], edxpushd [09820014]inc byte ptr [45AA]cmp es:[0342], 1; ds:[bx]; note add to mem; note mem to mem; compute in mem; segment override— Look in A, find address (A) and look there foroperandX86 Memory Indirect AddressingCascaded Indirect Addressing Memory indirect addressing is very restrictedin x86 architecture Transfer of control instructions only: CALL andJMP Examples: Rarely usedfunc1 dw ?func2 dw ? CALL [func1]OrJMP [func2]— e.g. EA (((A))) Implemented by using one bit of full-wordaddress as an indirect flag— Allows unlimited depth of indirection Requires multiple memory accesses to findoperand; hence slower than any other type ofaddressingRegister Addressing (1)Register Addressing (2) Operand(s) is(are) registers EA R Register R is EA (not contents of R) There are a limited number of registers — Therefore a very small address field is needed— Shorter instructions— Faster instruction fetch— X86: 3 bits used to specify one of 8 registersNo memory access needed to fetch EAVery fast executionVery limited address spaceMultiple registers can help performance— Requires good assembly programming or compilerwriting— Note: in C you can specify register variablesregister int a;— This is only advisory to the compiler— No guarantees2
Register Indirect AddressingRegister Indirect Addressing Similar to memory-indirect addressing; muchmore common EA (R) Operand is in memory cell pointed to bycontents of register R Large address space (2n) One fewer memory access than indirectaddressingDisplacement AddressingTypes of Displacement Addressing EA A (R) Combines register indirect addressing withdirect addressing Address field hold two values Relative Addressing Base-register addressing Indexing— A base value— R register that holds displacement or vice versaRelative AddressingBase-Register Addressing Sometimes called PC-relative addressing EA A (PC) Address field A treated as 2’s complementinteger to allow backward references Fetch operand from PC A Can be very efficient because of locality ofreference & cache usage — But in large programs code and data may be widelyseparated in memoryA holds displacementR holds pointer to base addressR may be explicit or implicite.g. segment registers in 80x86 are baseregisters and are involved in all EAcomputations x86 processors have a wide variety of baseaddressing formatsmov eax,[edi 4 * ecx]sub [bx si-12],23
Indexed AddressingX86 Indexed Addressing Autoincrement only with string instructions:A baseR displacementEA A RGood for accessing arraysExample : rep movsdSemanticses:[edi] - ds:[esi]esi - esi /- 4 ;DF determines or edi - edi /- 4ecx - ecx - 1— EA A R— R Iterative access to sequential memorylocations is very common Some architectures provide auto-increment orauto-decrement Preindex EA A (R ) Postindex EA A ( R) Combine register pairs with optionaldisplacementmov eax,[edi 4 * ecx]sub [bx si-12],2Stack AddressingPentium Addressing Modes Operand is (implicitly) on top of stack e.g. Virtual or effective address is offset into segment— PUSH— POP X87 is a stack machine so it has instructionssuch asFADDP; st(1) - st(1) st(0); pop stack; result left in st(0)FIMUL qword ptr [bx]; st(0) - st(0) * 64 integer pointed to; by bxPentium EA Calculation— Starting address plus offset gives linear address— This goes through page translation if paging enabled 12 addressing modes ter operandDisplacementBaseBase with displacementScaled index with displacementBase with index and displacementBase scaled index with displacementRelativeARM Addressing Modes A typical RISC characteristic is a small andsimple set of addressing modes ARM departs somewhat from this conventionwith a relatively rich set of addressing modes But Load and Store are the only instructionsthat can reference memory— Always indirect through a base register plus offset Three alternatives— Offset— Preindex— Postindex4
Offset AddressingPreindex Addressing Offset added or subtracted from value in baseregister Example: store byte, base register is R1 anddisplacement is decimal 12. This is the addresswhere the byte from r0 is stored Memory address formed same way as offsetaddressing, but the memory address is writtenback to the base register after adding orsubtracting the displacement With preindexing the writeback occurs beforethe store to memoryPostindex AddressingIndexed Addressing Operands Like preindex addressing but the writeback ofthe effective address occurs after the store Previous examples had immediate values but theoffset or displacement can also be in anotherregister If a register is used then addresses can be scaled The value in the offset register is scaled by oneof the shift operators— Logical Shift Left / Right— Arithmetic Shift Right— Rotate Right— Rotate Right Extended Amount of shift is an immediate operand in theinstructionArithmetic and Logical InstructionsBranch Instructions Use register and immediate operands only For register addressing one of the registeroperands can be scaled by one of the five shiftoperations mentioned previously Only form of addressing is immediate Branch instruction contains a 24-bit immediatevalue For address calculation this value is shiftedleft by 2 bits so the address is on a wordboundary This provides a range of 26 bits so we havebackwards or forwards branches of 32MB (225)5
Load/Store MultipleInstruction Formats Load/Store multiple loads or stores a subset ofgeneral purpose registers (possibly all) from/tomemory List of registers is specified in a 16-bit field inthe instruction (one bit/register) Memory addresses are sequential; low addresshas lowest numbered register Found addressing modes: Defines the layout of bits in an instruction Includes opcode and includes implicit orexplicit operand(s) Usually there are several instruction formats inan instruction set Huge variety of instruction formats have beendesigned; they vary widely from processor toprocessor— Increment/decrement before/after— Base reg specifies a main memory address— Inc/Dec starts before/after the first memory access— Useful for block loads/stores; stack operations andprocedure or function entry and exit sequencesInstruction LengthInstruction format trade-offs The most basic issue Affected by and affects: — Memory size— Memory organization— Bus structure— CPU complexity— CPU speedLarge instruction set small programsSmall instruction set large programsLarge memory longer instructionsFixed length instructions same size or multiple of buswidth fast fetch Variable length instructions may need extra bus cycles Processor may execute faster than fetch— Use cache memory or use shorter instructions Trade off between a powerful instructionrepertoire and saving space with shorterinstructions Note complex relationship between word size,character size, instruction size and bus transfer widthAllocation of BitsAllocation of bits Determines several important factors Number of addressing modes — In almost all modern computers these are all multiples of 8and related to each other by powers of 2— Implicit operands don’t need bits— X86 uses 2-bit mode field to specify interpretation of 3-bitoperand fields Number of operands— 3 operand formats are rare— For two operand instructions we can use one or two operandmode mode indicators— X86 uses only one 2-bit indicatorNumber of register sets——— Address range—— Register versus memory————Tradeoff between # of registers and program sizeStudies suggest optimal number of between 8 and 32Most newer architectures have 32 or moreX86 architecture allows some computation in memoryRISC architectures tend to have larger sets of uniform registersSmall register sets require fewer opcode bitsSpecialized register sets can reduce opcode bits further byimplicit reference (address vs. data registers)Large address space requires large instructions for directaddressingMany architectures have some restricted or short forms ofdisplacement addressing– Ex: x86 short jumps and loops, PowerPC 16-bit displacementaddressingAddress granularity——Size of object addressed.Typically 8,16, 32 and 64 instruction variants6
PDP-8PDP-8 Memory References Very simple machine and instruction setHas one register (the Accumulator)12-bit instructions operate on 12-bit wordsVery efficient implementation – 35 operationsalong with indirect addressing, displacementaddressing and indexing in 12 bits The lack of registers is handled by using part ofthe first physical page of memory as a registerfile Main memory consisted of 4096 words dividedinto 32 128-word pages Instructions with a memory reference had a 7-bitaddress plus two modifier bits (leaving 3 bits foropcode!)Instruction FormatsPDP-8 Instruction Format— Z/C bit Page 0 or current page (with this instruction)— D/I bit Direct or Indirect addressing In addition the first 8 words of page 0 aretreated as autoindex “registers” Note that memory-indirect addressing was usedbecause processor had no index registers A 3-bit opcode and three types of instructions— For opcodes 0 – 5 (6 basic instructions) we have singleaddress mem ref with Z/C I/D bits Opcode 6 is I/O with 6 device-select bits and 3operation bits Opcode 7 defines a register reference ormicroinstruction— Three groups, where bits are used to specify operation(e.g., clear accumulator)— Forerunner of modern microprogrammingPDP-10PDP-10 Instruction Format Designed to be a large scale time-sharingmachine Emphasis on ease of programming even at theexpense of additional hardware Design considerations 1. Orthogonality between opcodes and EA computations(EA computed in the same way regardless of opcode)2. Completeness: each data type (int, fixed point, real)has a complete and identical set of operations3. Direct Addressing in place of base displacementaddressing 36 bit word and instruction lengthSingle fixed instruction format9-bit opcode allows 512 operations; 365 were used2 address instructions-one operand is GP register (16regs 4 bits)2nd operand 18-bit address fieldIndirection available for mem sizes 2 18Provides indexing for iterative processing18 bit address field makes immediate addressingattractive7
Fixed and Variable Length InstructionsPDP 11 Fixed length instructions can provide compactness andefficiency at the cost of flexibility (PDP-8) or can utilizespace inefficiently (PDP-10) Variable length instructions can provide variety andflexibility in a compact format Cost occurs in processor complexity Trend until RISC was for variable length instructions;performance factors have reversed the trend Note that instruction length should be a multiple ofword length; if you fetch max length you might getmultiple instructions Intel x86 architecture does not follow this principle PDP-11 Instruction FormatVAX Design PhilosophyVariable length instruction format8 16-bit GP regs (one is SP, one is PC)13 instruction formatsOpcodes are 4-16 bits; 0,1,2 addressesRegister references are 6 bits: 3 for reg, 3 foraddressing mode Rich set of addressing modes Instructions are 16, 32 or 48 bits long Most architectures provide a fairly smallnumber of fixed instruction formats— Addressing mode and opcode are not orthogonal–Instructions typically limited to reg/mem, reg/reg etc— Only 2 or 3 operands max can be accommodated;some instructions inherently require more (ex:integer division with 2 inputs and 2 outputs) VAX design principles were:1. All instructions should have the “natural” number ofoperands2. All operands should have the same generality inspecificationVAX InstructionsOperand Specifiers Highly variable instruction format Opcode is one or two bytes long At a minimum, 1 byte in which leftmost 4 bits arethe address mode specifier— First by FF or FD indicates two byte opcode Followed by 0 to 6 operand specifiers Minimum instruction length is one byte Maximum is 37 bytes!— except “literal” mode (00 followed by 6 literal bits)— 4 bits specify one of 16 registers Operand specifier can be extended by immediateor displacement 8 – 32 bits Indexed addressing mode 0010 4 bit index reg id,followed by base address 8-32 bits8
Example 6 operand instructionADDP6 OP1, OP2, OP3, OP4, OP5, OP6VAXInstructionExamples Adds two packed decimal strings— Op1 and op1 are length and start addr of onestring; op3 and 4 are second string— Result is stored in length/location op5, op6Pentium Instruction FormatARM Instruction Formats All instructions are 32 bits long and follow aregular format— First four bits are condition codes— Next three specify general type of instruction— For most instructions other than branches next fivebits are an opcode and/or modifier bits— Remaining 20 bits are for operand addressing The very regular structure simplifies thedesign of instruction decode unitsARM Instruction FormatsData Processing Immediate The data processing immediate format provides agreat range of values by specifying both an immediatevalue and a rotate value The 8 bit immediate value is expanded to 32 bits andthen rotated by twice the 4-bit rotate valueS For data processing instructions, signifies that the instruction updates condition codesS For load/store multiple, signifies whether execution is restricted to supervisor modeP, U, W bits that distinguish between different types of addressing modeB Distinguishes between an unsigned byte (B 1) and a word (B 0) accessL For load/store instructions, distinguishes between a Load (L 1) and a Store (L 0)L For branch instructions, determines whether a return address is stored in the link register9
Thumb Instruction SetThumb Instruction Set Differences A re-encoded subset of the ARM instruction set Designed to increase performance of ARMimplementations that use a 16-bit or narrowermemory data bus and provide better codedensity 32-bit instructions are re-encoded into 16-bitinstructions All instructions are unconditional (so cc field isunused – saving 4 bits) All arithmetic and logical instructions updatethe condition flags – saving 1 bit Thumb has a subset of operations with a 2-bitopcode plus 3-bit type field – saving 2 bits Remaining 9-bits come from reductions inoperand specifiers. Ex:— Can reference only r0-r7; using only 3 bits forregister references— Immediate values do not include a 4 bit rotate fieldThumb Instructions The ARM processor can execute a mixture ofARM and Thumb instructions A bit in the Processor Control Registerspecifies instruction type10
Computer Organization and Architecture Instruction Set Design One goal of instruction set design is to minimize instruction length Another goal (in CISC design) is to maximize . —Logical Shift Left / Right —Arithm
What is Computer Architecture? “Computer Architecture is the science and art of selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals.” - WWW Computer Architecture Page An analogy to architecture of File Size: 1MBPage Count: 12Explore further(PDF) Lecture Notes on Computer Architecturewww.researchgate.netComputer Architecture - an overview ScienceDirect Topicswww.sciencedirect.comWhat is Computer Architecture? - Definition from Techopediawww.techopedia.com1. An Introduction to Computer Architecture - Designing .www.oreilly.comWhat is Computer Architecture? - University of Washingtoncourses.cs.washington.eduRecommended to you b
Paper Name: Computer Organization and Architecture SYLLABUS 1. Introduction to Computers Basic of Computer, Von Neumann Architecture, Generation of Computer, . “Computer System Architecture”, John. P. Hayes. 2. “Computer Architecture and parallel Processing “, Hwang K. Briggs. 3. “Computer System Architecture”, M.Morris Mano.
CS31001 COMPUTER ORGANIZATION AND ARCHITECTURE Debdeep Mukhopadhyay, CSE, IIT Kharagpur References/Text Books Theory: Computer Organization and Design, 4th Ed, D. A. Patterson and J. L. Hennessy Computer Architceture and Organization, J. P. Hayes Computer Architecture, Berhooz Parhami Microprocessor Architecture, Jean Loup Baer
The first part of Computer Organization and Architecture: Themes and Variations is concerned with the instruction set architecture, and the second part is concerned with computer organization which described an ISA is actually implemented. Today, the term microarchitecture has largely replaced the computer organization. In this workbook, we are .
COMPUTER ORGANIZATION (3-1-0 ) . Computer System Architecture, Morris Mano, PHI Reference Books: 1. Computer Architecture & Organization, William Stallings, Pearson Prerequisite 1. Knowledge of digital circuit 2. Functionality of various gates . Computer Architecture and Organization, by - John P. Hayes, 3rd Edition, Mc Graw Hill .
CS429: Computer Organization and Architecture Instruction Set Architecture Dr. Bill Young Department of Computer Science University of Texas at Austin Last updated: October 2, 2019 at 18:05 CS429 Slideset 6: 1 Instruction Set Architecture
1. Computer Architecture and organization – John P Hayes, McGraw Hill Publication 2 Computer Organizations and Design- P. Pal Chaudhari, Prentice-Hall of India Name of reference Books: 1. Computer System Architecture - M. Morris Mano, PHI. 2. Computer Organization and Architecture- William Stallings, Prentice-Hall of India 3.
Computer Architecture: David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Elsevier. Carl Hamachar, Zvonco Vranesic and Safwat Zaky, Computer Organization, McGraw-Hill. John P. Hayes, Computer Architecture and Organization, McGraw-Hill. Operating System:
