DS1284/DS1286 Watchdog Timekeepers
DS1284/DS1286Watchdog Timekeeperswww.maxim-ic.comGENERAL DESCRIPTIONFEATURESThe DS1284/DS1286 watchdog timekeepers areself-contained real-time clocks, alarms, watchdogtimers, and interval timers in a 28-pin JEDEC DIPand encapsulated DIP package. The DS1286contains an embedded lithium energy source and aquartz crystal, which eliminates the need for anyexternal circuitry. The DS1284 requires an externalquartz crystal and a VBAT source, which could be alithium battery. Data contained within 64 8-bitregisters can be read or written in the same manneras byte-wide static RAM. Data is maintained in thewatchdog timekeeper by intelligent control circuitrythat detects the status of VCC and write protectsmemory when VCC is out of tolerance. The lithiumenergy source can maintain data and real time forover 10 years in the absence of VCC. Watchdogtimekeeper information includes hundredths ofseconds, seconds, minutes, hours, day, date, month,and year. The date at the end of the month isautomatically adjusted for months with fewer than31 days, including correction for leap year. TheDS1284/DS1286 operate in either 24-hour or 12hour format with an AM/PM indicator. The devicesprovide alarm windows and interval timing between0.01 seconds and 99.99 seconds. The real-timealarm provides for preset times of up to one week. Keeps Track of Hundredths of Seconds,Seconds, Minutes, Hours, Days, Date of theMonth, Months, and Years; Valid Leap YearCompensation Up to 2100Watchdog Timer Restarts an Out-of-ControlProcessorAlarm Function Schedules Real-Time-RelatedActivitiesEmbedded Lithium Energy Cell MaintainsTime, Watchdog, User RAM, and AlarmInformationProgrammable Interrupts and Square-WaveOutputs Maintain JEDEC FootprintAll Registers are Individually Addressable viathe Address and Data BusAccuracy is Better than 1 Minute/Month at 25 C (EDIP)Greater than 10 Years of Timekeeping in theAbsence of VCC50 Bytes of User NV RAMUnderwriters Laboratory (UL) Recognized-40 C to 85 C Industrial Temperature RangeOptionPin Configurations appear at end of data sheet.ORDERING INFORMATIONPARTTEMP RANGE0 C to 70 CDS1284-40 C to 85 CDS1284N0 C to 70 CDS1284Q0 C to 70 CDS1284Q 0 C to 70 CDS1284Q/T&R0 C to 70 CDS1284Q T&R-40 C to 85 CDS1284QN-40 C to 85 CDS1284QN -40 C to 85 CDS1284QN/T&R-40 C to 85 CDS1284QN T&R0 C to 70 CDS1286-40 C to 85 CDS1286I-40 C to 85 CDS1286I Denotes a lead(Pb)-free/RoHS-compliant package.VOLTAGE AGE28 DIP (600 mils)28 DIP (600 mils)28 PLCC28 PLCC28 PLCC/Tape and Reel28 PLCC/Tape and Reel28 PLCC28 PLCC28 PLCC/Tape and Reel28 PLCC/Tape and Reel28 EDIP (720 mils)28 EDIP (720 mils)28 EDIP (720 mils)TOP MARK*DS1284DS1284 4QNDS1284QNDS1286DS1286 INDDS1286 IND* A “ ” anywhere on the top mark indicates a lead-free package.1 of 18REV: 032406
DS1284/DS1286OPERATION—READ REGISTERSThe DS1284/DS1286 execute a read cycle whenever WE (write enable) is inactive (high) and CE (chipenable) and OE (output enable) are active (low). The unique address specified by the six address inputs(A0–A5) defines which of the 64 registers is to be accessed. Valid data is available to the eight dataoutput drivers within tACC (access time) after the last address input signal is stable, provided that CE andOE access times are also satisfied. If OE and CE access times are not satisfied, then data access must bemeasured from the latter occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOEfor OE rather than address access.OPERATION—WRITE REGISTERSThe DS1284/DS1286 are in the write mode whenever the WE and CE signals are in the active-low stateafter the address inputs are stable. The latter occurring falling edge of CE or WE determines the start ofthe write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputsmust be kept valid throughout the write cycle. WE must return to the high state for a minimum recoverystate (tWR) before another cycle can be initiated. Data must be valid on the data bus with sufficient datasetup (tDS) and data hold time (tDH) with respect to the earlier rising edge of CE or WE. The OE controlsignal should be kept inactive (high) during write cycles to avoid bus contention. However, if the outputbus has been enabled (CE and OE active), then WE will disable the outputs in tODW from its falling edge.DATA RETENTIONThe watchdog timekeeper provides full functional capability when VCC is greater than VTP. Data ismaintained in the absence of VCC without any additional support circuitry. The DS1284/DS1286constantly monitor VCC. Should the supply voltage decay, the watchdog timekeeper automatically writeprotects itself, and all inputs to the registers become “don’t care.” Both INTA and INTB (INTB) areopen-drain outputs. The two interrupts and the internal clock continue to run regardless of the level ofVCC. However, it is important to ensure that the pullup resistors used with the interrupt pins are neverpulled up to a value greater than VCC 0.3V. As VCC falls below the battery voltage, a power-switchingcircuit turns on the lithium energy source to maintain the clock and timer data functionality. Also ensurethat during this time (battery-backup mode), the voltage present at INTA and INTB (INTB) neverexceeds the battery voltage. If the active-high mode is selected for INTB (INTB), this pin only goes highin the presence of VCC. During power-up, when VCC rises above approximately 3.0V, the power-switchingcircuit connects external VCC and disconnects the VBAT energy source. Normal operation can resume afterVCC exceeds VTP for tREC.WATCHDOG TIMEKEEPER REGISTERSThe watchdog timekeeper has 64 8-bits-wide registers that contain all the timekeeping, alarm, watchdog,control, and data information. The clock, calendar, alarm, and watchdog registers are memory locationsthat contain external (user-accessible) and internal copies of the data. The external copies are independentof internal functions, except that they are updated periodically by the simultaneous transfer of theincremented internal copy (see Figure 1). The command register bits are affected by both internal andexternal functions. This register is discussed later. The 50 bytes of RAM registers can only be accessedfrom the external address and data bus. Registers 0, 1, 2, 4, 6, 8, 9, and A contain time-of-day and dateinformation (see Figure 2). Time-of-day information is stored in binary-coded decimal (BCD). Registers3, 5, and 7 contain the time-of-day alarm information. Time-of-day alarm information is stored in BCD.Register B is the command register and information in this register is binary. Registers C and D are thewatchdog alarm registers and information stored in these two registers is in BCD. Registers E to 3F areuser bytes and can be used to contain data at the user’s discretion.2 of 18
DS1284/DS1286PIN DESCRIPTIONDIPPINEDIPPLCC112, 3—NAMEFUNCTION1INTA2, 3X1, X2Active-Low Interrupt Output A. This open-drain pin requires apullup resistor for proper operation.Connections for Standard 32.768kHz Quartz Crystal. The internaloscillator circuitry is designed for operation with a crystal havinga specified load capacitance (CL) of 6pF. The crystal is connecteddirectly to the X1 and X2 pins. There is no need for externalcapacitors or resistors. For more information on crystal selectionand crystal layout considerations, refer to Application Note 58:Crystal Considerations with Dallas Real Time Clocks.4N.C.No Connection5–1011, 12,13, 15,16–1914, 2120222, 3, 4,21, 24,255–1011, 12,13, 15,16–191420225–1011, 12,13, 15,16–1914, 212022A5–A0DQ0, DQ1,DQ2, DQ3,DQ4–DQ7GNDCEOEAddress TB)272727WE4Data Input/OutputGroundActive-Low Chip-Enable InputActive-Low Output-Enable InputSquare-Wave Output. Push-pull output. High impedance whenVCC is below VTP.Active-Low RAM Clear. Used to clear (set to logic 1) all 50bytes of user NV RAM, but does not affect the registersinvolved with time, alarm, and watchdog functions. To clear theRAM, RCLR must be forced to an input logic 0 (-0.3V to 0.8V) during battery-backup mode when VCC is not applied.The RCLR function is designed to be used via human interface(shorting to ground or by switch) and not be driven with externalbuffers. This pin is internally pulled up and should be leftfloating when not in use.Input for Any Standard 3V Lithium Cell or Other EnergySource. Input voltage must be held between the minimum andmaximum limits for proper operation. The supply should beconnected directly to the VBAT pin. A diode must not be placedin series with the battery to the VBAT pin. Furthermore, a diode isnot necessary because reverse charging current-protectioncircuitry is provided internal to the device and has passed therequirements of Underwriters Laboratories for UL listing. Thispin should be grounded but can be left floating.Active-Low (Active-High) Interrupt Output B. When the activehigh state is selected (IBH 1), an open-drain pullup transistorconnected to VCC sources current when the output is active.When the active-low state is selected (IBH 0), an open-drainpulldown transistor connected to ground sinks current when theoutput is active. If active-high output operation is selected, apulldown resistor is required for proper operation. When activelow output operation is selected, a pullup resistor is required forproper operation.Active-Low Write-Enable Input3 of 18
ry Power-Supply Input. When voltage is applied withinnormal limits, the device is fully accessible and data can bewritten and read. When a backup supply is connected to thedevice and VCC is below VTP, read and writes are inhibited.However, the timekeeping function continues unaffected by thelower input voltage.VCCFigure 1. Block DiagramVCCVBATX1X2Oscillator 8 40.96 40.96PF delay 10PowerSwitchGNDDS1286 onlyDS1286only1024HzSQW 4INTAA0-A5CEOEWEAddress Decode and ControlInternal RegistersExternal Registers,clock, calendar,time of day alarmUpdate seconds throughyears and check time ofday alarmTD INTWD INTCommandRegisterVCC100HzUser RAM50 BytesNSwappinsInternal CountersExternalRegistersWatchdog AlarmInternal CountersIBH100HzInternal RegistersExternalRegistersHundredths ofSecondsDS1284/DS1286Data I/O BuffersDQ0–DQ74 of 18PINTB/(INTB)N
DS1284/DS1286HUNDREDTHS-OF-SECONDS GENERATORThe hundredths-of-seconds generator circuit shown in the Block Diagram (Figure 1) is a state machinethat divides the incoming frequency (4096Hz) by 41 for 24 cycles and 40 for 1 cycle. This produces a100Hz output that is slightly off during the short term, and is exactly correct every 250ms. The divideratio is given by:Ratio [41 x 24 40 x 1] / 25 40.96Thus, the long-term average frequency output is exactly 100Hz.Figure 2. Watchdog Timekeeper Registers5 of 18
DS1284/DS1286TIME-OF-DAY REGISTERSRegisters 0, 1, 2, 4, 6, 8, 9, and A contain time-of-day data in BCD. Ten bits within these eight registersare not used and always read 0 regardless of how they are written. Bits 6 and 7 in the months register (9)are binary bits. When set to logic 0, EOSC (bit 7) enables the RTC oscillator. This bit is set to logic 1 asshipped from Dallas Semiconductor to prevent lithium energy consumption during storage and shipment.The user normally turns this bit on during device initialization. However, the oscillator can be turned onand off as necessary by setting this bit to the appropriate level. Bit 6 of this same byte controls the squarewave output (pin 23). When set to logic 0, the square-wave output pin outputs a 1024Hz square-wavesignal. When set to logic 1, the square-wave output pin is in a high-impedance state. Bit 6 of the hoursregister is defined as the 12- or 24-hour select bit. When set to logic 1, the 12-hour format is selected. Inthe 12-hour format, bit 5 is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is thesecond 10-hour bit (20–23 hours). The time-of-day registers are updated every 0.01 seconds from theRTC, except when the TE bit (bit 7 of register B) is set low or the clock oscillator is not running. Thepreferred method of synchronizing data access to and from the watchdog timekeeper is to access thecommand register by doing a write cycle to address location 0B and setting the TE (transfer enable) bit toa logic 0. Doing so freezes the external time-of-day registers at the present recorded time, allowing accessto occur without danger of simultaneous update. When the watch registers have been read or written, asecond write cycle to location 0B, setting the TE bit to a logic 1, puts the time-of-day registers back tobeing updated every 0.01 second. No time is lost in the RTC because the internal copy of the time-of-dayregister buffers is continually incremented while the external memory registers are frozen.An alternate method of reading and writing the time-of-day registers is to ignore synchronization.However, any single read may give erroneous data as the RTC may be in the process of updating theexternal memory registers as data is being read. The internal copies of seconds through years areincremented and time-of-day alarm is checked during the period that hundreds of seconds read 99 and aretransferred to the external register when hundredths of seconds roll from 99 to 00. A way of making suredata is valid is to do multiple reads and compare. Writing the registers can also produce erroneous resultsfor the same reasons. A way of making sure that the write cycle has caused proper update is to do readverifies and re-execute the write cycle if data is not correct. While the possibility of erroneous resultsfrom reads and write cycles has been stated, it is worth noting that the probability of an incorrect result iskept to a minimum due to the redundant structure of the watchdog timekeeper.TIME-OF-DAY ALARM REGISTERSRegisters 3, 5, and 7 contain the time-of-day alarm registers. Bits 3, 4, 5, and 6 of register 7 always read 0regardless of how they are written. Bit 7 of registers 3, 5, and 7 are mask bits (Figure 3). When all themask bits are logic 0, a time-of-day alarm only occurs when registers 2, 4, and 6 match the values storedin registers 3, 5, and 7. An alarm is generated every day when bit 7 of register 7 is set to logic 1.Similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to logic 1. When bit 7 ofregisters 7, 5, and 3 is set to logic 1, an alarm occurs every minute when register 1 (seconds) rolls from 59to 00.Time-of-day alarm registers are written and read in the same format as the time-of-day registers. Thetime-of-day alarm flag and interrupt is always cleared when alarm registers are read or written.6 of 18
DS1284/DS1286WATCHDOG ALARM REGISTERSRegisters C and D contain the time for the watchdog alarm. The two registers contain a time count fromto 99.99 seconds in BCD. The value written into the watchdog alarm registers can be written or read inany order. Any access to Registers C or D causes the watchdog alarm to reinitialize and clears thewatchdog flag bit and the watchdog interrupt output. When a new value is entered or the watchdogregisters are read, the watchdog timer starts counting down from the entered value to 0. When 0 isreached, the watchdog interrupt output goes to the active state. The watchdog timer countdown isinterrupted and reinitialized back to the entered value every time either of the registers is accessed. In thismanner, controlled periodic accesses to the watchdog timer can prevent the watchdog alarm from evergoing to an active level. If access does not occur, the countdown alarm is repetitive. The watchdog alarmregisters always read the entered value. The actual countdown register is internal and is not readable.Writing Registers C and D to 0 disables the watchdog alarm feature.COMMAND REGISTER (0Bh)Bit #:BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0Name:TEIPSWIBHPU/LVLWAMTDMWAFTDFNote: The initial state of these bits is not defined.Bit 7: Transfer Enable (TE). This bit when set to logic 1 allows the internal time and date counters toupdate the user accessible registers. When set to logic 0, the external, user-accessible time and dateregisters remain static when being read or written, while the internal counters continue to run. Thefunction of this bit is further described in the time-of-day registers sectionBit 6: Interrupt Pin Swap (IPSW). This bit directs which type of interrupt is present on interrupt pinsINTA or INTB (INTB). When set to logic 1, INTA becomes the time-of-day alarm interrupt pin andINTB (INTB) becomes the watchdog interrupt pin. When bit 6 is set to logic 0, the interrupt functions arereversed such that the time-of-day alarm is output on INTB (INTB) and the watchdog interrupt is outputon INTA. Caution should be exercised when dynamically setting this bit as the interrupts are reversedeven if in an active state.Bit 5: Interrupt B Active High/Low (IBH). When bit 5 is set to logic 1, the B interrupt output sourcescurrent when active. When bit 5 is set to logic 0, the B interrupt output sinks current when active.Bit 4: Pulse/Level Output (PU/LVL). When set to logic 1, the pulse mode is selected and INTA sinkscurrent for a minimum of 3ms and then releases. Output INTB (INTB) either sinks or sources current fora minimum of 3ms depending on the level of bit 5. The watchdog timer continues to run and WAF iscleared at the end of the pulse. When set to a logic 0, both INTA and INTB (INTB), when active, outputan active low (INTB (INTB) active high when IBH 1) until the interrupt is cleared.Bit 3: Watchdog Alarm Mask (WAM). When this bit is written to logic 1, the watchdog interruptoutput is deactivated regardless of the state of WAF. When WAM is set to logic 0 and the WAF bit is setto a 1, the watchdog interrupt output goes to the active state, which is determined by bits 1, 4, 5, and 6 ofthe command register.Bit 2: Time-of-Day Alarm Mask (TDM). When this bit is written to logic 1, the time-of-day alarminterrupt output is deactivated regardless of the state of TDF. When TDM is set to logic 0, the time-of-day7 of 18
DS1284/DS1286interrupt output goes to the active state, which is determined by bits 0, 4, 5, and 6 of the commandregister.Bit 1: Watchdog Alarm Flag (WAF). When this bit is set internally to logic 1, a watchdog alarm hasoccurred. This bit is read-only and writing this register has no effect on the bit. The bit is reset when anyof the watchdog alarm registers are accessed. The WAM bit has no effect on the operation of this bit. Ifpulse mode (PU/LVL 1) is selected, the watchdog continues to run and the flag is internally written to 0at the end of the pulse. The WAM bit has no effect on the operation of this bit.Bit 0: Time-of-Day Alarm Flag (TDF). When this bit is set internally to a logic 1, indicates that a matchwith the time-of-day alarm registers has occurred. This bit is read-only and writing this register has noeffect on the bit. The time of the alarm can be determined by reading the time-of-day alarm registers. Thebit is reset when any of the time-of-day alarm registers are read. The TDM bit has no effect on theoperation of this bit.Figure 3. Time-of-Day Alarm Mask S1110FUNCTIONAlarm once per minuteAlarm when minutes matchAlarm when hours and minutes matchAlarm when hours, minutes, and days match8 of 18
DS1284/DS1286ABSOLUTE MAXIMUM RATINGSVoltage Range on Any Pin Relative to Ground .-0.3V to 7.0VOperating Temperature RangeCommercial .0 C to 70 CIndustrial .-40 C to 85 CStorage Temperature Range .-40 C to 85 CSoldering Temperature . .See IPC/JEDEC J-STD-020 Specification (Note 13)Stresses beyond those listed as “Absolute Maxim Ratings” may cause permanent damage to the device. These are stress ratings only, anyfunctional operation of the device at these or any other conditions beyond the those indicated in operations section of the specifications is noimplied. Exposure to absolute maximum ratings for extended periods may affect device reliability.RECOMMENDED DC OPERATING CONDITIONS(TA -40 C to 85 C or 0 C to 70 C.)PARAMETERSYMBOLMINTYPMAXUNITSNOTES5.05.5VCC 0.3 0.83.5V10V10VV1010MAX 1.0 1.0UNITS A A NOTES 1.0 APower-Supply VoltageVCC4.5Input Logic 1VIH2.2VILVBAT-0.32.4Input Logic 0VBAT Input Voltage3.0DC ELECTRICAL CHARACTERISTICS(VCC 5V 10%, TA -40 C to 85 C or 0 C to 70 C.)PARAMETERSYMBOL MINInput Leakage CurrentIIL-1.0Output Leakage CurrentILO-1.0I/O Leakage CurrentILIO-1.0CE VIH VCCOutput Current at 2.4VIOH-1.0Output Current at 0.4VIOL2.0Standby Current CE 2.2VICCS1Standby Current CE VCC - 0.5ICCS2Active CurrentICC1.088Write-Protection VoltageVTPx VBATTYP3.01.26 xVBAT7.04.0151.324x VBATTYP 0.5MAX 0.6mAmAmAmAmAVDC ELECTRICAL CHARACTERISTICS(VCC 0V, VBAT 2.4V to 3.5V, TA 0 C to 70 C.)PARAMETERSYMBOL MINBattery Current (EOSC 0)IBAT9 of 18UNITS ANOTES
DS1284/DS1286CAPACITANCE(TA 25 C)PARAMETERInput CapacitanceOutput CapacitanceInput/Output OTES1AC ELECTRICAL CHARACTERISTICS(VCC 4.5V to 5.5V, TA -40 C to 85 C or 0 C to 70 C.)PARAMETERSYMBOL MINRead Cycle TimetRC150Address Access TimetACCCE Access TimetCOOE Access TimetOEOE or CE to Output ActivetCOE10Output High-Z from DeselecttODOutput Hold from Address ChangetOH10Write Cycle TimetWC150Write Pulse WidthtWP140Address Setup TimetAW0Write Recovery TimetWR10Output High-Z from WEtODWOutput Active from WEtOEW10Data Setup TimetDS45Data Hold TimetDH0INTA, INTB Pulse WidthtIPW310 of 18TYPMAX150150606050344,511,12
DS1284/DS1286READ CYCLE (NOTE 1)WRITE CYCLE 1 (NOTES 2, 6, 7)11 of 18
DS1284/DS1286WRITE CYCLE 2 (NOTES 2, 8)TIMING DIAGRAM: INTERRUPTOUTPUTS PULSE MODE (NOTES 11, 12)12 of 18
DS1284/DS1286POWER-UP/POWER-DOWN CONDITIONPARAMETERCE at VIH before Power-DownVCC Slew from 4.5V to 0V (CE at VIH)VCC Slew from 0V to 4.5V (CE at VIH)CE at VIH after NITS s s snsMAXUNITSNOTESyears9POWER-DOWN/POWER-UP CONDITION(TA 25 C)PARAMETERExpected Data-Retention Time(DS1286)SYMBOLMINtDR10TYPWARNING: Under no circumstances are negative undershoots, of any amplitude, allowedwhen device is in battery-backup mode.13 of 18
DS1284/DS1286NOTES:1. WE is high for a read cycle.2. OE VIH or VIL. If OE VIH during write cycle, the output buffers remain in a high-impedance state.3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE goinglow to the earlier of CE or WE going high.4. tDS or tDH are measured from the earlier of CE or WE going high.5. tDH is measured from WE going high. If CE is used to terminate the write cycle, then tDH 20ns.6. If the CE low transition occurs simultaneously with or later than the WE low transition in write cycle1, the output buffers remain in a high-impedance state during this period.7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the outputbuffers remain in a high-impedance state during this period.8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,the output buffers remain in a high-impedance state during this period.9. Each DS1284/DS1286 is marked with a four-digit date code AABB. AA designates the year ofmanufacture. BB designates the week of manufacture. The expected tDR is defined as starting at thedate of manufacture.10. All voltages are referenced to ground.11. Applies to both interrupt pins when the alarms are set to pulse.12. Interrupt output occurs within 100ns on the alarm condition existing.13. RTC modules can be successfully processed through conventional wave-soldering techniques as longas temperature exposure to the lithium energy source contained within does not exceed 85 C.However, post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonicvibrations are not used to prevent crystal damage.AC TEST CONDITIONSOutput Load: 100pF 1TTL GateInput Pulse Levels: 0 to 3.0VTiming Measurement Reference LevelsInput: 1.5VOutput: 1.5VInput Pulse Rise and Fall Times: 5nsPACKAGE INFORMATIONFor the latest package outline information and land patterns, go to www.maxim-ic.com/packages.PACKAGE TYPEPACKAGE CODEDOCUMENT NO.28 PDIPP28 921-004428 PLCCQ28 1121-004928 EDIPMDP28 121-024114 of 18
DS1284/DS1286PIN CONFIGURATIONSTOP VIEWINTAX1X2N.C.A5A4A3A2A1A0DQ0DQ11282723 DS1284 15DQ3INTAN.C.N.C.N.C.A5A4A3A2A1A0DQ0VCCWEINTB 0191817DQ21316DQ4GND1415DQ3EDIP(720 mils)N.C.X2X1INTAVCCWEINTB (INTB)DIP(600 mils)4532128 27 26256247DS12848232292110201112 13 141915 16 17 18DQ1DQ2GNDDQ3DQ4DQ5DQ6A5A4A3A2A1A0DQ0PLCC15 of 18VCCWEINTB EGNDCEDQ7OEN.C.CEDQ7DQ6DQ5
DS1284/DS1286PACKAGE INFORMATIONPKGDIMA IN.MMB IN.MMD IN.MMD2 IN.MME IN.MME2 IN.MMF IN.MMH IN.MM16 of 1828-PIN PLCCMINMAX0.300 20.0150.0200.380.5180.1000.0202.540.518
DS1284/DS1286PACKAGE INFORMATION (continued)PKGDIMA IN.MMB IN.MMC IN.MMD IN.MME IN.MMF IN.MMG IN.MMH IN.MMJ IN.MMK IN.MM17 of 1828-PIN .0150.022
DS1284/DS1286PACKAGE INFORMATION (continued)PKGDIMA IN.MMB IN.MMC IN.MMD IN.MME IN.MMF IN.MMG IN.MMH IN.MMJ IN.MMK IN.MM28-PIN 0.3500.3758.899.52 120.200.300.0150.0210.380.53NOTE: PINS 2, 3, 21, 24, AND 25 ARE MISSING BY DESIGN.18 of 18Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2006 Maxim Integrated ProductsThe Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
Normal operation can resume after VCC exceeds VTP for tREC. WATCHDOG TIMEKEEPER REGISTERS . The watchdog timekeeper has 64 8-bits-wide registers that contain all the timekeeping, alarm, watchdog, control, and data information. The clock, cal
The DS1286 Watchdog Timekeeper is a self-contained real time clock, alarm, watchdog timer, and interval timer in a 28-pin JEDEC DIP package. The DS1286 contains an embedded lithium energy source . Normal operation can resume after VCC exceeds 4.5 volts for a period of 150 ms. DS12
Rule 165-Timing and Photo Finish HAND TIMING Timekeepers in line with the finish, 5m outside the track, in good view of the finish. Timekeepers use manually operated electronic timers with digital readers. Chief timekeeper allocates duties to judges. Three official timekeepers including chief (and one or two additional timekeepers) on first place and sufficient others for .
Several studies have looked at the relevance and importance of the watchdog model to journalists and media workers, but empirical evidence supporting audience preference for neutral, factual watchdog journalism is scarce. This study addresses this gap in the literature by examining the effect of perceived watchdog reporting on news satisfaction.
Feb 27, 2019 · 2. If no timekeepers have been entered previously, click Blank Template. If some timekeepers have been entered already, click Existing Timekeepers. The Microsoft Excel template downloads to your computer. 3. Open the file and enter the timekeeper information. See the Example and Details work
lithium energy source. Normal operation can resume after VCC exceeds 4.5V for a period of 200ms. RAMIFIED TIMEKEEPER REGISTERS The RAMified timekeeper has 14 registers that are 8 bits wide that contain all the timekeeping, alarm, watchdog, and control information. The
Watchdog Many embedded systems use watchdog timers to rein in errant processors; in safety-critical systems, they're mandatory. But as systems increase in complexity, the watchdog subsystem must mirror that complexity. Ideally in a multitasking system, every active task should be
timeout reaction (reset or NMI) Dependencies: [SRS_Wdg_12018] Watchdog mode selection service Supporting Material: BMW Specification MCAL V1.0a, REQ MAL31.1.2 ⌋(RS_BRF_01464) 6.1.1.2 Initialization 6.1.1.2.1 [SRS_Wdg_12105] The watchdog driver shall provide an initialization
3. Wenger-Clemons, J. (2014). Client system assessment tools for social work practice (Canvas). Group Assignment s . 1. Therapeutic Group Work Assignment 2. Therapeutic Group Work Twitter Feed Individual Assignment 1. M2 Quiz . Module 3: Identity-Based Social Action Group Work . Weeks 5 and 6 . Overview . A. This module reviews a number of topics around how we construct self-concepts and self .
