L1: 6.111 Course Overview - MIT
L1: 6.111 Course OverviewCourse Website: s:¾ Rex Min¾Some lecture material adapted from J. Rabaey, A. Chandrakasan, B. Nikolic, “DigitalIntegrated Circuits: A Design Perspective” Copyright 2003 Prentice Hall/Pearson.L1: 6.111 Spring 2007Introductory Digital Systems Laboratory1
6.111 Staff Contact Information In-charge and Lecturer Lecturer Wendi Li (wendili@mit.edu), Alex Valys (avalys@mit.edu), Zhongying Zhou(zy3@mit.edu)Technical Instructor Javier Castro (javy@mit.edu)Amir Hirsch (amirh@mit.edu)David Wentzloff (ddw@mit.edu)Lab Aides (LAs) Margaret Flaherty – meg@mtl.mit.edu (38-107, x3-0016)Teaching Assistants (TAs) - x3-7350, lab hours in 38-600 Prof. Akintunde (Tayo) Akinwande – akinwand@mtl.mit.edu (39-553, 2587974)Course Assistant: Prof. Anantha P. Chandrakasan – anantha@mtl.mit.edu (38-107, x8-7619)Gim P. Hom (gim@mit.edu, Room 38-644, x4-3373)Stock Clerk Arlin Mason (lab kits) - arlin@mit.edu (38-600, x3-4674)John Sweeney (5th floor) - jsweeney@mit.edu (38-501, x3-0601)L1: 6.111 Spring 2007Introductory Digital Systems Laboratory2
Recommended Books Logic Design: RandyKatz, Gaetano Borriello, Contemporary Logic Design,Pearson Education, 2005 Verilog: there are plenty of good Verilog books and on-lineresources. We recommend the book below for a basicintroduction to Verilog: SamirL1: 6.111 Spring 2007Palnitkar, Verilog HDL, Pearson Education (2nd edition)Introductory Digital Systems Laboratory3
6.111 Goals and Prerequisite Design and Implement Complex Digital SystemsFundamentals of logic design : combinational and sequential blocks System integration with multiple components (memories, discretecomponents, FPGAs, etc.) Use a Hardware Design Language (Verilog) for digital design Interfacing issues with analog components (ADC, DAC, sensors, etc.) Understand different design metrics: component/gate count andimplementation area, switching speed, energy dissipation and power Understand different design methodologies and mapping strategies(discrete logic, FPGAs vs. custom integrated circuits) Design for test Demonstrate a large scale digital or mixed-signal system PrerequisitePrior digital design experience is NOT Required 6.004 is not a prerequisite! Take 6.004 before 6.111 orTake 6.004 after 6.111 orTake both in the same termMust have basic background in circuit theory Some basic material might be a review for those who have taken 6.004 L1: 6.111 Spring 2007Introductory Digital Systems Laboratory4
Overview of Labs Lab 1: Basics of Digital Logic (Discrete Devices) Learnabout lab equipment in the Digital Lab (38-600): oscilloscopesand logic analyzers Experiment with logic gates, flip-flops, device characterization Introduction to Verilog Lab 2: Simple FSM (Traffic Light Controller) Designand implement simple Finite State Machines (FSM) Use Verilog to program an FPGA Report and its revision will be evaluated for CI-M Lab 3: Simple FSM (Memory Tester) Learn how to use an SRAM and testing techniquesLab 4: Complex FSM (Pong Game) Designa system with multiple FSMs (Major/Minor FSM) Video interfaceL1: 6.111 Spring 2007Introductory Digital Systems Laboratory5
Final Project Done in groups of two or three Open ended You and the staff negotiate a project proposal Mustemphasize digital concepts, but inclusion of analog interfaces(e.g., data converters, sensors or motors) common and oftendesirable Proposal Conference Design Review(s) Design presentation in class (% of the final grade for the inclass presentation) Top projects will be considered for design awards Staff will provide help with project definition and scope,design, debugging, and testing It is extremely difficult for a student to receive an A withoutcompleting the final project.L1: 6.111 Spring 2007Introductory Digital Systems Laboratory6
Grading and Collaboration Grading Policy Approximate breakdown:zzzzzz Quiz3 Problem Sets4 Lab exercises Lab 1 Lab 2 Lab 3 Lab 4Writing (Lab 2 revision- part of CIM requirement)Participation (lecture, recitation, project presentations)Final Project10%3%9%10%8%11%10%3%36%We impose late penaltiesLabs are penalized 20% per day Final Project MUST be done on time Collaboration Discuss labs with anyone (staff, former students, other students, etc.)Then do them individuallyz Do not copy anything, including computer files, from anyone else Collaboration (with your partners) on the project is desirablez Project reports should be joint with individual authors specified for each sectionz Copy anything you want (with attribution) for your project reportzL1: 6.111 Spring 2007Introductory Digital Systems Laboratory7
The First ComputerThe BabbageDifference Engine(1834)25,000 partscost: 17,470 The first digital systems were mechanical and used base10 representation. Most popular applications: arithmetic and scientificcomputationL1: 6.111 Spring 2007Introductory Digital Systems Laboratory8
Meanwhile, in the World of Theory ANDORNOT0000000100110110010110111111 1854: George Boole shows that logic is math, not justphilosophy! Boolean algebra: the mathematics of binary valuesL1: 6.111 Spring 2007Introductory Digital Systems Laboratory9
Key Link Between Logic and Circuits(The Vacuum Tube)010101 Lee de Forest, 1906DigitalElectronics Despite existence of relays and introduction of vacuum tube in 1906,digital electronics did not emerge for thirty years! Claude Shannon notices similarities between Boolean algebraand electronic telephone switches Shannon’s 1937 MIT Master’s Thesis introduces the world tobinary digital electronicsL1: 6.111 Spring 2007Introductory Digital Systems Laboratory10
Evolution of Digital ElectronicsVacuum TubesENIAC, 1946TransistorsFirst TransistorBell Labs, 1948UNIVAC, 1951IBM System/360, 19641900 adds/sec500,000 adds/secL1: 6.111 Spring 2007Introductory Digital Systems LaboratoryVLSI Circuits4004, 1971Intel Itanium, 20032,000,000,000adds/sec11
Building Digital Systems Goal of 6.111: Building binary digital solutions tocomputational problems Problem Statement Labs & Design projectProduct specsalgorithm selection,flowcharts, etc. Behavioral Description Algorithms, RTL, etc.FlowchartsState transition diagramsconversion to binary,Booelan algebraBoolean Logic and Statedevice selectionand wiring Hardware Implementation L1: 6.111 Spring 2007Logic equationsCircuit schematicsTTL Gates (AND,OR,XOR )Modules (counter, shifter, )Programmable LogicIntroductory Digital Systems Laboratory12
Building Digital Systems with HDLs Logic synthesis using a Hardware Description Language (HDL)automates the most tedious and error-prone aspects of design Problem Statement Labs & Design projectProduct specsalgorithm selection,flowcharts, etc. Behavioral Description Algorithms, RTL, etc.FlowchartsState transition diagramssoftware-likeprogrammingHDL Description Verilog codeVHDL codeautomated synthesis Hardware ImplementationL1: 6.111 Spring 2007 Programmable LogicCustom ASICsIntroductory Digital Systems Laboratory13
Verilog and VHDLVHDLVerilog Commissioned in 1981 byDepartment of Defense;now an IEEE standard Created by Gateway DesignAutomation in 1985;now an IEEE standard Initially created for ASICsynthesis Initially an interpretedlanguage for gate-levelsimulation Strongly typed; potentialfor verbose code Less explicit typing (e.g.,compiler will pad argumentsof different widths) Strong support for packagemanagement and largedesigns No special extensions forlarge designsHardware structures can be modeled effectively in eitherVHDL and Verilog. Verilog is similar to c and a bit easier to learn.L1: 6.111 Spring 2007Introductory Digital Systems Laboratory14
Levels of Modeling in Verilog Behavioral or Algorithmic LevelHighest level in the Verilog HDL Design specified in terms of algorithm (functionality) without hardwaredetails. Similar to “c” type specification Most common level of description Dataflow Level The flow of data through components is specified based on the idea of howdata is processedGate LevelSpecified as wiring between logic gates Not practical for large examples Switch LevelDescription in terms of switching (modeling a transistor) No useful in general logic design – we won’t use it A design mix and match all levels in one design is possible.In general Register Transfer Level (RTL) is used for acombination of Behavioral and Dataflow descriptionsL1: 6.111 Spring 2007Introductory Digital Systems Laboratory15
Verilog HDL Misconceptions Thecoding style or clarity does not matter as long as it works Two different Verilog encodings that simulate the same way willsynthesize to the same set of gates Synthesis just can’t be as good as a design done by humansz Shades of assembly language versus a higher level languageWhat can be Synthesized CombinationalzzMultiplexors, Encoders, Decoders, Comparators, Parity Generators,Adders, Subtractors, ALUs, MultipliersRandom logic Controlz FunctionsLogicFSMsWhat can’t be Synthesized Precisetiming blocks (e.g., delay a signal by 2ns) Large memory blocks (can be done, but very inefficient)Understand what constructs are used insimulation vs. hardware mappingL1: 6.111 Spring 2007Introductory Digital Systems Laboratory16
The FPGA: A Conceptual View An FPGA is like an electronic breadboard that is wired togetherby an automated synthesis tool Built-in components are called macros3232 b,c,d)ADRR/WRAMDATA(for everything else)L1: 6.111 Spring 2007Introductory Digital Systems Laboratory17
Synthesis and Mapping for FPGAs Infer macros: choose the FPGA macros that efficientlyimplement various parts of the HDL code.always @ (posedge clk)begincount count 1;end.“This section of code lookslike a counter. My FPGA hassome of those.”HDL Code counterInferred MacroPlace-and-route: with area and/or speed in mind, choosethe needed macros by location and route the interconnectL1: 6.111 Spring 2007MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM“This design only uses 10% ofthe FPGA. Let’s use the macrosin one corner to minimize thedistance between blocks.”Introductory Digital Systems Laboratory18
Embedded Digital SystemAnalog Inputs(sensors, audio,video, , motors,multimedia)ControlsynchronizeDigital Inputs(peripherals,buses, rals,buses, lights) Digital processing systems consist of a datapath, memory, and control.Early machines for arithmetic had insufficient memory, and oftendepended on users for control Today’s digital systems are increasingly embedded into everyday placesand things Richer interaction with the user and environmentL1: 6.111 Spring 2007Introductory Digital Systems Laboratory19
Cell Phone Processor (OMAP 2420) from TIL1: 6.111 Spring 2007Introductory Digital Systems Laboratory20
Real-World Performance MetricsCostSpeedEnergycommodity productsscientific computing,simulationportable applications Commercial digital designs seek the most appropriatetrade-offs for the target application keeping time-to-market in mindL1: 6.111 Spring 2007Introductory Digital Systems Laboratory21
Verification and Testing Design can be fun. Verification/testing is hard work. Verification by simulation (and formally through testbenches) is a critical part of the design process. The physical hardware must be tested to debug themapping process and manufacturing defects. Physical realizations often do not allow access to internalsignals. We will introduce formal methods to observe andcontrol internal state.Verification and Design for Test (DFT) are importantcomponents of digital designL1: 6.111 Spring 2007Introductory Digital Systems Laboratory22
The Inverter: Voltage Transfer CharacteristicTruth TableINOUTINOUTDigital circuits perform operations on logical (or Boolean) variables01A logical variable is a mathematical abstraction. In a physicalimplementation, such a variable is represented by an electrical quantity10V(y)VfOHV(y) V(x)VM (Switching Threshold)V OLV OLVOHVOH f (VOL)VOL f (VOH)VM f (VM)V(x)Nominal Voltage LevelsL1: 6.111 Spring 2007Introductory Digital Systems Laboratory23
Example Noise Sources in Digital CircuitsV DDv(t)Capacitive couplingPower and groundnoise Noise sources: coupling, cross talk, supply noise, etc. Digital circuits must be robust against such noisesourcesL1: 6.111 Spring 2007Introductory Digital Systems Laboratory24
The Inverter: Noise MarginTruth TableIN"1"VOHVIHOUT"0"VOLOUT0110V(y)VSlope -1OHNML VIL -VOLNMH VOH -VIHUndefinedRegionVILINSlope -1VOLVVOHVOL IL VIHV(x) Large noise margins protect against various noise sourcesL1: 6.111 Spring 2007Introductory Digital Systems Laboratory25
Regenerative PropertyA chain of invertersv0v1v2v3v4v5outv6Simulated responsev3f (v)5V (Volt)v1fin v(v)v03v1121v2v0in024v26810t (nsec) Voltage gain should be 1 between logic statesL1: 6.111 Spring 2007Introductory Digital Systems Laboratory26
Lab Hours, Equipment, Computers The normal lab hours are (please be out by the indicatedtime):zzzzz Please do not move or reconfigure computers and other lab equipment(logic analyzers, scopes, power supplies, etc.). Please turn off thepower switch for the labkit when you are done for the day.Please report any equipment malfunctions (Logic Analyzers,Computers, labkit, etc.) by tagging such equipment. Also email6.111staff@mit.eduWe will use the following tools installed on the lab PCs (courtesy ofIntel): Monday through Thursday – 9:00 AM to 11:45 PMFriday – 9:00 AM to 5:15 PMSaturday – CLOSEDSunday – 1:00PM to 11:45 PMHours for Holidays, Spring Break, etc. is posted on the course websiteModelSim (powerful front-end simulator for Verilog), Xilinx ISE (software forXilinx FPGAs), Office (Microsoft word, power point, etc.)You can use WinSCP to transfer files between the lab PCs and athenaUse a USB flash drive (provided with your kit) to save your workperiodicallyOn athena use ‘setup 6.111’- ‘setup 6.111’ sources /mit/6.111/.attachrcwhich attaches 6.111-nfs and sources /mit/6.111-nfs/.attachrc whichsets up your path and environment variables, etc.L1: 6.111 Spring 2007Introductory Digital Systems Laboratory27
The 6.111 Lab Labkit based on a state-of-the-art Xilinx FPGA (6 Million gates) Built-in audio/video interfaces, flash memory, high-speed SRAMAdvanced projects in audio/video, wireless, graphics, etc.State-of-the-art testing equipment (logic analyzers, scopes,computers)L1: 6.111 Spring 2007Introductory Digital Systems Laboratory28
L1: 6.111 Spring 2007 Introductory Digital Systems Laboratory 4 6.111 Goals and Prerequisite Design and Implement Complex Digital Systems Fundamentals of logic design : combinational and sequential blocks System integration with multiple components (memories, discrete components, FPGAs, etc.) Us
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Feb 107,4 r 109,6 111,4 113,5 112,3 109,1 r 111,0 r 109,2 Mar 111,9 109,9 111,4 116,8 111,8 110,5 112,2 111,0 . STATISTICS SOUTH AFRICA 6 P0151.1 Construction Materials Price Indices, March 2019 Table 2 - Construction input price index (CIPI): material purchases by type of service Service Weight .
10 AES Accelerator 111 10.1 Introduction 111 10.2 Features 111 10.3 Functional Description 111 10.3.1 AES Algorithm Operations 111 10.3.2 Key, Plaintext and Ciphertext 111 10.3.3 Endianness 112 10.3.4 Encryption and Decryption Operations 114 10
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model: km-280mae title: b. refrigeration circuit index no. description material or model part number required number number f-1 g-0 g-1 g-2 h-0 h-1 h-2 h-3 h-4 j-0 24 copper tube (a1) - high side copper 3a0510-01 1 111 11 111 25 copper tube (b) - high side copper 3a0511g01 1 111 11 111 26 copper tube (c) - high side copper 4a0830-01 1 111 11 111
PIAGGIO/VESPA ET2 50 Alle 044437 89,- 111:-NRG Extreme MC3 AC 50 Alle 044436 89,- 111:-NRG MC-2 LC 50 96- 044419 89,- 111:-Zip 50 (30 km/t) 96-99 044417 89,- 111:-Zip 50 4-Takt 00- 044434 89,- 111:-SCOOTERNØGLEN · NYCKELN 2011
NP60 111 Full-04 16.7 0.6574200 23 0.600 88 111 Full-06 20.9 0.8234200 25 0.670 69 111 Full-08 24.2 0.9534200 27 0.830 75 111 Full-12 31.8 1.2524200 34 1.100 70 111 Full-16 40.6 1.5984200 44 1.500 80 IT01 00 NOTE: Die and dial settings are app
HE-NCM oltage NCM-111 ] E Q U Discharge profiles HV spinel vs. NCM-111 1.5 2.0 2.5 3.0 3.5 0 Capacity [Ah/kg] oltage] 50 100 150 NCM-111 HV spinel E Q U Performance benefit calculated in a model cell Gravimetric energy density [Wh/kg] Volumetric energy density [Wh/l] NCM-111 219 606 HE-NCM 15% 5% HV spinel 8% 8% Marked voltage .
