Synopsys Synthesis Methodology Guide
Synopsys Synthesis Methodology GuideUNIX Environments
Actel Corporation, Sunnyvale, CA 94086 2001 Actel Corporation. All rights reserved.Printed in the United States of AmericaPart Number: 5579009-4Release: April 2001No part of this document may be copied or reproduced in any form or byany means without prior written consent of Actel Corporation.Actel makes no warranties with respect to this documentation and disclaimsany implied warranties of merchantability or fitness for a particular purpose. Information in this document is subject to change without notice.Actel assumes no responsibility for any errors that may appear in thisdocument.This document contains confidential proprietary information that is not tobe disclosed to any unauthorized person without prior written consentfrom Actel Corporation.TrademarksActel and the Actel logotype are registered trademarks ofActel Corporation.Adobe and Acrobat Reader are registered trademarks ofAdobe Systems, Inc.Cadence is a registered trademark of Cadence Design Systems, Inc.Mentor Graphics is registered trademark of Mentor Graphics, Inc.Synopsys, Design Compiler, VHDL Compiler, HDL Compiler, and LibraryCompiler are trademarks or registered trademarks of Synopsys, Inc.UNIX is a registered trademark of X/Open Company Limited.Verilog is a registered trademark of Open Verilog International.Viewlogic is a registered trademark and MOTIVE is a trademark ofViewlogic Systems, Inc.All other products or brand names mentioned are trademarks or registeredtrademarks of their respective holders.ii
Table of ContentsIntroduction . . . . . . . . . . . . . . . . . . . . . . . xiDocument Organization . .Document Assumptions . .Document Conventions . .HDL Keywords and NamingActel Manuals . . . . . . .Online Help. . . . . . . . . . . . . . . . . . . . . . . . . .Conventions . . . . . . . . . . . . . xi. xii. xii. xiii. xvxviii1Setup . . . . . . . .Software RequirementsSystem Setup . . . . .User Setup . . . . . .2Actel-Synopsys Design Flow . . . . . . . . . . . . . . . 9.1.1.1.2Design Flow Illustrated . . . . . . . . . . . . . . . . . . . . 9Design Flow Overview . . . . . . . . . . . . . . . . . . . 103Actel-Synopsys Coding Considerations . . .Multiplexer Encoding . . . . . . . . . . . . . . .Finite State Machine Design . . . . . . . . . . . .DesignWare Module Coding . . . . . . . . . . . .4Synthesis Constraints . . . . . . . . . . . . . . . . . . 53Operating Conditions . . . . . . . .Design Constraints. . . . . . . . . .Design Hierarchy . . . . . . . . . .Internal Tri-State. . . . . . . . . . .Inferring Buffers . . . . . . . . . . .Reducing the Maximum Fanout ValueRegister Type Preferences . . . . . .Avoid Using Certain Cells . . . . . .Register Balancing . . . . . . . . . .Removing Attributes . . . . . . . . .1313263353535761626364646466iii
Table of ContentsUsing (Q)CLKINT . . . . . . . . . . . . . . . . . . . . . . 66Wide Decode Cells in 3200DX and 42MX . . . . . . . . . . . 675Actel-Synopsys Design Considerations . . . . .Compiling Designs with DesignWare Components . .Translating Designs from Other Technologies . . . . .Translating a Design from one Actel family to anotherTranslating Timing Constraints into Designer . . . . .Assigning Pins in Synopsys. . . . . . . . . . . . . .Bus Array Syntax . . . . . . . . . . . . . . . . . .Script Mode Place and Route . . . . . . . . . . . . .Control Flow Commands. . . . . . . . . . . . . . .Complex Act 3 I/O Mapping . . . . . . . . . . . . .Instantiating ACTgen Macros . . . . . . . . . . . . .Generating an EDIF Netlist . . . . . . . . . . . . . .Generating a Structural HDL Netlist . . . . . . . . . .Designing for Radiation Environments . . . . . . . .Maintaining Technology Independence . . . . . . . .696970717272727374758286878888A Synthesis Library Information . . . . . . . . . . . . . 89Timing Parameters. . . . . . . . . .Attributes . . . . . . . . . . . . . .Max Fanout . . . . . . . . . . . . .ACT 3 Specific Information. . . . . .54SX/54SXA Specific Information . . .Additional Information . . . . . . . .Synthesis Library Operating Conditions.89899394949596B DesignWare Library Information . . . . . . . . . . . . yLibraryLibraryLibraryDescription .Adders . . .Subtractors .Comparators . 99.100.101.102
Table of ContentsDesignWare Library Counters . . . .DesignWare Library Incrementer . . .DesignWare Library Decrementer. . .DesignWare Library BOOTH MultiplierImproving Compilation Time. . . . .Module Count and Performance . . .103.104.105.106.107.107C Common Problems . . . . . . . . . . . . . . . . . . .119Library Errors . . . . .Inferring DesignWare .Internal Tri-State. . . .Multiplexer Inferencing.119.120.120.121D Product Support . . . . . . . . . . . . . . . . . . . . .123Actel U.S. Toll-Free Line . . . . . .Customer Service . . . . . . . . .Customer Applications Center . . .Guru Automated Technical SupportWeb Site . . . . . . . . . . . . .FTP Site. . . . . . . . . . . . . .Electronic Mail . . . . . . . . . .Worldwide Sales Offices . . . . . .123.123.124.124.124.125.125.126Index . . . . . . . . . . . . . . . . . . . . . . . . . . .127v
List of FiguresDesignWare Libraries Directory Structure . . . . . . . .Synthesis Libraries Directory Structure . . . . . . . . .Actel-Synopsys Design Flow . . . . . . . . . . . . . .Multiplexer Diagram . . . . . . . . . . . . . . . . .FSM Diagram . . . . . . . . . . . . . . . . . . . . .Compile-Characterize-Recompile Methodology DiagramSchematic Before Register Balancing . . . . . . . . . .Schematic after Register Balancing . . . . . . . . . . .ACT 3 I/O Macros Directory Structure . . . . . . . . .IOPCLBUF and IOCLKBUF driven sequential cells . . .Compilation Results . . . . . . . . . . . . . . . . . .Script Execution Results . . . . . . . . . . . . . . . .“CLK” Pad Driving Sequential I/O Cells and Other LogicCorrected Design After Script Implementation . . . . .Sequential I/O Cell to ACT 3 I/O Cell Link . . . . . . .ACTgen Generated 32 x 32 bit Dual Port RAM . . . . .ACTgen Generated 32 x 32 bit FIFO . . . . . . . . . .DesignWare Adder Symbol . . . . . . . . . . . . . .DesignWare Subtractor Symbol . . . . . . . . . . . .DesignWare Comparator Symbol . . . . . . . . . . .DesignWare Counter Symbol . . . . . . . . . . . . .DesignWare Incrementer Symbol . . . . . . . . . . .DesignWare Decrementer Symbol . . . . . . . . . . .DesignWare Multiplier Symbol . . . . . . . . . . . . .Adder Module Count . . . . . . . . . . . . . . . . .Adder Logic Level . . . . . . . . . . . . . . . . . . .54SX/54SX-A/eX/A500K Adder Module Count . . . . .54SX/54SX-A/eX/A500K Adder Logic Level . . . . . . .Subtractor Module Count . . . . . . . . . . . . . . .Subtractor Logic Level . . . . . . . . . . . . . . . . .54SX/54SX-A/eX/A500K Subtractor Module Count . . .54SX/54SX-A/eX/A500K Subtractor Logic Level . . . . . .5. .6. .9. 15. 26. 59. 64. 65. 75. 76. 78. 78. 79. 79. 80. 84. .111.112.112vii
List of FiguresComparator Module Count . . . . . . . . . . . .Comparator Logic Levels . . . . . . . . . . . . .Area and Module Count For 54SX/54SX-A/eX/A500KLogic Levels for 54SX/54SX-A/eX/A500K . . . . . .Counter Module Count . . . . . . . . . . . . . .Counter Logic Levels . . . . . . . . . . . . . . .Incrementer Module Count . . . . . . . . . . . .Incrementer Logic Levels . . . . . . . . . . . . .Decrementer Module Count . . . . . . . . . . . .Decrementer Logic Levels . . . . . . . . . . . . .viii.113.113.114.114.115.115.116.116.117.117
List of TablesFSM Table . . . . . . . . . . . . . . . . . . . .Sequential Input Cells Available for Synthesis . . . .Sequential Output Cells Available for Synthesis . . .ACT 1/40MX “dont touch” and “dont use” Macros .ACT 2/1200XL “dont touch” and “dont use” Macros3200DX/42MX “dont touch” and “dont use” MacrosACT 3 “dont touch” and “dont use” Macros . . . .54SX “dont touch” and “dont use” Macros . . . . .Macros that Cannot be Connected to HCLKBUF . .Default Operating Conditions . . . . . . . . . . .Synthesis Library Operating Conditions . . . . . .Supported Modules . . . . . . . . . . . . . . . .Adder Pin Description . . . . . . . . . . . . . . .Subtractor Pin Description . . . . . . . . . . . . .Comparator Pin Description . . . . . . . . . . . .Counter Pin Description . . . . . . . . . . . . . .Counter Operation Truth Table . . . . . . . . . .Incrementer Pin Description . . . . . . . . . . . .Decrementer Pin Description . . . . . . . . . . .Multiplier Pin Description . . . . . . . . . . . . . 26. 76. 76. 90. 90. 91. 92. 93. 94. 96. 97. 99.100.101.102.103.103.104.105.106ix
IntroductionThe Synopsys Synthesis Methodology Guide contains information aboutusing Synopsys UNIX synthesis tools with the Actel Designer SeriesFPGA development software to create designs for Actel devices. Referto the Designing with Actel manual for additional information aboutusing the Designer series software and the Synopsys documentationfor additional information about using Synopsys software.Document OrganizationThe Synopsys Synthesis Methodology Guide is divided into the followingchapters:Chapter 1 - Setup contains information and procedures about settingup Synopsys software for use in creating Actel designs.Chapter 2 - Actel-Synopsys Design Flow illustrates and describesthe design flow for creating Actel designs using Synopsys and DesignerSeries software.Chapter 3 - Actel-Synopsys Coding Considerations describes ActelSynopsys specific HDL coding techniques.Chapter 4 - Synthesis Constraints contains descriptions, examples,and procedures for using design constraints on Actel designs.Chapter 5 - Actel-Synopsys Design Considerations containsinformation and procedures to assist you in creating Actel designs withSynopsys and Designer Series software.Appendix A - Synthesis Library Information describes the featuresof the Actel synthesis libraries available for use in design synthesis.Appendix B - DesignWare Library Information describes thefeatures of the Actel DesignWare libraries available for use in designsynthesis.Appendix C - Common Problems describes problems that mayoccur during synthesis and the solution to the problem.Appendix D - Product Support provides information aboutcontacting Actel for customer and technical support.xi
IntroductionDocument AssumptionsThe information in this manual is based on the following assumptions:1.You have installed the Designer Series software.2.You have installed the Synopsys software.3.You are familiar with UNIX workstations and operating systems.4.You are familiar with FPGA architecture and FPGA design software.Document ConventionsThe following conventions are used throughout this manual.Information that is meant to be input by the user is formatted asfollows:keyboard inputThe contents of a file is formatted as follows:file contentsHDL code appear as follows, with HDL keywords in bold:entity actel isport (a: in bit;y: out bit);end actel;Messages that are displayed on the screen appear as follows:Screen Messagexii
IntroductionThe act fam variable represents Actel device family librarydirectories and files. To reference an actual family library directory orfile, substitute the actual name of the family when you see thisvariable. Available families are act1, act2 (for ACT 2 and 1200XLdevices), act3, 3200DX, 40MX, 42MX, 54SX, 54SX-A, eX, and A500K.HDL Keywords and Naming ConventionsThere are naming conventions you must follow when writing Verilogor VHDL code. Additionally, Verilog and VHDL have reserved wordsthat cannot be used for signal or entity names. This section lists thenaming conventions and reserved keywords for each.VHDLThe following naming conventions apply to VHDL designs: VHDL is not case sensitive. Two dashes “--” are used to begin comment lines. Names can use alphanumeric characters and the underscore “ ”character. Names must begin with an alphabetic letter. You may not use two underscores in a row, or use an underscore asthe last character in the name. Spaces are not allowed within names. Object names must be unique. For example, you cannot have asignal named A and a bus named A(7 downto 0).xiii
IntroductionThe following is a list of the VHDL reserved keywords that cannot beused in your withxnorxorThe following naming conventions apply to Verilog HDL designs: Verilog is case sensitive. Two slashes “//” are used to begin single line comments. A slash andasterisk “/*” are used to begin a multiple line comment and anasterisk and slash “*/” are used to end a multiple line comment. Names can use alphanumeric characters, the underscore “ ”character, and the dollar “ ” character. Names must begin with an alphabetic letter or the underscore. Spaces are not allowed within names.xiv
IntroductionThe following is a list of the Verilog reserved keywords that cannot beused in your tributejoinremostaskendcaselargerealtimeActel ManualsThe Designer Series software includes printed and online manuals. Theonline manuals are in PDF format on the CD-ROM in the“/manuals” directory. These manuals are also installed onto yoursystem when you install the Designer software. To view the onlinemanuals, you must install Adobe Acrobat Reader from the CD-ROM.xv
IntroductionThe Designer Series includes the following manuals, which provideadditional information on designing Actel FPGAs:Getting Started User’s Guide. This manual contains information forusing the Designer Series Development System software to createdesigns for, and program, Actel devices.Designer User’s Guide. This manual provides an introduction to theDesigner series software as well as an explanation of its tools andfeatures.PinEdit User’s Guide. This guide provides a detailed description of thePinEdit tool in Designer. It includes cross-platform explanations of allthe PinEdit features.ChipEdit User’s Guide. This guide provides a detailed description of theChipEdit tool in Designer. It includes a detailed explanation of theChipEdit functionality.Timer User’s Guide. This guide provides a detailed description of theTimer tool in Designer. It includes a detailed explanation of the Timerfunctionality.Actel HDL Coding Style Guide. This guide provides preferred codingstyles for the Actel architecture and information about optimizing yourHDL code for Actel devices.Silicon Expert User’s Guide. This guide contains information to assistdesigners in the use of Actel’s Silicon Expert tool.Cadence Interface Guide. This guide contains information to assistdesigners in the design of Actel devices using Cadence CAE softwareand the Designer Series software.Mentor Graphics Interface Guide. This guide contains information toassist designers in the design of Actel devices using Mentor GraphicsCAE software and the Designer Series software.Synopsys Synthesis Methodology Guide. This guide contains preferredHDL coding styles and information to assist designers in the design ofActel devices using Synopsys CAE software and the Designer Seriessoftware.Innoveda eProduct Designer Interface Guide (Windows). This guidecontains information to assist designers in the design of Actel devicesxvi
Introductionusing eProduct Designer CAE software and the Designer Seriessoftware.Innoveda eProduct Designer Interface Guide (UNIX). This guidecontains information to assist designers in the design of Actel devicesusing eProduct Designer CAE software and the Designer Seriessoftware.VHDL Vital Simulation Guide. This guide contains information to assistdesigners in simulating Actel designs using a Vital compliant VHDLsimulator.Verilog Simulation Guide. This guide contains information to assistdesigners in simulating Actel designs using a Verilog simulator.Activator and APS Programming SystemInstallation and User’s Guide. This guide contains information abouthow to program and debug Actel devices, including information aboutusing the Silicon Explorer diagnostic tool for system verification.Silicon Sculptor User’s Guide. This guide contains information abouthow to program Actel devices using the Silicon Sculptor software anddevice programmer.Silicon Explorer Quick Start. This guide contains information aboutconnecting the Silicon Explorer diagnostic tool and using it to performsystem verification.Actel FPGA Data Book. This guide contains detailed specifications onActel device families. Information such as propagation delays, devicepackage pinout, derating factors, and power calculations are found inthis guide.Macro Library Guide. This guide provides descriptions of Actel libraryelements for Actel device families. Symbols, truth tables, and modulecount are included for all macros.A Guide to ACTgen Macros. This Guide provides descriptions ofmacros that can be generated using the Actel ACTgen Macro Buildersoftware.xvii
IntroductionOnline HelpThe Designer Series software comes with online help. Online helpspecific to each software tool is available in Designer, ACTgen, SiliconExpert, Silicon Explorer II, Silicon Sculptor, and APSW.xviii
1SetupThis chapter contains information about setting up UNIX Synopsystools to create Actel designs. This includes setting environmentvariables and information about setting up a system to access the Actelmacro and synthesis libraries. Refer to the Synopsys documentation foradditional information about setting up Synopsys tools.Software RequirementsThe information in this guide applies to the Actel Designer Seriessoftware release R2-1999 or later and Synopsys DC Compiler and FPGACompiler. For specific information about which versions are supportedwith this release, go to the Guru automated technical support systemon the Actel Web site (http://www.actel.com/guru) and type thefollowing in the Keyword box:third partySystem SetupAfter installing Synopsys, make sure the proper environment variablesare set in your UNIX shell script. The following are C shell variables. Ifyou are using another shell, adjust the syntax accordingly.setenv SYNOPSYS synopsys install directory source SYNOPSYS/admin/install/sim/bin/environ.cshsetenv ALSDIR actel install directory setenv ACT SYNOPDIR ALSDIR/lib/synopset path ( ALSDIR/bin path)set path ( SYNOPSYS/ operating system /syn/bin path)For ProASIC A500K devices, use the following C shell variables:setenv SYNOPSYS synopsys install directory source SYNOPSYS/admin/install/sim/bin/environ.cshsetenv ALSDIR actel install directory setenv ACT SYNOPDIRset path ( ALSDIR/am/etc/deskits/synopsys/lib/bin path)set path ( SYNOPSYS/ operating system /syn/bin path)1
Chapter 1: SetupReplace the operating system variable in the “set path” line with“sparc” if you use SunOS, “sparcOS5” if you use Solaris, or “hp700” ifyou use HP-UX.If you use SunOS or Solaris, the following variable must also be set:setenv LD LIBRARY PATH ALSDIR/libIf you use HP-UX, the following variable must also be set:setenv SHLIB PATH ALSDIR/libRefer to the Designer User’s Guide and the Synopsys documentation foradditional information about setting environment variables.User SetupIf you use Actel macros or synthesis libraries when creating designs inSynopsys, you must setup your system to access them. This sectiondescribes how to access Actel DesignWare and synthesis libraries.ReanalyzingDesignWareLibrariesBefore creating a design in Synopsys, you must reanalyze theencrypted DesignWare and simulation libraries to achieve compatibilitywith your version of Synopsys. During reanalysis, the existingDesignWare libraries are overwritten. If you wish to retain the oldlibraries for use with earlier Synopsys versions, copy the “ ALSDIR/lib/synop” tree to a new location before you reanalyze the libraries.To reanalyze all installed Actel DesignWare libraries ProASICA500K devices:1. Acquire write permission.2. Go to the “dwact” directory. Type the following command at theprompt:cd ACT SYNOPDIR/dwact3. Reanalyze the DesignWare libraries. Type:update a500k dw2
User SetupTo reanalyze all installed Actel DesignWare libraries for all otherfamilies:1. Acquire write permission.2. Go to the “scripts” directory. Type the following command at theprompt:cd ACT SYNOPDIR/scripts3. Reanalyze the DesignWare libraries. Type:update all dwTo reanalyze a specific Actel family DesignWare library:1. Acquire write permission.2. Go to the “scripts/ act fam ” directory. Type the followingcommand at the prompt:cd ACT SYNOPDIR/scripts/ act fam 3. Reanalyze the DesignWare library. Type the followingcommand at the prompt:update dwactAccessingDesignWareLibrariesTo access the DesignWare libraries for ProASIC devices, set the searchpath in the “.synopsys dc.setup” file to include the “setup.scr” file(located in ACT SYNOPDIR/dwact) of the A500K device family andinclude the “DWACT” library and component package in your VHDLdescription each time you infer or instantiate a synthetic componentfrom the DesignWare libraries.For ProASIC A500K devices, add the following lines to the“.synopsys dc.setup” file to access the “setup.scr” file:script lib get unix variable (“ACT SYNOPDIR”)include script lib /dwact/setup.scr3
Chapter 1: SetupTo access the DesignWare libraries for all other families, set the searchpath in the “.synopsys dc.setup” file to include the “actsetup.scr” file ofthe Actel device family you want to access and include the “DWACT”library and component package in your VHDL description each timeyou infer or instantiate a synthetic component from the DesignWarelibraries. Add the following lines to the “.synopsys dc.setup” file toaccess the “actsetup.scr” file:script lib get unix variable (“ACT SYNOPDIR”)include script lib /scripts/ act fam /actsetup.scrAdd the following lines to your VHDL description to include the“DWACT” library and component package each time you infer orinstantiate a synthetic component from the DesignWare libraries:library dwact;use dwact.dwact components.all;4
User SetupFigure 1-1 shows the directory structure for the DW libraries1. ACTSYNOPDIRdwact.sldbact components.vhdscriptsDWACT *.SimProASIC A500K DevicesDWACT *.MraDWACT *.SynDWACT vhdCOMPONENTS.SIMCOMPONENTS.SYN act fam dwactact components.vhddwacttutorialDWACT *.SynscriptsDWACT *.Mrasyntutorial ACTSYNOPDIRAll Other Device FamiliesFigure 1-1. DesignWare Libraries Directory StructureThe “dwact.sldb” file is a compiled description of the Actel syntheticlibraries and “DWACT COMPONENTS.syn” is a “compile package”file. An ASCII version of the package file can also be found in the samedirectory. Refer to “DesignWare Module Coding” on page 33 forinformation about using the DesignWare library modules.1. DesignWare libraries are not available for ACT 1 and 40MX devices.5
Chapter 1: SetupAccessingSynthesisLibrariesTo access the synthesis libraries, set the search path in the“.synopsys dc.setup” file to include the “actsetup.scr” file of the Acteldevice family you want to access. Add the following lines to the“.synopsys dc.setup” file to access the “actsetup.scr” file for nonProASIC (A500K) devices:actlib get unix variable (“ACT SYNOPDIR”)include actlib /scripts/ act fam /actsetup.scrFor ProASIC (A500K) devices, add the following lines to the“.synopsys dc.setup” file to access the “setup.scr” file.actlib get unix variable (“ACT SYNOPDIR”)include actlib /dwact/setup.scrNote: To target the 1200XL family, synthesize using the ACT 2 libraryand use the “XL” operating conditions for timing. Refer to“Synthesis Library Operating Conditions” on page 96 foradditional information.Figure 1-2 shows the directory structure for the Synthesis libraries. ACTSYNOPDIR dba500k.sdbProASIC A500K Devices act fam act.dbactsym.sdbAll Other Device FamiliesFigure 1-2. Synthesis Libraries Directory Structure6
User SetupTo verify the library version (non-A500K devices only):Type the following command at the prompt: ACT SYNOPDIR/scripts/version7
2Actel-Synopsys Design FlowThis chapter illustrates and describes the design flow for creating Acteldesigns using Synopsys tools and the Designer Series software.Design Flow IllustratedFigure 2-1 illustrates the design flow for creating an Actel device usingSynopsys Designer Series software1.Design Creation/VerificationBehavioralHDLACT3I/O rarySimulation ToolSynopsysACTgenMacro st etlistStructuralHDLNetlistDesign ImplementationSDFFileExport Commandin File MenuCompileLayoutFuseUser ToolsxBitstream File(for A500K ogrammingAPS SoftwareActivator 2/2s ProgrammerSMS SprintSystem GeneralSilicon SculptorData I/OBP MicrosystemsActelDeviceSystem VerificationSilicon ExplorerFigure 2-1. Actel-Synopsys Design Flow1. Actel-specific utilities/tools are denoted by the grey boxes in Figure 2-1.9
Chapter 2: Actel-Synopsys Design FlowDesign Flow OverviewThe Actel-Synopsys design flow has four main steps; design creation/verification, design implementation, programming, and systemverification. These steps are described in the following sections.DesignCreation/VerificationDuring design creation/verification, a design is captured in an RTLlevel (behavioral) HDL source file. After capturing the design, abehavioral simulation of the HDL file can be performed to verify thatthe HDL code is correct. The code is then synthesized into an Actelgate-level (structural) netlist. After synthesis, a structural simulation ofthe design can be performed. Finally, an EDIF netlist is generated forimport into Designer from which an HDL structural netlist is generatedfor structural and timing simulation.HDL Design Source EntryEnter your HDL design source using a text editor or a context-sensitiveHDL editor. Your HDL design source can contain RTL-level constructs,as well as instantiations of structural elements, such as ACTgen macros.Behavioral SimulationYou may perform a behavioral simulation of your design beforesynthesis. Behavioral simulation verifies the functionality of your HDLcode. Typically, unit delays are used and a standard HDL test benchcan be used to drive simulation. Refer to the VHDL VITAL SimulationGuide or Verilog Simulation Guide for information about performingbehavioral simulation.SynthesisAfter you have created your HDL design source, you must synthesize itbefore placing and routing it in Designer. Synthesis transforms thebehavioral HDL file into a gate-level netlist and optimizes the designfor a target technology. Refer to the Synopsys documentation forinformation about performing design synthesis.10
Design Flow OverviewEDIF Netlist GenerationAfter you have created, synthesized, and verified your design, youmust generate an EDIF netlist for place and route in Designer. ThisEDIF netlist is also used to generate a structural HDL netlist. Refer to“Generating an EDIF Netlist” on page 86 for information aboutgenerating an EDIF netlist.Structural HDL Netlist GenerationGenerate a structural HDL netlist from your EDIF netlist for use instructural and timing simulation by either exporting it from Designer orby using the Actel “edn2vlog” or “edn2vhdl” program. Refer to“Generating a Structural HDL Netlist” on page 87 for information aboutgenerating a structural netlist.Structural SimulationYou may perform a structural simulation of your design before placingand routing it. Structural simulation verifies the functionality of yourpost-synthesis structural HDL netlist. Default unit delays included inthe Actel libraries are used for every gate. Refer to the VHDL VITALSimulation Guide or Verilog Simulation Guide for information aboutperforming structural simulation.DesignImplementationDuring design implementation, a design is placed and routed usingDesigner.
the design flow for creating Actel designs using Synopsys and Designer Series software. Chapter 3 - Actel-Synopsys Coding Considerations describes Actel-Synopsys specific HDL coding techniques. Chapter 4 - Synthesis Constraints contains descriptions, examples, and procedures for us
the design flow for creating Actel designs using Synopsys and Designer Series software. Chapter 3 - Actel-Synopsys Coding Considerations describes Actel-Synopsys specific HDL coding techniques. Chapter 4 - Synthesis Constraints contains descriptions, examples, and procedures for us
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this section shows how to debug using the Synopsys provided Eclipse CDT Debugger or the command-line GDB Debugger along with OpenOCD and Opella-LD on the Synopsys EMSK board. Note: the Synopsys MetaWare Development Toolkit (MWDT) including the ARC MDB or MIDE debuggers are not supported by Opella-LD please use Opella-XD.
Milli-Q Synthesis/Synthesis A10 1 Chapter 1 INTRODUCTION 1-1 USING THIS MANUAL MATCHING THIS MANUAL WITH YOUR MILLI-Q This manual is intended for use with a Millipore Milli-Q Synthesis or Milli-Q Synthesis A10 Water Purification System. This Owner s Manual is a guide for use during the in
and this is still in the form of a PID controller but now the settings are: 2Ip W p c W T p c p K K, W W, and W T 1 Dp. . Colorado School of Mines CHEN403 Direct Synthesis Controller Tuning Direct Synthesis - Direct Synthesis - Direct Synthesis - Colorado School of Mines CHEN403 Direct Synthesis Controller Tuning File Size: 822KB
Organic Synthesis What are the Essentials in Synthesis? 5 Since organic synthesis is applied organic chemistry, to stand a realistic chance of succeeding in any synthesis, the student ought to have a good knowledge-base of organic chemistry in the following areas: Protecting group chemistry Asymmetric synthesis
2.87 GPa ASTM D 4255 Shear modulus G 13 G 23 157.48 MPa ASTM D 732 Sheet compressive strength 71.20 MPa Modified ASTM D 695 Sheet compressive modulus 3.50 GPa Modified ASTM D 695 Core compressive strength 8.73 MPa ASTM C 365 Core compressive modulus 268.9 MPa ASTM C 365 Sheet density 3960 kg/m - Core density 156 kg/m3 - 4 U T T U I 2( / sin )cos ( / )(2 / 1) 2 * h l h l t t l t (1) where, ρ .
