Qucs-S And QucsStudio For Compact Device Modeling

Qucs-S and QucsStudio for Compact Device ModelingMike BrinsonCentre for Telecommunications ResearchLondon Metropolitan University, UKbrinsonm@staff.londonmet.ac.ukSeptember 14-18, 20201 of 3

Presentation Topics Qucs-S and QucsStudio compact device modelling and simulation features QucsStudio and Qucs-S: a combined modelling and simulation package QucsStudio Verilog-A module development: facilities and properties Built in Verilog-A modules: CMC and others Equation-Defined Device (EDD) modelling: principles and application Qucs-S Verilog-A module synthesis: facilities and link to QucsStudio The Verilog-A Equation-Defined Device (VAEDD): structure and properties Enhanced QucsStudio compact device modelling and simulation Enhanced Qucs-S/Xyce behavioural EDD modelling Onwards to the next generation packageMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France2 of 32

QucsStudio and Qucs-SLinux and Windowscompact devicemodelling andsimulation packageMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France3 of 32

QucsStudio and Qucs-SMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France4 of 32

Verilog-A DevelopmentSynthesizeVerilog-AModuleCode[with ADMS]To form“Transistor.va.cpp”and CompileC codeto Turn-Key” systemClick to display generated C codeMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France5 of 32

Verilog-A DevelopmentDrag and drop“transistor.va”Add pins PC,PB and PE.Draw model symbol.Pass symbol parameter valuesto “user compiled model” vianame name construction.Mike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France6 of 32

Built in Verilog-A modulesWindows “turn key” ADMS Verilog-Amodule development systemQucsStudioStandard SPICE models:Diode, BJT, MOSFET, JFETand MESFETCMC and other models:BJT – HICUM/L2/L0MOSFET – EKV2.6The Windows serial (single processor) version of Xyceis compiled under Cygwin64 using static libraries.Hence, a “turn key” Verilog-A module developmentsystem is NOT implemented.Qucs-S/XyceStandard SPICE models:Diode, BJT, MOSFET, JFET and MESFETCMC and other models:BJT – VBIC 1.3, FBH HBT X, HICUML0/L2,MEXTRAM.MOSFET – BSIM3, BSIM4, BSIM6, BSIM SOI,BSIM CMG, MVS, PSPVerilog-A ADMS generated modelsCMC Compact Modelling CoalitionMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France7 of 32

Equation-Defined DevicesQucsStudio: 8 two portTerminals max.Qucs-S: 20 two port terminals max.Mike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France8 of 32

Equation-Defined DevicesMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France9 of 32

EKV 2.6 Id/Vd ExampleMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France10 of 32

EKV 2.6 Example-dynamic chargeMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France11 of 32

EKV 2.6 intrinsic and extrinsic modelsMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France12 of 32

Verilog-A module synthesisQucs-0.0.22-S includes a GPL Verilog-A synthesis tool for compact device modeling. The Verilog-A synthesizer is a fully working version of this open source ECAD tool, Verilog-A device/subcircuit models can be synthesized from the following built in components:Mike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France13 of 32

Verilog-A module synthesisMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France14 of 32

Verilog-A module synthesisInternal nodes - two I(xx) contributions per EDD equationExternal nodes- one I(yy) contribution per node pair.Mike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France15 of 32

Verilog-A module synthesisOnly one I(yy) contribution perexternal node pairMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France16 of 32

Verilog-A Equation-Defined Devices Simulation of complex EDDcompact models can be very slow. Constructing complex Verilog-A modelsoften requires considerable time andeffort. Introduce a compromise: construct acompact device model from a mixtureof EDD blocks and very simple Verilog-Amodules where each Verilog-A module modelsat most two or three EDD equations.These simplified Verilog-A blocks are called Verilog-A Equation-Defineddevices or VAEDDMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France17 of 32

VAEDD ExampleOne or more VAEDD blockscan be mixed with EDD toconstruct a compact devicemodelEKV2.6 :VgdashVPBETAMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France18 of 32

QucsStudio 3.3.2QucsStudio 3.3.2 was released on the 15 July 2020 two years after version 2.5.7.New features: NOT in any specific order EM field simulation using openEMS, New diagram: equation, HICUM L0 model implemented, Improved random-number generation, Smith chart: enable impedance and admittance circles, New document type: PCB layout, Differentiate name.i and name.v in simulator equations, Complex source and load impedance possible in matching dialogue.Plus others and many bug fixesMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France19 of 32

Enhanced QucsStudio features This package has reached an advanced stage of development in that itoffers an almost complete set of circuit simulation routines covering the d.c.to transient domains with significant additions beyond SPICE 3f5, like multitone Harmonic Balance analysis, Monte Carlo analysis, parameter sweep,multi-port S parameter and noise simulation, optimization and systemsimulation. Full "turn-key" Verilog-A compact modelling is also offered via the ADMSsoftware. In terms of development QucsStudio is particularly interesting in that it isthe first of the Qucs series of circuit simulators to introduce interactiveanimation as a tool for advanced circuit simulation. QucsStudio allows one or more parameter values to be simultaneouslycontrolled by sliders. With the computational power of a modern PC changes in simulation outputdata can be observed as movements in plotted curves as the sliders aremoved.Mike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France20 of 31

Enhanced QucsStudio featuresR and CParametertuningMeasurements:Digilent “AnalogDiscovery 2” [16][6]A simple RC low pass passivefilter example showing anadvanced test bench schematicwith a computer controlled transferfunction measurement systemwhere the measured output datais converted from CSV format toQucs simulation control ICONS.Synthesized simulationa.c. control Icon andmeasured data IconsMeasured data andsimulation outputvisualizationMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France21 of 32

Enhanced QucsStudio features* measured dataOptimized valuesThree parameter optimization (Bf, Is, Vaf ) with parallel IC/Vce BJT test bench using a single Vce parametersweep and (1) Ib 200u, PricM measured Ic data and (2) Ib 400u, Pric1M measured Ic data.Mike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France22 of 32

Enhanced QucsStudio featuresOpen EMS simulated responseEM field simulation using openEMS: 1.5 GHz bandpass filter (imported from HyperLynx file by KoenDe Vleeschauwer). Example developed by Dr M. Margraf as part of the Qucs-Studio 3.3.2 release.Mike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France23 of 32

Enhanced Qucs-S/Xyce featuresXyce 7.1 was released on 8 June 2020.New features: NOT in any specific order Non-linear solution dependent capacitorsCap1 1 2 q {ca*(c1*v1*ln(cosh((v(1,2)-v0)/v1) c0*v(1,2))}, orCap1 1 2 c {ca*(c0 c1*tanh((v(1,2)-v0)/v1))}, where both forms areimplemented to ensure charge conservation,C-style ternary conditional operator,.LIN transfer analysis and extraction of S, Y and Z parameters from a generalmultiport network,.SAMPLING : calculates a full analysis (.DC, .TRAN, .AC etc.) over a distributionof parameter values,Sweep loops can now use .DATA commandPlus others and many bug fixesMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France24 of 32

Enhanced Qucs-S/Xyce featuresAdding new Xyce features to Qucs-S. These Xyce specific icons allow new features to be placed on a circuitschematic and interpreted during simulation. Qucs-S has in fact a two level GUI system; items common to SPICE 3f5,and other equivalent simulators, operate via built-in Icons or a XYCEscript, while the less used or recently added features, can only beaccessed via a XYCE script. For example, since 2018 approximately 20 important additions to Xycefunctionality have been implemented, including Monte Carlo analysis andLattice Hypercube sampling via a new .SAMPLING feature, transientsimulation direct sensitivity analysis that supports .FOUR, .LIN for Sparameter multiport analysis with Y and Z output data in Touchstonelevel 1 and level 2 format, and a new charge expression variant forcapacitors that is similar to the EDD branch charge implementation.Mike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France25 of 32

Enhanced Qucs-S/Xyce featuresA Xyce SPICE style tunnel diode compact model with a test bench forinvestigating the effects of stepped device parametersMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France26 of 32

Enhanced Qucs-S/Xyce featuresMuch improved SPICE stylebehavioral modelling facilitiesMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France27 of 32

Enhanced Qucs-S/Xyce featuresIds versus Vds output characteristics generated by .DC scan usingparallel test circuits with fixed values of VgsMike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France28 of 32

Future Qucs-S/Xyce changes Xyce 7.0/7.1 and beyond: Improved mixed-signal interface via the Verilog ProceduralInterface (VPI); Increased Verilog-A simulation speeds; bug fixes (.MEASURE, .ACetc); Improved simulation data output. Current and future Verilog-A developments:Xyce/ADMS compiler modified to use analytic derivatives, new Xyce XML templates.Possible future Verilog-A additions – full implementation of ddx function and a newnon-ADMS-based model compiler !. Tighter linking between QucsStudio/Qucs-S, Verilog-A/Xyce and device/circuitparameter measurements via an Octave “Toolkit”. Introduction of multi-physics modelling via links to OPENMODELLICA: simulation ofreal world systems built from non-electrical and electrical components.Mike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France29 of 32

Summary Low-cost high-performance PC engineering workstations have encouraged the developmentof compact device modelling and circuit simulation tools centered on a high-resolution graphicsinterface for schematic drawing, simulation control and output data visualization. Thispresentation outlined the capabilities of the Qucs/Qucs-S and QucsStudio series of circuitsimulators and modelling tools. These tools allow interactive prototyping of compact device models and their testing usingQucs/QucsStudio and Qucs-S as a central platform in the construction of Verilog-A modulesand Equation-Defined Device models. Each of these, when coupled with established, or new compact modeling techniques likemixed Equation-Defined Device and Verilog-A models (VAEDD), make the current softwarea highly flexible and innovative platform for compact modeling and circuit simulation. Future improvements to the Qucs software indicate that by merging device parametermeasurements with circuit simulation for device parameter extraction, and the introduction ofEM field simulation with openEMS will significantly extend the scope of traditional circuitsimulation.Mike BrinsonESSCIRC/ESSDERC 2020, Grenoble, France30 of 32