XMEGA AU Manual - Oregon State University
8-bit Atmel XMEGA AU MicrocontrollerXMEGA AU MANUALThis document contains complete and detailed description of all modules included inthe Atmel AVR XMEGA AU microcontroller family. The Atmel AVR XMEGA AU is afamily of low-power, high-performance, and peripheral-rich CMOS 8/16-bitmicrocontrollers based on the AVR enhanced RISC architecture. The available AtmelAVR XMEGA AU modules described in this manual are:Atmel AVR CPUMemoriesDMAC - Direct memory access controllerEvent systemSystem clock and clock optionsPower management and sleep modesSystem control and resetBattery backup systemWDT - Watchdog timerInterrupts and programmable multilevel interrupt controllerPORT - I/O portsTC - 16-bit timer/countersAWeX - Advanced waveform extensionHi-Res - High resolution extensionRTC - Real-time counterRTC32 - 32-bit real-time counterUSB - Universal serial bus interfaceTWI - Two-wire serial interfaceSPI - Serial peripheral interfaceUSART - Universal synchronous and asynchronous serial receiver and transmitterIRCOM - Infrared communication moduleAES and DES cryptographic engineCRC - Cyclic redundancy checkEBI - External bus interfaceADC - Analog-to-digital converterDAC - Digital-to-analog converterAC - Analog comparatorIEEE 1149.1 JTAG interfacePDI - Program and debug interfaceMemory programmingPeripheral address mapRegister summaryInterrupt vector summaryInstruction set summary8331F–AVR–04/2013
1.About the ManualThis document contains in-depth documentation of all peripherals and modules available for the Atmel AVR XMEGA AUmicrocontroller family. All features are documented on a functional level and described in a general sense. All peripheralsand modules described in this manual may not be present in all Atmel AVR XMEGA AU devices.For all device-specific information such as characterization data, memory sizes, modules, peripherals available and theirabsolute memory addresses, refer to the device datasheets. When several instances of a peripheral exists in one device,each instance will have a unique name. For example each port module (PORT) have unique name, such as PORTA,PORTB, etc. Register and bit names are unique within one module instance.For more details on applied use and code examples for peripherals and modules, refer to the Atmel AVR XMEGAspecific application notes available from http://www.atmel.com/avr.1.1Reading the ManualThe main sections describe the various modules and peripherals. Each section contains a short feature list and overviewdescribing the module. The remaining section describes the features and functions in more detail.The register description sections list all registers and describe each register, bit and flag with their function. This includesdetails on how to set up and enable various features in the module. When multiple bits are needed for a configurationsetting, these are grouped together in a bit group. The possible bit group configurations are listed for all bit groupstogether with their associated Group Configuration and a short description. The Group Configuration refers to the definedconfiguration name used in the Atmel AVR XMEGA assembler header files and application note source code.The register summary sections list the internal register map for each module type.The interrupt vector summary sections list the interrupt vectors and offset address for each module type.1.2ResourcesA comprehensive set of development tools, application notes, and datasheets are available for download fromhttp://www.atmel.com/avr.1.3Recommended ReadingAtmel AVR XMEGA AU device datasheetsXMEGA application notesThis manual contains general modules and peripheral descriptions. The AVR XMEGA AU device datasheets contains the device-specific information. The XMEGA application notes and AVR Software Framework contain example code and show applied use of the modules and peripherals.For new users, it is recommended to read the AVR1000 - Getting Started Writing C Code for Atmel XMEGA, andAVR1900 - Getting Started with Atmel ATxmega128A1 application notes.XMEGA AU [MANUAL]8331F–AVR–04/20132
2.OverviewThe AVR XMEGA AU microcontrollers is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bitmicrocontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clockcycle, the Atmel AVR XMEGA AU devices achieve throughputs approaching one million instructions per second (MIPS)per megahertz, allowing the system designer to optimize power consumption versus processing speed.The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directlyconnected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many timesfaster than conventional single-accumulator or CISC based microcontrollers.The Atmel AVR XMEGA AU devices provide the following features: in-system programmable flash with read-while-writecapabilities; internal EEPROM and SRAM; four-channel DMA controller; eight-channel event system and programmablemultilevel interrupt controller; up to 78 general purpose I/O lines; 16- or 32-bit real-time counter (RTC); up to eightflexible, 16-bit timer/counters with capture, compare and PWM modes; up to eight USARTs; up to four I2C and SMBUScompatible two-wire serial interfaces (TWIs); one full-speed USB 2.0 interface; up to four serial peripheral interfaces(SPIs); CRC module; AES and DES cryptographic engine; up to two 16-channel, 12-bit ADCs with programmable gain;up to two 2-channel, 12-bit DACs; up to four analog comparators with window mode; programmable watchdog timer withseparate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection.The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. Selecteddevices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for on-chip debug andprogramming.The Atmel AVR XMEGA devices have five software selectable power saving modes. The idle mode stops the CPU whileallowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. Thepower-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until thenext TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time countercontinues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standbymode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startupfrom the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator andthe asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individualperipheral can optionally be stopped in active mode and idle sleep mode.The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory canbe reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use anyinterface to download the application program to the flash memory. The boot loader software in the boot flash section willcontinue to run while the application flash section is updated, providing true read-while-write operation. By combining an8/16-bit RISC CPU with In-system, self-programmable flash, the Atmel AVR XMEGA is a powerful microcontroller familythat provides a highly flexible and cost effective solution for many embedded applications.The Atmel AVR XMEGA AU devices are supported with a full suite of program and system development tools, includingC compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.XMEGA AU [MANUAL]8331F–AVR–04/20133
2.1Block DiagramFigure 2-1. Atmel AVR XMEGA AU block diagram.Oscillator / Crystal / ClockGeneral Purpose I/OVBATPowerSupervision32.768 kHzXOSCBattery BackupControllerReal TimeCounterPORT Q (8)EBIPORT R (2)Digital functionAnalog functionBus masters / Programming / illatorReal TimeCounterEVENT ROUTING NETWORKWatchdogTimerDATA BUSDACAEvent SystemControllerPORT A (8)PowerSupervisionPOR/BOD TAGInt. Refs.PORT P (8)AESTemprefPORT N (8)OCDAREFBDESADCBPORT M (8)InterruptControllerCPUCRCPORT L (8)ACBPORT K (8)NVM ControllerPORT B (8)PORT J (8)FlashDACBE E P RO MEBIPORT H (8)PORT G (8)DATA BUSPORT D (8)SPIFTWIFTCF0:1USARTF0:1SPIEPORT E ICPORT C (8)TWICTCC0:1USARTC0:1IRCOMEVENT ROUTING NETWORKPORT F (8)In Table 2-1 on page 5 a feature summary for the XMEGA AU family is shown, split into one feature summary column foreach sub-family. Each sub-family has identical feature set, but different memory options, refer to their device datasheetfor ordering codes and memory options.XMEGA AU [MANUAL]8331F–AVR–04/20134
Table 2-1.XMEGA AU feature summary overview.FeaturePins, I/OMemoryDetails / sub-familyA1UA3UA3BUA4UTotal100646444Programmable I/O pins78504734Program memory (KB)64 - 12864 - 25625616 - 128Boot memory (KB)4-84-884-8SRAM (KB)4-84 - 16162-8EEPROM22-441 -2General purpose /100C2––49C2TQFPPackageQFN /VQFNBGAQTouchSense channels56565656DMA ControllerChannels4444Channels8888QDEC33330.4 - 16MHz XOSCYesYesYesYes32.768 kHz TOSCYesYesYesYes2MHz calibratedYesYesYesYes32MHz calibratedYesYesYesYes128MHz PLLYesYesYesYes32.768kHz calibratedYesYesYesYes32kHz ULPYesYesYesYesTC0 - 16-bit, 4 CC4443TC1 - 16-bit, 2 CC4322TC2 - 2x 8-bit4442Hi-Res4443AWeX4221RTC11Event SystemCrystal OscillatorInternal OscillatorTimer / CounterRTC321Battery Backup SystemSerial Communication1YesUSB full-speed device1111USART8765SPI4332TWI4222XMEGA AU [MANUAL]8331F–AVR–04/20135
FeatureCrypto /CRCDetails / –222112121212Sampling speed (kbps)2000200020002000Input channels per ADC16161612Conversion IYesYesYesYesJTAGYesYesYesBoundary scanYesYesYesChip selectsExternal Memory (EBI)SRAMYesSDRAMYesResolution (bits)Analog to DigitalConverter (ADC)Digital to AnalogConverter (DAC)Resolution (bits)Sampling speed (kbps)Output channels per DACAnalog Comparator (AC)Program and DebugInterfaceXMEGA AU [MANUAL]8331F–AVR–04/20136
3.3.1AVR CPUFeatures8/16-bit, high-performance Atmel AVR RISC CPU142 instructionsHardware multiplier32x8-bit registers directly connected to the ALUStack in RAMStack pointer accessible in I/O memory spaceDirect addressing of up to 16MB of program memory and 16MB of data memoryTrue 16/24-bit access to 16/24-bit I/O registersEfficient support for 8-, 16-, and 32-bit arithmeticConfiguration change protection of system-critical features3.2OverviewAll Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code andperform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute theprogram in the flash memory. Interrupt handling is described in a separate section, “Interrupts and ProgrammableMultilevel Interrupt Controller” on page 131.3.3Architectural OverviewIn order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memoriesand buses for program and data. Instructions in the program memory are executed with single-level pipelining. While oneinstruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions tobe executed on every clock cycle. For a summary of all AVR instructions, refer to “Instruction Set Summary” on page429. For details of all AVR instructions, refer to http://www.atmel.com/avr.Figure 3-1. Block diagram of the AVR CPU architecture.XMEGA AU [MANUAL]8331F–AVR–04/20137
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and aregister. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register isupdated to reflect information about the result of the operation.The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all havesingle clock cycle access time allowing single-cycle arithmetic logic unit operation between registers or between aregister and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and dataspace addressing, enabling efficient address calculations.The memory spaces are linear. The data memory space and the program memory space are two different memoryspaces.The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can bememory mapped in the data memory.All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/Omemory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed asdata space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five differentaddressing modes supported in the AVR architecture. The first SRAM address is 0x2000.Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.The program memory is divided in two sections, the application program section and the boot program section. Bothsections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming of the application flash memory must reside in the boot program section. The application section containsan application table section with separate lock bits for write and read/write protection. The application table section canbe used for save storing of nonvolatile data in the program memory.3.4ALU - Arithmetic Logic UnitThe arithmetic logic unit supports arithmetic and logic operations between registers or between a constant and a register.Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purposeregisters. In a single clock cycle, arithmetic operations between general purpose registers or between a register and animmediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the statusregister is updated to reflect information about the result of the operation.ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bitarithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardwaremultiplier supports signed and unsigned multiplication and fractional format.3.4.1Hardware MultiplierThe multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports differentvariations of signed and unsigned integer and fractional numbers:Multiplication of unsigned integersMultiplication of signed integersMultiplication of a signed integer with an unsigned integerMultiplication of unsigned fractional numbersMultiplication of signed fractional numbersMultiplication of a signed fractional number with an unsigned oneA multiplication takes two CPU clock cycles.XMEGA AU [MANUAL]8331F–AVR–04/20138
3.5Program FlowAfter reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The programcounter (PC) addresses the next instruction to be fetched.Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the wholeaddress space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the generaldata SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. Afterreset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in theI/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily beaccessed through the five different addressing modes supported in the AVR CPU.3.6Instruction Execution TimingThe AVR CPU is clocked by the CPU clock, clkCPU. No internal clock division is used. Figure 3-2 on page 9 shows theparallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access registerfile concept. This is the basic pipelining concept used to obtain up to 1MIPS/MHz performance with high power efficiency.Figure 3-2. The parallel instruction fetches and instruction executions.T1T2T3T4clkCPU1st Instruction Fetch1st Instruction Execute2nd Instruction Fetch2nd Instruction Execute3rd Instruction Fetch3rd Instruction Execute4th Instruction FetchFigure 3-3 on page 9 shows the internal timing concept for the register file. In a single clock cycle, an ALU operationusing two register operands is executed and the result is stored back to the destination register.Figure 3-3. Single Cycle ALU Operation.T1T2T3T4clkCPUTotal Execution TimeRegister Operands FetchALU Operation ExecuteResult Write BackXMEGA AU [MANUAL]8331F–AVR–04/20139
3.7Status RegisterThe status register (SREG) contains information about the result of the most recently executed arithmetic or logicinstruction. This information can be used for altering program flow in order to perform conditional operations. Note thatthe status register is updated after all ALU operations, as specified in the “Instruction Set Summary” on page 429. Thiswill in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compactcode.The status register is not automatically stored when entering an interrupt routine nor restored when returning from aninterrupt. This must be handled by software.The status register is accessible in the I/O memory space.3.8Stack and Stack PointerThe stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storingtemporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bitregisters that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH andPOP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushingdata onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loadedafter reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to pointabove address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can betwo or three bytes, depending on program memory size of the device. For devices with 128KB or less of programmemory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For deviceswith more than 128KB of program memory, the return address is three bytes, and hence the SP isdecremented/incremented by three. The return address is popped off the stack when returning fro
the Atmel AVR XMEGA AU microcontroller family. The Atmel AVR XMEGA AU is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. The available Atmel AVR XMEGA AU modules described in this manual are: zAtmel AVR CPU zMemories zDMAC - Direct memory access controller
XMEGA E5 [DATASHEET] 5 Atmel-8153K AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet 08/2016 4. Overview The Atmel AVR XMEGA is a family of low power, high perfo rmance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices
xMega ADC For Idiots Like Me. Posted by Tom on Oct 16, 2013 The ADC in Atmel's xMega parts is poorly understood by many, including me. Part of the problem is the large number of problem versions of the xMega chips where the silly thing just doesn't do what you think it should. In fact, even in 2013, they often don't do what you think they should.
Introduction to mikromedia for XMEGA The mikromedia for XMEGA is a compact development system with lots of on-board peripherals which allow development of devices with multimedia contents. The central part of the system is a 8-bit ATxmega128A1 microcontroller. The mikromedia for XMEGA
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AVR Basics The AVR microcontrollers are divided into three groups: 1. tiny AVR 2. AVR (Classic AVR) 3. mega AVR 4. xmega AVR The difference between these devices lies in the available features. The tinyAVR μC are usually devices with lower pin-count or a reduced feature set compared to the mega & xmega AVR's. All AVR devices have identical
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