8 BIT PISO SHIFT REGISTER
M74HC1658 BIT PISO SHIFT REGISTER HIGH SPEED :tPD 15ns (TYP.) at VCC 6VLOW POWER DISSIPATION:ICC 4µA(MAX.) at TA 25 CHIGH NOISE IMMUNITY:VNIH V NIL 28 % VCC (MIN.)SYMMETRICAL OUTPUT IMPEDANCE: IOH IOL 4mA (MIN)BALANCED PROPAGATION DELAYS:tPLH tPHLWIDE OPERATING VOLTAGE RANGE:VCC (OPR) 2V to 6VPIN AND FUNCTION COMPATIBLE WITH74 SERIES 165DESCRIPTIONThe M74HC165 is an high speed CMOS 8 BITPISO SHIFT REGISTER fabricated with silicongate C2MOS technology.This device contains eight clocked master slaveRS flip-flops connected as a shift register, s parallel entry. Parallel data enterswhen the shift/load input is low. The parallel datacan change while shift/load is low, provided thatthe recommended set-up and hold times areobserved. For clocked operation, shift/load mustDIPSOPTSSOPORDER &RM74HC165RM13TRM74HC165TTRbe high. The two clock input perform identically;one can be used as a clock inhibit by applying ahigh signal; to permit this operation clocking isaccomplished through a 2 input nor gate.To avoid double clocking, however, the inhibitsignal should only go high while the clock is high.Otherwise the rising inhibit signal will cause thesame response as rising clock edge.All inputs are equipped with protection circuitsagainst static discharge and transient excessvoltage.PIN CONNECTION AND IEC LOGIC SYMBOLSJuly 20011/12
M74HC165INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONPIN No1279SYMBOLNAME AND FUNCTIONSHIFT/LOAD Data InputsComplementary OutputQHQHSerial OutputClock Input (LOW toCLOCKHIGH, Edge TriggeredSISerial Data Inputs1011, 12, 13,A to H14, 3, 4, 5, 615CLOCK INH8GND16VccParallel Data InputsClock InhibitGround (0V)Positive Supply VoltageTRUTH TABLEINPUTSINTERNAL OUTPUTSOUTPUTSSHIFT /LOADCLOCK nHLHXHQAnQGnHLLXLQAnQGnHXXXXXHHXHa.h : The level of steady input voltage at inputs a through respectivelyQAn - QGn : The level of QA - QG, respectively. before the most-recent transition of the clockLOGIC DIAGRAM2/12NO CHANGENO CHANGE
M74HC165TIMING CHARTABSOLUTE MAXIMUM RATINGSSymbolVCCParameterSupply VoltageValueUnit-0.5 to 7VVIDC Input Voltage-0.5 to VCC 0.5VVODC Output VoltageIIKDC Input Diode Current-0.5 to VCC 0.5 20mAIOKDC Output Diode Current 20mAIODC Output Current 25mAICC or IGND DC VCC or Ground CurrentPDPower DissipationTstgStorage TemperatureTLLead Temperature (10 sec)V 50mA500(*)mW-65 to 150 C300 CAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions isnot implied(*) 500mW at 65 C; derate to 300mW by 10mW/ C from 65 C to 85 C3/12
M74HC165RECOMMENDED OPERATING CONDITIONSSymbolVCCParameterValueSupply VoltageVIInput VoltageVOOutput VoltageTopOperating TemperatureInput Rise and Fall Timetr, tfUnit2 to 6V0 to VCCV0 to VCCV-55 to 125 CVCC 2.0V0 to 1000nsVCC 4.5V0 to 500nsVCC 6.0V0 to 400nsDC SPECIFICATIONSTest ConditionSymbolVIHVILVOHVOLIIICC4/12ParameterHigh Level InputVoltageLow Level InputVoltageHigh Level OutputVoltageLow Level OutputVoltageInput LeakageCurrentQuiescent SupplyCurrentValueTA 25 CVCC(V)Min.2.04.56.02.04.56.0Typ.Max.1.53.154.2-40 to 85 C-55 to 125 1.351.8V0.51.351.82.0IO -20 µA1.92.01.91.94.5IO -20 µA4.44.54.44.46.0IO -20 µA5.96.05.95.94.5IO -4.0 mA4.184.314.134.105.68UnitVV6.0IO -5.2 mA2.0IO 20 µA0.00.10.10.14.5IO 20 µA0.00.10.10.16.0IO 20 µA0.00.10.10.14.5IO 4.0 mA0.170.260.330.406.0IO 5.2 mA0.180.260.330.406.0VI VCC or GND 0.1 1 1µA6.0VI VCC or GND44080µA5.85.635.60V
M74HC165AC ELECTRICAL CHARACTERISTICS (CL 50 pF, Input tr tf 6ns)Test ConditionSymbolParametertTLH tTHL Output TransitionTimetPLH tPHL Propagation DelayTime(CLOCK - QH, QH)tPLH tPHL Propagation DelayTime(SHIFT/LOAD QH, QH)tPLH tPHL Propagation DelayTime(H - QH, QH)fMAXMaximum ClockFrequencytW(H)tW(L)Minimum PulseWidth(CLOCK)tW(L)Minimum PulseWidth(SHIFT/LOAD)tsthtREMMinimum Set-upTime(PI - SHIFT/LOAD)(SI - CLOCK)(SHIFT/LOAD - CK)Minimum HoldTime(PI - SHIFT/LOAD)(SI - CLOCK)(SHIFT/LOAD - CK)Minimum RemovalTime(CLOCK - CK INH)ValueTA 25 CVCC(V)Min.-40 to 85 C-55 to 125 82428nsnsMHznsnsnsnsnsCAPACITIVE CHARACTERISTICSTest ConditionSymbolParameterVCC(V)ValueTA 25 CMin.Typ.Max.10CINInput Capacitance5.05CPDPower DissipationCapacitance (note1)5.055-40 to 85 C-55 to 125 CMin.Min.Max.10UnitMax.10pFpF1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption withoutload. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) CPD x VCC x fIN ICC5/12
M74HC165TEST CIRCUITCL 50pF or equivalent (includes jig and probe capacitance)RT ZOUT of pulse generator (typically 50Ω)WAVEFORM 1: SERIAL MODE PROPAGATION DELAY (f 1MHz; 50% duty cycle)6/12
M74HC165WAVEFORM 2: PARALLEL MODE PROPAGATION DELAY (f 1MHz; 50% duty cycle)WAVEFORM 3: MINIMUM PULSE WIDTH (S/L), PROPAGATION DELAY TIMES(f 1MHz; 50% duty cycle)7/12
M74HC165WAVEFORM 4: SETUP AND HOLD TIME (PI TO S/L) (f 1MHz; 50% duty cycle)WAVEFORM 5: MINIMUM REMOVAL TIME (CK INH TO CK) (f 1MHz; 50% duty cycle)8/12
M74HC165Plastic DIP-16 (0.25) MECHANICAL 0.1301.270.050P001C9/12
M74HC165SO-16 MECHANICAL 190.250.0070.010C0.50.019c145 270.0190.050MS0.620.0248 (max.)PO13H10/12
M74HC165TSSOP16 MECHANICAL 0.1730.1761e0.65 BSCK0 L0.45A0.600.0256 BSC8 0 0.750.0188 0.0240.030A2A1beKcLEDE1PIN 1 IDENTIFICATION10080338D11/12
M74HC165Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom http://www.st.com12/12
The M74HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. Parallel data enters when the shift/load input is low. The parallel data
154 ciento cincuenta y cuatro Lección 5 Las vacaciones ciento cincuenta y cinco 155 El Hotel Regis Label the floors of the hotel. a. piso b. piso c. piso d. piso e. piso f. piso g. piso h. baja Contestar Look at the illustrations of the months and seasons on the previous page.Then answer these questions. modelo Estudiante 1
8-Bit Shift and Store Register High Performance Silicon Gate CMOS The MC74HC4094A is a high speed CMOS 8 bit serial shift and storage register. This device consists of an 8 bit shift register and latch with 3 state output buffers. Data is shifted on positive clock (CP) transitions. The data in the shift register is transferred to the .
21 INPUT: Select a TV input source. 22 SHIFT: Press and hold this button then press buttons 0-9 to directly select TV input Shift-1 VIDEO Shift-2 N/A Shift-3 HDMI 3 Shift-4 USB Shift-5 Component Shift-6 N/A Shift-7 N/A Shift-8 HDMI 1 Shift-9 HDMI 2 Shift-0 TV Tuner Shift-ON Power Toggle
Implementation o Load bit o Read logic o Write logic Multi-bit register Bit out load in if load(t-1) then out(t) in(t-1) else out(t) out(t-1) 1-bit register o Register’s width: a trivial parameter o Read logic o Write logic Bit. . . w-bit register out load in w w Bit Bit Aside: Hardware Simulation Relevant topics from the HW simulator tutorial:
1. Abra las ventanas diariamente un mínimo de 2” para permitir la evaporación de la humedad y para evitar un tiempo de secado prolongado del yeso en la base de piso. 2. Las junturas entre las hojas de la base de piso acústica, al igual que entre la base de piso acústica y las franjas de aislamiento del perímetro, deben pegarse con
2 By the first shift Is meant the morning shift, by the second shift the afternoon or evening shift, and by the third shift the night shift. Some agreements refer to the shift beginning at midnight as the first shift, but this report classifies such work as the third shift. 3 For example, a 10-cent differential on an hourly wage of 60 cents is .
8127FS–AVR–02/2013 4. Register Summary Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F SREG I T H S V N Z C Page 12 0x3E SPH Stack Poin
American Revolution This question is based on the accompanying document (1-6). The question is designed to test your ability to work with historical documents. Some of the documents have been edited for the purposes of the question. As you analyze the documents, take into account the source of each document and any point of view that may be presented in the document. HISTORICAL CONTEXT: passed .
