Design For Scalability In 3D Computer Graphics Architectures

Chapter 1. Introduction2Rendered imageCameraProjectionplane3D objectFigure 1.1: Example of perspective projection in 3D computer graphics. TheBunny 3D model on the right side is rendered to the computer screen plane.The 2D image to the left is the result of rendering the Bunny from the camera’s point of view.mating the original dataset, which would make it possible to view it on a standardgraphics processor, but it would also result in a loss of detail. Scaling the performance of a computer graphics system to facilitate rendering of the large datasetswithout sacrificing detail is a better approach.The process of generating an image in computer graphics is called rendering[63], figure 1.1 shows an example of how an object, the 3D model of The Bunny 1 , isrendered on the screen using perspective projection, simulating how a real cameraworks. Rendering a dataset such as the Bunny is relatively straightforward usinga sequential polygon renderer to render its 69,451 triangles. The triangles form atriangle mesh connecting 35,947 vertices. A simple sequential renderer will breakthe mesh into 69,451 individual triangles, resulting in a vertex count of 208,353 i.e.nearly 6 times as many as needed. This illustrates why a renderer must be carefullyimplemented in order to take advantage of special properties of the input data.1.1 Parallel rendering – the next stepParallel rendering is becoming very important in computer graphics. Historicallyparallel rendering has been used in massively parallel graphics supercomputerssuch as the Silicon Graphics RealityEngine [5] and InfiniteReality [158], as wellas the UNC PixelFlow [155, 57], Pixel-Planes 5 [65] and many others. Howeverthese systems were prohibitively expensive especially when scaled to a high levelof parallelism, with a typical system price tag of one million dollars.1 Thisis the Bunny model from the Stanford 3D scanning repository [208].

1.1. Parallel rendering – the next step3Computer animation for motion pictures is another area where parallel rendering is currently being used successfully. Since motion pictures do not requireinteractive rendering it becomes very simple to parallelize rendering as batch jobs.The computer animation studio simply employs a “rendering farm” of multipleworkstations, possibly hundreds, each working on its own set of animation frames.This type of parallelism is often known as “embarrassingly parallel” because of itsstraightforward implementation. It is not suitable for interactive real-time rendering.At the turn of the millennium we are witnessing a revolution in computationalpower in ordinary PCs, driven by the advances in semiconductor technology. Thishas up to now allowed commodity microprocessors such as the Pentium IV, Athlon,PowerPC and Alpha to scale to very high performance levels. The microprocessorcomputational power evolution was made possible by shrinking the dimensions ofthe transistor, which in turn makes it possible to fit many more transistors on asingle chip and increase the clock frequency. Currently the minimum feature sizeof cutting-edge commercial CMOS semiconductor process technologies is 0.13 µ .Maximum clock frequency for a chip such as the Pentium IV CPU is 1.7 GHz, andthe maximum number of transistors that can be fitted on a chip die as large as 400mm2 is more than 100 million transistors.This progress in semiconductor technology development is not going to stopany time soon, as predicted by Gordon Moore’s historically proven law. Moore’slaw predicts a two-fold increase in semiconductor transistor density every 18months, i.e. exponential growth. Sources in the semiconductor industry claim thatthis development will continue for at least ten more years just by improving CMOSsemiconductor technologies. Note that Moore’s law only claims technology improvements of the minimum transistor size in semiconductors, while improvementsin computational power, complexity and speed are side-effects of putting improvedtechnology to good use.Ironically it is becoming increasingly more difficult to put all this on-chip realestate made available by technological advances to good use. Current microprocessors are using the added silicon area to embed larger cache memories, longerpipelines, multiple execution units and wider SIMD (Single Instruction MultipleData) vector processing datapaths. A detailed description of these concepts in thecontext of the microarchitecture of the AMD K6-2 3D-Now! microprocessor isavailable in [206]. Current 3D graphics accelerators are also taking advantageof increased silicon area by integrating more parts and improved features of therendering pipeline into a single chip. These parts were previously executed bymicroprocessors and/or several other ASICs (Application Specific Integrated Circuit). Some recent graphics accelerators [188, 187] are even integrating on-chipmemories in order to overcome memory bandwidth problems.

Chapter 1. Introduction4Let us examine the hypothetical situation when an entire graphics renderingpipeline has been implemented in hardware on one chip, and the chip still hasmany nanoacres2 of unused area left. Note that because of the numerous pins 3 required to interface with high performance memories and buses, a graphics ASICdesign is often pad-limited so the die size cannot simply be reduced, leaving uswith unused silicon area. Adding extra functionality to a chip to utilize the increasing chip area has limitations, though. Let us assume in this hypothetical casethat better pipelining or “feature creep scalability” will not improve the speed ofthe design further. In order to scale to higher levels of performance (in computergraphics infinite rendering performance is preferred), parallelism is required. Thiscan be achieved with a scalable graphics architecture, which will allow processingunits of the graphics accelerator to be replicated across the entire chip. This thesiswill show that replicating a single type of processing unit across the chip surfaceis not ideal, several different processor types are needed as well as an efficientcommunication network between them, forming a heterogeneous structure of processors, memories and communication. This is because a parallel renderer needsto redistribute temporary rendering data at least once at some point in the rendering pipeline in order to be scalable. Automatic load-balancing is also needed in aparallel renderer in order to keep all processors busy. While the parallel redistribution network provides a facility for internal load balancing, the input to the parallelrenderer should also be partitioned so it can be distributed over the renderers toequalize the rendering workload.Further, some level of programmability of the functional units is desirable asit will provide a tradeoff between having hardwired datapaths or general purposemicroprocessors at each node. Several emerging new microarchitectures such asIntel’s network processors and the Imagine [172] stream processor give an idea ofwhat is possible when integrating multiple programmable parallel processing unitson one chip. This is also evidenced by recent trends in the graphics accelerator market, where the new Nvidia GeForce 3 graphics processor provides programmablefunctional units for per-vertex and per-pixel processing, allowing the applicationwriter to customize those parts of the pipeline by using simple stream processingscripts, rather than a hardwired pipeline. A promising emerging alternative methodfor achieving programmability is to use field programmable gate arrays (FPGAs).To summarize, under the somewhat unlikely assumption that we cannot thinkof any extra functional features to add to the renderer and that the number ofpipeline stages cannot be increased further, then one practical way to utilize anyremaining chip area is to parallelize. This can be done by building a pipeline21nanoacre 4.0469 mm2Neon [140] chip has 824 pins (609 signal pins power supply pins).3 The

1.2. Contribution of this thesis5of parallel processing farms [62], each corresponding to a stage in the graphicspipeline. By using efficient communication for data redistribution between theworker processors in each stage, good scalability can be achieved. This is why parallel processing is likely to see a revival soon, but this time for embedded systemssuch as 3D graphics processors. By implementing such embedded parallel systemson a single chip, many of the communication problems limiting the scalability ofparallel real-time graphics can be reduced.The author’s past experience with Transputer networks for rendering (raytracing) [87] by using networks containing up to 40 transputers were severely limited by the slow communication channels and all-to-one communication requiredto assemble the final image, making real-time rendering impossible although theslower ray-tracing algorithms did scale in performance from the parallelism. Today parallel real-time rendering looks far more promising as better communicationpaths are available.1.2 Contribution of this thesisThis thesis is an attempt to describe and analyze useful methods and techniquesfor designing and implementing scalable parallel rendering architectures for 3Dcomputer graphics. During the Ph.D. study a prototype 3D graphics architecturecalled Hybris has been developed. Hybris is also a prototype rendering systemimplementation testbed for experimental hardware/software codesign of graphicsarchitectures, which can be tailored to many specific 3D graphics applications.Several variants of Hybris have been implemented during the Ph.D. study for bothsoftware and hardware. In software, both scanline and tile-based versions wereimplemented. Two different parallel software renderers were implemented, onebased on functional parallelism and another based on data parallelism. Parallelsoftware implementations for both single- and multi-processor Windows 2000 systems have been demonstrated. Efficient methods for partitioning and sorting wereimplemented to allow parallelism and efficient cache usage.Working hardware/software codesign implementations of Hybris for standardcell design based ASIC (simulated) [71] and FPGA technologies [207] have beendemonstrated. The hardware part of the design was carried out using manual translation of the software C source code to a synthesizable VHDL specification. TheFPGA implementation was the first physically working hardware implementationof the Hybris renderer back-end. Currently the FPGA implementation shows greatpotential for future development, for example many of the parallel back-end architectural concepts demonstrated on the multiprocessor PC may be implemented.Additionally a fully functional VGA video output interface was implemented in

6Chapter 1. Introductionthe FPGA, eliminating the need to transfer the final rendered frames back to thehost PC.For interfacing the graphics rendering architecture to applications an interfacewith a high abstraction level is required. Since common interfaces such as OpenGLenforce strict ordering of input data, they make data partitioning optimizations difficult, in effect relying on the calling application to do all front-end optimizations.The chosen solution is to rely on the ISO standard VRML 97 virtual reality modeling language [28]. VRML uses a scene graph programming model which does notassume anything about how an object is actually rendered. This abstraction allowsobject level optimizations to be made “behind the scenes”.In Hybris a flexible VRML 97 scene graph engine with an EAI [135] Javainterface and a custom object-oriented C interface has been implemented toallow flexible integration of the Hybris rendering technology into Java and C applications. The VRML abstraction allows Hybris to perform object level preprocessing and data partitioning optimizations. While lower level interfaces arealso present internally in the Hybris architecture for the front-end and back-endgraphics pipelines, these interfaces are not intended to be exposed to applications.Finally the 3D-Med medical visualization workstation is an example of a complete application which uses the Hybris 3D computer graphics architecture for visualization of e.g. bone structures from CT-scans.In summary figure 1.2 gives an overview of the various aspects of the workdone in the Ph.D. study, however only some parts of the work will be covered inthis thesis. The description of the design of the Hybris hybrid parallel graphicsarchitecture is the main topic of this thesis. Hybrid parallel rendering offers somenice advantages; Good load balancing, low memory bandwidth requirements andgood scalability.1.3 Thesis chapter overviewThis chapter has presented the motivation to design a scalable graphics architecture as well as an introduction to some of the concepts. The rest of this thesis isstructured as follows:Chapter 2 focuses on scalability in general with special focus on parallel rendering. State of the art in current commercial rendering architectures is covered.An introduction to recurring concepts in parallel rendering is given with an analysisof some of the available options.Chapter 3 gives an in-depth view of the design concepts of the Hybris graphicsarchitecture at an abstraction level slightly above the possible implementations.The potentially available parallelism of the architecture is described independent

1.3. Thesis chapter overview7of an actual implementation.Chapter 4 goes forth by analyzing the possible implementation options for thearchitecture presented in chapter 3 by using codesign to map the designed architecture onto software and hardware components. We look at different base implementation platforms, such as single or dual CPU PC’s for software implementations.ASIC and FPGA hardware accelerator implementations are also covered.Chapter 5 discusses how to interface with the application that uses the graphicsarchitecture. An implementation of VRML 97 is used as a high-level interface tothe architecture. As an example of an application which uses the architecture, the3D-Med medical visualization workstation is presented.Finally, Chapter 6 summarizes the work with conclusions and suggestions forfuture work.

Chapter 1. Introduction8Data acquisition and extraction3D tion3D ewingexperienceApplication levelVRMLscene with3D rocessing and static optimization3D surfacemodelPreprocessing& StaticoptimizationOptimized3D surfacemodel3D graphics pipeline, Front-endOptimized3D surfacemodel3D modeltraversal,culling &distributionGeometryTransform& LightingBackfaceculling sortedtriangleheap3D graphics pipeline, gSub-imagecompositionFinalrenderedimage!Figure 1.2: Overview of the Hybris 3D computer graphics architecture, including extensions for interactive virtual reality based on VRML as well asextensions to support the 3D-Med medical 3D visualization workstation.

Chapter 2Parallel Rendering andScalabilityThis chapter focuses on parallel rendering in general but with special focus on scalability. State of the art in current commercial rendering architectures is discussed,including recent PC based architectures. An introduction to recurring conceptsin parallel rendering is given with an analysis of some of the available options.Architectural concepts and design methods for scalability of parallel rendering architectures on the system-architecture level will also be discussed.2.1 Scalable 3D graphics architecturesIn computer graphics there is a need for a scalable solution where the rendering performance increases as more parallel hardware processing units are added. Severalscalable 3D graphics architectures have been published, e.g. the PixelFlow [155]and Pomegranate [51]. With the advent of highly integrated ASIC technologiesand fast interconnects, scalable architectures are gaining interest.Before parallelism can be applied to rendering in 3D computer graphics somemethods for achieving scalability is needed. Definition of scalability: The abilityof a system to take advantage of additional processing units. This usually impliesthat the system can take advantage of parallel execution. Two types of scalabilitycan be considered; hardware scalability and software scalability. Hardware (i.e.performance) scalability is the ability to gain higher levels of performance on afixed size problem. Software (i.e. data) scalability is the ability to encompass largersize problems, such as added model complexity or framebuffer resolution.In popular terms software scalability means that a system can take advantageof faster/better/more complex hardware to improve the overall quality of the work9

Chapter 2. Parallel Rendering and Scalability10performed. This definition is often used with recent PC graphics hardware (e.g.Nvidia), where the intent is to make proper use of faster graphics hardware withexisting software, i.e. the software should detect that powerful hardware is used andattempt to utilize it by increasing the quality of the task. In a computer graphicsapplication such as a game this can mean using more detailed geometry in the 3Dmodels, larger textures, additional texture layers, better illumination models, etc.This definition of scalability refers to the scalability of the application with respectto dynamically adapting itself to different generations of hardware.As a combined definition, scalability refers to the ability of an algorithm to beable to efficiently utilize multiple parallel processors.A simple form of scalability is when a software renderer is running on a multiprocessor computer, for example a PC configured in an SMP (Symmetric MultiProcessing) configuration with two CPUs using shared main memory. The PCmust be running an operating system such as Linux or Windows NT/2000 whichsupports multiple processors, processes and threads. In an SMP system the mainmemory is shared between all processors and a process can have two concurrentlyrunning threads with a speedup scaling factor of around 2 (the actual scaling factordepends on the main memory access patterns and synchronization of the threads).However hardware performance scalability is limited by the bandwidth of theshared main memory, because adding more processors does not increase the mainmemory bandwidth. This is why highly scalable multiprocessors use a distributedmemory architecture where the pro

The need for scalability comes from the desire to design and build an interactive 3D graphics system with the ability to handle very large datasets. Such a large dataset, possibly containing millions of polygons, cannot easily be handled by nor-mal graphics workstations and PCs. This thesis will focus on the techniques and