Energy-Efficient Low Latency IIR Using Enhanced Boost Logic - IRD India

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Energy-Efficient Low Latency IIRUsing Enhanced Boost Logic1R.Gomathi & 2Kalpalatha Reddy1SKR Engineering College, Poonamallee , ChennaiECE dept. SKR Engineering College, Poonamallee , ChennaiE-mail : go22mathi@gmail.com2Abstract – In this work, a 6-tap 8-bit IIR filter which usesa novel charge recovery logic, called Enhanced BoostLogic, which achieves high efficiency and highperformance operation through the use of aggressivevoltage scaling, gate overdrive, and charge-recoverytechniques. A 6-tap 8-bit IIR filter implemented usingEnhanced Boost Logic with only 1.5 cycles of latencyoverhead compared to a static CMOS implementation. TheIIR using EBL logic dissipates only 24mW which achieves36.07% improvement compared to previously reportedFIR Filter (14 tap 8-bit FIR) .In recent years, a charge-recovery family that usesmultiple power supply level is called as Boost Logicwas demonstrated in silicon at clock speeds exceeding1GHz [5], [6]. Boost Logic improves upon theenergy/latency tradeoff of previous charge-recoverycircuit families, as it relies on gate overdrive to evaluatelogic functions with significantly decreased delay andwith minimal short-circuit current. It thus has thepotential to achieve high-speed and low-poweroperation with pipeline latencies that are comparable tothose of static CMOS designs. Enhanced Boost Logic(EBL) is an improved version of the basic Boost Logicthat achieves shorter pipeline latencies while retainingits energy advantages over static CMOS. Similar toBoost Logic, EBL is capable of operation at high clockfrequencies by developing a near-threshold voltagebefore the onset of the power clock.Index Terms—Digital signal processing (DSP), low-powerVLSII.INTRODUCTIONVoltage scaling has diminished with eachadvancement in process technologies, making powerdissipation one of the primary design considerations formodern digital systems. This design describes a novelcharge-recovery logic family and that utilizes energyrecovery techniques to recycle the charge from thesystem,effectively reducingdynamicpowerdissipation[1].Evaluation devices in EBL have twice the gateoverdrive compared to first-generation BoostLogic[5],[6] however, enabling the design of complexlogic gates and thus decreasing total gate counts.Consequently, EBL used in IIR further improves uponthe energy/latency tradeoff of Boost Logic, yieldinglower latency while maintaining good energy efficiency.It improves upon Boost Logic also with respect toimplementation complexity, as it requires a smallernumber of power supplies and less area[12],[13].Charge recovery circuitry has the potential toreduce dynamic power consumption in digital systemswith significant switching activity. To keep energyconsumption to a minimum, charge-recovery circuitry istypically designed so that it maintains low voltage dropsacross device channels, while recovering the chargesupplied to it every clock cycle[1]. The overall energyefficiency of charge-recovery circuitry thereforedepends on the rate at which transitions occur, yieldingan inverse relationship between energy consumption andclock period. Relying on this energy/latency tradeoff,charge-recovery circuitry can operate with energyconsumption below, the fundamental limit of staticCMOS.II. METHODOLOGYA. Enhanced Boost logicEnhanced Boost Logic (EBL) is presented in thischapter which is an improved version of the basic BoostLogic that achieves shorter pipeline latencies whileretaining its energy advantages over static CMOS.Similar to Boost Logic, EBL is capable of operation athigh clock frequencies by developing a near-thresholdvoltage before the onset of the power-clock. EvaluationISSN (PRINT) : 2320 – 8945, Volume -1, Issue -4, 20139

ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE)devices in EBL have twice the gate overdrive comparedto first generation Boost Logic, however, enabling thedesign of complex logic gates and thus decreasing totalgate counts. Consequently, EBL further improves uponthe energy/latency tradeoff of Boost Logic, yieldinglower latency while maintaining good energy efficiency.EBL improves upon Boost Logic also with respect toimplementation complexity, as it requires a smallernumber of power supplies.III. ENHANCED BOOST LOGIC USEDIN IIR FILTERIIR filters are digital filters with infinite impulseresponse. Unlike FIR filters, they have the feedback (arecursive part of a filter) and are known as recursivedigital filters.The Enhanced Boost Logic presented in this paperis another variant of Boost Logic that is aimed atpushing the iso-energy frequency point higher thanSubthreshold Boost Logic, while at the same timedecreasing latency overhead. Fig. 1 shows a cascade ofthree EBL buffers. Each EBL gate has two stages:Evaluation and Boost. Similar to SBL, the Boost stageconsists of a cross-coupled inverter with the source ofthe PMOS connected to a charge-recovering clock phasepc, enabling high performance through enhanced gateoverdrive. Unlike SBL, however, the Evaluation stagerelies on a NMOS precharge device for pull-up, insteadof a complementary pull-up network, thus increasingperformance by avoiding the series-connected devices inthe pull-down network (PDN). The bulk of all NMOStransistors are connected to ground, and the bulk ofPMOS transistors in the cross-coupled inverters areconnected to the corresponding power-clock phases.From a functional point of view, each EBL gate isequivalent to a combinational logic block (Evaluationstage) that is powered by a near-threshold supply V CCand drives a transparent latch synchronized by clockphase pc (Boost stage). Cascades of EBL gates areclocked by alternating clock phases pc and pc b.Figure 2 Block diagrams of FIR and IIR filtersFor this reason IIR filters have much betterfrequency response than FIR filters of the same order.Unlike FIR filters, their phase characteristic is not linearwhich can cause a problem to the systems which needphase linearity. For this reason, it is not preferable to useIIR filters in digital signal processing when the phase isof the essence.Otherwise, when the linear phase characteristic isnot important, the use of IIR filters is an excellentsolution. There is one problem known as a potentialinstability that is typical of IIR filters only. FIR filtersdo not have such a problem as they do not have thefeedback. For this reason, it is always necessary tocheck after the design process whether the resulting IIRfilter is stable or not.IIR filters can be designed using different methods.One of the most commonly used is via the referenceanalog prototype filter. This method is the best fordesigning all standard types of filters such as low-pass,high-pass, band-pass and band-stop filters.The design method using reference analogprototype filter. Figure.3 illustrates the block diagram ofthis method.Figure 3. Block diagram of design method usingreference analog prototype filterFigure 1.Cascade of three EBL buffersISSN (PRINT) : 2320 – 8945, Volume -1, Issue -4, 201310

ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE)FIR filters can have linear phase characteristic,which is not typical of IIR filters. When it is necessaryto have linear phase characteristic, FIR filters are theonly available solution. In other cases when linear phasecharacteristic is not necessary, such as speech signalprocessing, FIR filters are not good solution. IIR filtersshould be used instead. The resulting filter order isconsiderably lower for the same frequency response.filter resembles an ideal filter. This is illustrated in thefollowing figure 4 of a frequency response of lowpassButterworth filters with different orders. The steeper thefilter gain falls, the higher the filter order is.The most commonly used IIR filter design methoduses reference analog prototype filter. It is the bestmethod to use when designing standard filters such aslow-pass, high-pass, bandpass and band-stop filters. Thefilter design process starts with specifications andrequirements of the desirable IIR filter. A type ofreference analog prototype filter to be used is specifiedaccording to the specifications and after that everythingis ready for analog prototype filter design. The next stepin the design process is scaling of the frequency range ofanalog prototype filter into desirable frequency range.This is how an analog prototype filter is converted intoan analog filter.The filter order determines the number of filterdelay lines, i.e. number of input and output samples thatshould be saved in order that the next output sample canbe computed. For instance, if the filter order is 10, itmeans that it is necessary to save 10 input samples plus10 output samples preceding the current sample. Allthese 21 samples will affect the next output sample. TheIIR filter transfer function is a ratio of two polynomialsof complex variable z-1. The numerator defines locationof zeros, whereas the denominator defines location ofpoles of the resulting IIR filter transfer function.A. Infinite impulse response (IIR) filter designThe impulse response or the frequency responseclassify digital filters. The impulse response is theresponse of a filter to an input impulse: x[0] 1 andx[i] 0 for all i 0. The Fourier transformation of theimpulse response is the filter frequency response whichdescribes the gain of the filter for different frequencies.If the impulse response of the filter falls to zeroafter a finite period of time, it is an FIR (Finite ImpulseResponse) filter. However, if the impulse responseexists indefinitely, it is an IIR (Infinite ImpulseResponse) filter. How the output values are calculateddetermines whether the impulse response of a digitalfilter falls to zero after a finite period of time. For FIRfilters the output values depend on the current and theprevious input values, whereas for IIR filters the outputvalues also depend on the previous output values. Theoutput values of IIR filters are calculated by adding theweighted sum of previous and current input values to theweighted sum of previous output values. If the inputvalues are xi and the output values yi, the differenceequation defines the IIR filter:Figure.4 IIR filter direct realizationThis structure is also known as a direct form Istructure. As seen from Figures 4, direct realizationrequires in total of 2N delay lines, (2N 1)multiplications and 2N additions.Direct realization is very convenient for softwareimplementation and this is where it is most commonlyused.Biquad filter is a second order recursive linearfilter, containing two poles and two zeros. Biquad" is anabbreviation of "biquadratic", which refers to the factthat in the Z domain, its transfer function is the ratio oftwo quadratic functions:The number of forward coefficients Nx and thenumber of reverse coefficients Ny is usually equal and isthe filter order. The higher the filter order, the more theISSN (PRINT) : 2320 – 8945, Volume -1, Issue -4, 201311

ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE)carry-out represents bit one of the result, while the sumrepresents bit zero. Likewise, a half adder can be used asa 2:2 lossy compressor, compressing four possibleinputs into three possible outputs.Such compressors can be used to speed up thesummation of three or more addends. If the addends areexactly three, the layout is known as the carry-saveadder. If the addends are four or more, more than onelayer of compressors is necessary and there is variouspossible designs for the circuit: the most commonare Dadda andWallace trees. This kind of circuit is mostnotably used in multipliers, which is why these circuitsare also known as Dadda and Wallace multipliers.High-order recursive filters can be highly sensitiveto quantization of their coefficients, and can easilybecome unstable. This is much less of a problem withfirst and second-order filters; therefore, higher-orderfilters are typically implemented as serially-cascadedbiquad sections (and a first-order filter if necessary)[10].The two poles of the biquad filter must be inside the unitcircle for it to be stable. In general, this is true for allfilters i.e. all poles must be inside the unit circle for thefilter to be stable. The figure5 shows the block diagramof an IIR using EBL logic.Figure 7. 4:2 CompressorThe 4:2 compressor takes five equallyweighted inputs (CIN, X1, X2, X3, X4) and generate asum bit (S), a carry-bit (C) and a carry-propagate-bit(COUT). The 4:2 compressor array is formed by a seriesof 4:2 compressors cascaded together it together, is usedto perform column wise compression of the partialproduct.IV. RESULTS AND DISCUSSIONResults are simulated using modelsim6.2c andsynthesized using Xilinx ISE 9.9 . The simulation resultis shown in figure 8 in which the random inputs aregenerated from the test bench wave form and the inputis operated in IIR using EBL which tends to reduce thepower consumption using recovery logic. Figure 9shows the power calculation which shows 24mw ofpower consumption, whereas EBL based FIR dissipates39.1mW and achieves 36% improvement.A full adder is a 3:2 lossy compressor, it sums threeone-bit inputs, and returns the result as a single two-bitnumber; that is, it maps 8 input values to 4 outputvalues. Thus, for example, a binary input of 101 resultsin an output of 1 0 1 10 (decimal number '2'). TheISSN (PRINT) : 2320 – 8945, Volume -1, Issue -4, 201312

ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE)As a future enhancement power dissipation can befurther decreased by using different charge recoverylogic or by pipelining concept in IIR.VI. REFERENCESFigure 8. Simulation result of the 6tap 8bit IIRFigure 9. Power calculation[1]Jerry C. Kao, Wei-Hsiang Ma, Visvesh S.Sathe,and Marios Papaefthymiou, “Low-LatencyEnergy-Recovery” IEEE transactions on verylarge scale integration (vlsi) systems, vol. 20, no.6, june[2]S. Kim, C. Ziesler, and M. Papaefthymiou,“Charge-recovery computing on silicon,” IEEETrans. Comput., vol. 54, no. 6, pp. 651–659,Jun.2005.[3]S. Kim and M. Papaefthymiou, “Single-phasesource-coupled adiabatic logic,” in Proc. Int.Symp. Low Power Electron. Des., 1999, pp. 97–99.[4]S. Kim, C. Ziesler, and M. Papaefthymiou, “Atrue single-phase 8-bit adiabatic multiplier,” inProc. Des. Autom. Conf., 2001, pp. 758–763.[5]V. Sathe, J.-Y. Chueh, and M. Papaefthymiou,“A 1.1 GHz chargerecovery logic,” in Dig.Techn. Papers IEEE Int. Solid-State CircuitsConf. (ISSCC), 2006, pp. 1540–1549.[6]V. S. Sathe, J.-Y. Chueh, and M. C.Papaefthymiou, “Energy-efficient GHz-classcharge-recovery logic,” IEEE J. Solid-StateCircuits, vol. 42, no. 1, pp. 38–47, Jan. 2007.[7]Y. Moon and D.-K. Jeong, “An efficient chargerecovery logic circuit,” IEEE J. Solid-StateCircuits, vol. 31, no. 4, pp. 514–522, Apr. 1996.[8]L. B. Jackson, “An improved Martinez/Parksalgorithm for IIR design with unequal numbers ofpoles and zeros,” IEEE Trans. Signal Processing,vol. 42, pp. 1234–1238, May 1994.[9]A. Betser and E. Zeheb,”Reduced Order IIRApproximation of FIR Digital Filters," IEEETransactions on Signal Processing, Vol. 39, No.11, pp.2240-2544, Nov. 1991.[10]Yutaka Yamamoto, Brian D. O. Anderson,Masaaki Nagahara, and Yoko Koyanagi,”Optimizing FIR Approximation for DiscreteTime IIR Filters”,IEEE Transactions on SignalProcessing, VOL. 10, NO. 9,pp 273-276 , Sep.,2003[11]V. Sreeram and P. Agathoklis, Design of linearphase IIR filters via impulse-response gramians,V. CONCLUSIONSixth order IIR filter with Enhanced boost logic(EBL) has been designed which consumes less power.EBL uses an aggressively scaled near threshold supplyto perform logic evaluation. The EBL in IIR presentedin this project is aimed at pushing the iso-energyfrequency point higher than EBL in FIR while at sametime decreasing latency over head and consumes lessarea. The design of Sixth order IIR filter with EBL wasverified using Modelsim 6.2c and synthesized usingXilinx ISE 9.9 and the hardware results are obtainedusing FPGA Xilinx Spartan 3 kit. It dissipates only25mW of power which achieves 36.07% improvementcompared to previously reported FIR Filter (14 tap 8-bitFIR)ISSN (PRINT) : 2320 – 8945, Volume -1, Issue -4, 201313

ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE)IEEE Transactions on Signal Processing, vol. 40,pp. 389-394, Feb. 1992.[13][12] B. Beliczynski, J. Kale, and G. D. Cain,Approximation of FIR by IIR digital filters: actionsonSignalProcessing, vol. 40, pp. 532-542, Mar. 1992.M. F. Fahmy, Y. M. Yassin, G. Abdel-Raheem,and N. El-Gayed, Design of linear-phase IIRfiltersfromFIRspecifications,IEEETransactions on Signal Processing, vol. 42, pp.437-440, Feb. 1994. ISSN (PRINT) : 2320 – 8945, Volume -1, Issue -4, 201314

IIR filters are digital filters with infinite impulse response. Unlike FIR filters, they have the feedback (a recursive part of a filter) and are known as recursive digital filters. Figure 2 Block diagrams of FIR and IIR filters For this reason IIR filters have much better frequency response than FIR filters of the same order. Unlike FIR .

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