FPGA Synthesis & Prototyping - Ioe.nchu.edu.tw
FPGA Synthesis & 進計畫 DIP聯盟
本單元在DIP設計中的角色Writefunction spec.Writetechnical spec.Developarea/timing/powerconstraintsWrite RTLRun lintFPGA verification coverageDigital IP Prototyping雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
IP Prototyping SystemGPIODigital DataKey ��子系 許明華RAM,ROMFPGAInstrumentLED, LCDD/AAnalog 路與系統設計」教育改進計畫 DIP聯盟
IP Deliverables在DIP設計中的角色 作為DIP之FPGA合成與實現 評估DIP雛型電路之功能驗証完整度 評估DIP雛型電路之效能(Speed, Cost) � �科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Course Contents FPGA DeviceAltera, Xilinx (pp. 5 39) FPGA Design Flow & SynthesisISE, Quartus II (pp. 40 83) DIP Rapid Prototyping Platform (pp. 84 104)DIP Prototype System Measurement(pp.105 141) 雲林科技大學電子系 許明華Design Example(pp.142 ��統設計」教育改進計畫 DIP聯盟
FPGA Device FPGA Design Flow & Synthesis DIP Rapid Prototyping Platform DIP Prototype System Measurement Design Example雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
PLD Complexity Drives DesignMethodology ChangesIncreasing PLD ComplexityIncreasing Time-to-MarketPressures Drive c1985 Second-Generation Synthesis IP Megafunctions Synthesis Macrofunctions Equations Schematics19901995Time雲林科技大學電子系 許明華 �積體電路與系統設計」教育改進計畫 DIP聯盟
Altera Device Families Programmable Logic Families High & Medium Density FPGAs Stratix, APEX II, APEX 20K, & FLEX 10K Low-Cost FPGAs Cyclone & ACEX 1K FPGAs With Clock Data Recovery Mercury & Stratix GX CPLDs MAX 7000 & MAX 3000 Embedded Processor Solutions NiosTM, ExcaliburTM Configuration Devices EPC雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
APEX 20K Family Industry’s first MultiCore Architecture– Look-up table (LUT) logic– Product-term logic– Embedded memory Fabricated on SRAM Process– 2.5-V, 0.25/0.22-Micron Process– 1.8-V, 0.18-Micron Process雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
APEX MultiCore Architecture MultiCore Makes Million-Gate PLD Design Possible Facilitates Efficient IP Integration– Look-up Table Core– Product-Term Core– Memory Core雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Enhanced FastTrack Interconnect 4-Level FastTrack Interconnect Continuous Routing– Fast, Predictable Timing雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
APEX 20K Device Features雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
The Stratix Device FamilyFeature DescriptionProcess0.13-µm TechnologyDensity10,570 to 114,140 Logic Elements (LEs)PerformanceAverage 40% IncreaseEmbedded MemoryTriMatrix Memory Incorporating3 Block Sizes for Maximum Bandwidth& CapacityDigital SignalProcessing (DSP)FunctionalityEmbedded DSP Blocksfor Complex Arithmetic FunctionsClock ManagementAdvanced System Clock Control forOn- & Off-Chip Clock NeedsI/O Capabilities840-Mbps Differential I/O Signaling,High-Speed Interface Support,External Memory Interfaces & On-ChipTermination Technology雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Stratix Architecture OverviewLogic ArrayBlocks (LABs)Phase-LockedLoops (PLLs)DSP BlocksMegaRAM BlocksI/O Elements(IOEs)M512 RAMBlocks雲林科技大學電子系 許明華M4K �與系統設計」教育改進計畫 DIP聯盟
Advanced I/O Capabilities DifferentialDifferential && SingleSingle-EndedEnded I/OI/O StandardsStandards ort,PCMLPCML HSTL,HSTL,SSTLSSTL PCI,PCI,PCI-X,PCI-X,CompactCompactPCIPCI ExternalExternal MemoryMemoryDeviceDevice InterfacesInterfaces DDRDDRSDRAMSDRAM&&SRAMSRAM SDRSDRSDRAMSDRAM QDRQDR&&QDRIIQDRIISRAMSRAM ZBTZBTSRAMSRAM DDRDDRFCRAMFCRAM雲林科技大學電子系 許明華 High-SpeedHigh-Speed InterfaceInterfaceProtocolsProtocols 10-Gigabit10-GigabitEthernetEthernetXSBIXSBI POS-PHYPOS-PHYLevelLevel44 HyperTransportHyperTransport RapidIORapidIO(Parallel)(Parallel) TerminatorTerminatorTechnologyTechnology ermination ationTermination 計」教育改進計畫 DIP聯盟
TriMatrix Memory Structure雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
DirectDrive Technology Each Interconnect Line Drivenby Single Source– Consistent Access to Routing– Eliminates Congestion Uniform Routing ResourcesAcross Device– Ensures Blocks Can be Movedwithin or between Designs雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
DSP Block雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
DSP Block Modes雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
The Stratix Device FamilyDeviceLogicElements32x18M512Blocks128x36 4,096x144M4K MegaRAMBlocksBlocksTotal �林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Package Offerings & User Pin1923-PinBGABGAFBGAFBGAFBGAFBGAFBGAWire-Bond Flip-Chip Wire-Bond Flip-ChipFlip-ChipFlip-ChipFlip-Chip1.27 mm1.27 mm1.0 mm1.0 mm1.0 mm1.0 mm1.0 mm35 x 35 mm 40 x 40 mm 27 x 27 mm 29 x 29 mm 33 x 33 mm 40 x 40 mm 45 x 45 S80679EP1S120Vertical Migration Supported雲林科技大學電子系 �� DIP聯盟
Nios Flexibility & ScalabilityNetwork ProcessorSystemACEX EP1K100APEX EP20K200E500K GatesAvailableExcalibur EPXA10雲林科技大學電子系 許明華ESBESBESBESBESBESBESB150K GatesAvailableESB75K GatesAvailableESBDSPESBLow-CostEmbedded ProcessorHigh-PerformanceCustom DSPESB ESBExcalibur ARM922T �系統設計」教育改進計畫 DIP聯盟
Nios System ArchitectureInstr.NiosCPUOn-ChipDebug ter/SlavePortInterfacesUART 0Timer 0UART nTimer nSPI 0SPI nWait StateGenerationGPIO 0Off-ChipSoftware TraceMemoryData inMultiplexerMasterArbitrationDynamicBus Sizing雲林科技大學電子系 許明華Avalon Bus ModuleDMA 0GPIO nDMA 育改進計畫 DIP聯盟
ARM-Based Excalibur EmbeddedProcessorDual-PortRAM 200-MHzARM922T ProcessorUp to 3.3 Mbits ofMemoryUp to 1M Gates ofProgrammable Logic雲林科技大學電子系 許明華Single-PortRAMARM922TCorePLD Area 體電路與系統設計」教育改進計畫 DIP聯盟
Embedded Processor PLD ArchitecturePLLUARTExternalProcessor & AMSRAMEmbeddedStripeTimerI-CACHE InterruptD-CACHEWatchdog8 KbytesController8 Kbytes ARM922TDPRAMDPRAMDPRAMTimerEPXA132 Kbytes SRAM16 Kbytes DPRAMLEs4,160ESB (Bytes) 6.5KPLDLEs16,400ESB (Bytes)26KEPXA4LEs38,400ESB (Bytes) 40KEPXA10雲林科技大學電子系 許明華128 Kbytes SRAM64 Kbytes DPRAM256 Kbytes SRAM128 Kbytes 系統設計」教育改進計畫 DIP聯盟
Introduction to Xilinx Product FPGA : Spartan/XL, Spartan II,Spartan-IIE, Virtex, VirtexE,Virtex II,Virtex-II Pro CPLD : XC9500/XL, CoolRunner Software :Foundation4.2i, ISE Alliance4.2i, ISE 4.2 Core : IP, LogiCore, Alliance Core Technical Support : support.xilinx.com, FAEs雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Xilinx has a solution for every designDensity (gates)ASICsHigh endFPGAs200K – 10MMid 200KSpartanLow 5KServesCPLDPAL DesignsDensity, Performance, Cores & Memory雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Spartan-II ArchitectureDelay Lock Loop (DLL)Block MemoryLogic andDistributed RAMCL 系 許明華IOBDLL CLI/O Routing RingIOBR CLBAMIOBRAM CLB.IOBRAMCLBIOB.CLB RAM.SelectI/OTMTechnologyI/O Routing RingCL DLLTrue Dual-PortTM4K bit RAMIOB.ClockmanagementMultiply clockDivide clockDe-skew clockConfigurable Logic Block (CLB)IOBIOBDLL CLChip to BackplanePCI 33MHz 3.3VPCI 33MHz 5.0VPCI 66MHz 3.3VGTL, GTL , AGPChip to MemoryHSTL-I, HSTL-IIIHSTL-IVSSTL3-I, SSTL3-IISSTL2-I, SSTL2-IICTTChip to ChipLVTTL, �系統設計」教育改進計畫 DIP聯盟
Simplified CLB Structure雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
3 Level Memory Hierarchy雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Virtex-II Pro Platform FPGAMGTMGT 3.125 Gbps Multi-GigabitTransceivers (MGTs) Supports 10 Gbps standardsUp to 24 per device PowerPC 405 Core 300 MHz / 450 DMIPSPerformance Up to 4 per device雲林科技大學電子系 許明華Fabric IP-Immersion Fabric ActiveInterconnect 18Kb Dual-Port RAM Xtreme Multipliers 16 Global Clock ��路與系統設計」教育改進計畫 DIP聯盟
PowerPC 405Processor Local Bus (PLB)I-Side On-ChipMemory (OCM) I-Cache(16KB)Fetch &DecodeMMU(64 Entry TLB) TimersandDebugLogic D-Cache(16KB)Execution Unit(32x32 GPR,ALU, MAC)JTAGInstructionTrace 5-stage data path pipeline16KB D and I CachesEmbedded MemoryManagement UnitExecution Unit Multiply / divide unit 32 x 32-bit GPRDedicated on-chip memoryinterfacesTimers: PIT, FIT, WatchdogDebug and trace supportPerformance: 450 DMIPS at 300 MHz 0.9mW/MHz TypicalPowerD-Side On-ChipMemory (OCM)雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Virtex -II Family12 Devices, 10 Packages, 37 combinationsVirtex-IIXC2V XC2VPart Number 40 80LUTs FFs 512 1,024BRAM (Kb) 72 144Multipliers48DCM Units4488 92CS14488 雲林科技大學電子系 許明華XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V250 500 1000 1500 2000 3000 4000 6000 80003,072 6,144 10,240 15,360 21,504 28,672 46,080 67,584 93,184432 5767208641,008 1,728 2,160 2,592 1,024243240485696120144168888881212121292172 172172200 2643243924564844325286247208248248249121,104 ��體電路與系統設計」教育改進計畫 DIP聯盟684
XC9500XL Overview Superset of XC9500 CPLDOptimized for 3.3V systems 雲林科技大學電子系 許明華compatible levels with 5.0/2.5VHigh fMAX 200 MHzFast tPD 4 nsecBest ISP/JTAG supportBest pin-lockingAdvanced �與系統設計」教育改進計畫 DIP聯盟
Technology 雲林科技大學電子系 許明華Optimized for high speed 3.3V systemsLeading-edge FLASH technology 0.35um feature-size (0.25um Leff) 4 layers of metalSuperior reliability Reprogramming endurance 10,000 Charge retention 20 yearsFast programming �電路與系統設計」教育改進計畫 DIP聯盟
High Level Architecture雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
XC9500XL 88Usable Gates800160032006400t PD (ns)4556f MAX �學電子系 體電路與系統設計」教育改進計畫 DIP聯盟
Higher Density Enables NewApplicationsSpartan-IIESystem Gates250KSpartan-II250k unit100KSpartan-XL40K30KHDLCPCIPCIMIPS3232-bit, Bridge3333-MHzPCI64 BitPCIReedSolomonEncoderATMIMAEthernetMACVideo LineBufferCable ModemGraphics CardOffice NetworkingSet-Top BoxEmbedded µP AppsFIFOs UARTsPALs1998雲林科技大學電子系 �積體電路與系統設計」教育改進計畫 DIP聯盟
Spartan-II Family OverviewDeviceXC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S2004329721728270038885292Block RAM Bits16,38424,57632,76840,96049,15257,344Block RAM Qty.468101214Max. User 6FG256FG456FG456FG456Logic CellsPackage雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
FPGA Device FPGA Design Flow & Synthesis DIP Rapid Prototyping Platform DIP Prototype System Measurement Design Example雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
FPGA Design Flow and SynthesisSpecificationSystem-Level SimSystemC ModelDevice SelectionDesign EntryC/C Matlab / SimulinkXilinxCoreGenLogiBoxIPFunction SimSimulationModel �大學電子系 HDLFSMSchematicCadence Verilog-XLSynopsys VCSiFPGA Compiler IIFPGA lifyDesign EntryLPMMegaCoreFPGA Express 教育改進計畫 DIP聯盟
FPGA Design Flow and SynthesisP&RTiming SimP&RConstraints,FloorplaningPlacement & RoutingBack Annotate Routing DelayCadence Verilog-XLTimingModel &TestBenchSynopsys VCSiPrototypingFittingFittingBack Annotate Routing DelayFittingConstraintsDebussyModelSimThird Party PrototypingPrototyping DevelopmentProgramming& DebugHardware DebuggerJTAG Programmer雲林科技大學電子系 許明華ChipScope ILAProgramming& �� DIP聯盟
Xilinx ISE雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
ISE Design Flows雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Project Navigator雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Creating New Projects雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Adding Source Files雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Creating HDL Source雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
HDL Wizard雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
HDL WizardConfirm information雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Setting Implementation Option雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Setting Synthesis Options雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Accessing Advanced Options雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Initiating a Design Flow雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Accessing Reports雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Static Timing Report雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Proactive Timing Closure雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Xilinx Synthesis Technology雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
HDL Bencher雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
HDL In, Test Bench Out雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Simulating with TestbenchWaveforms雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Simulating with TestbenchWaveforms雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
ModelSim HDL Simulator雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Using I/O Buffers雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Configuration Download雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Altera Quartus II雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Design Methodologies Quartus supports three common design methodologies: Top-down Create a top-level of the design first, and then break downthe design into lower-level design blocks. Bottom-up Begin by creating the lower-level design blocks first and thenstitch together the design at the top-level. Middle-out Start in-between Top-down and Bottom-up designmethodologies雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
PLD Design Flow(1)雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
PLD Design Flow(2)雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Design Entry Multiple design entry methods Quartus Block/Schematic Editor Text Editor AHDL, VHDL, Verilog Memory Editor Hex, Mif Third party EDA tools EDIF HDL VQM Add flexibility and optimization to the design entry process by: Mixing and matching design files Using LPM and Megafunctions to accelerate design entry教育部顧問室雲林科技大學電子系 �教育改進計畫 DIP聯盟
Design Entry FilesQuartusText EditorQuartusBlock EditorQuartusMemory SchematicTop-level design filescan be .bdf, .tdf, .vhd,.vhdl, .v, .vlg, .edif erated within Quartus雲林科技大學電子系 許明華.v, .vlg,.vhd, Imported from教育部顧問室third-party �改進計畫 DIP聯盟tools
Main Toolbar and Modes雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
New Project WizardWhat is the workingdirectory for this projectWhat is the name of this projectWhat is the name of the top-leveldesign entitiy in your project雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
New Project Wizard雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Set Chips & DevicesDevice Select雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Set User Libraries雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
CompilerClick this button to execute compilerShow thesection ofcompilersummaryWhen compilation was successfulwill appear this messageCompiler Message雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Timing AnalysisFeatures Quartus II has built in static timing analysis Single clock timing analysis– fmax (maximum clock frequency)– Tsu, Th, Tco (setup time, hold time, clock-to-outtime)– Optional system fmax reporting Multi-clock analysis– Allows analysis of multiple synchronous clocks– Slack analysis is used雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Timing Analysis雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
fmaxThe worst fmax is listed on the top.Select fmax雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Locate Delay Path in Floorplan雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
DownloadClick this button to open programmerMake sure Type is“ByteBlasterMV”Make sureis “JTAG”雲林科技大學電子系 許明華Select .sof file �路與系統設計」教育改進計畫 DIP聯盟
DownloadWhen it show 100% meaningdownload finishedEnable this field雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
FPGA Device FPGA Design Flow & Synthesis DIP Rapid Prototyping Platform DIP Prototype System Measurement Design Example雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
IP Rapid Prototype Platform Altera Demo Board Xilinx Demo Board FPGA µp Demo Board Application Specific Demo Board ARM SoC Development Platform雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Nios Board (Altera)PIO buttonsFlashConfigurationControllerSRAMseven segmentJTAG Headeruart雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
EPXA10 Development Board (Altera)BOOT FLASHJP40POWERRS 232Flash MemJTAGUARTEthernetPCI Connector雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
EPXA10 Development Board Features Platform for Device Evaluation & Application DevelopmentMemory Support1. SDR SDRAM: 256 Mbytes Flexible Clocking 50-MHz Embedded Stripe Clock External Clock Generator Can Be UsedDedicated Stripe PLLs for Frequency SynthesisPLD Clocks 2. Flash: 16 MbytesDedicated Crystals for Each of Four PLD PLLsApplication Support Two UARTsByteBlasterMV JTAG ConnectorMulti-ICE & Trace Port ConnectorsEthernet PHY雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
EPXA10 Development Board Features PCI Two 3.3-V 33-MHz PCI Connectors Provided for Off-the-ShelfApplicationsUser Interface1. Eight LEDs 2. Four Push-Buttons3. Nine-Position DIP Switch Power Supply 3.3-Volt DC Supply 1.8-V Generated1.25-V Generated for VREF & VTTATX Power Supply 雲林科技大學電子系 許明華Required for PCISame Voltage Regulation as 3.3-V DC �系統設計」教育改進計畫 DIP聯盟
Altera IP Development KitszzzzzzzzAPEX DSP Development KitAPLEX 20KE PCI Development KitSOPC Development BoardDIGILAB 10K*240 Development BoardPROC20K Prototyping BoardBluetooth Prototype BoardConstellation 20K Prototype BoardPCISYS Data Acquistition and Processing PCIBoardz Megalogic 2A15 Development Boardz XT1000 Device Emulation Kit雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
MicroBlaze Kits with Boards (Xilinx)雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
MicroBlaze IP PeripheralsDevelopment Kit MicroBlaze CPU OPB Arbiter Watchdog Timer/Timebase Timer/Counter Block Interrupt Controller SRAM Controller Flash Memory Controller ZBT Memory Controller BRAM UART Lite GPIO SPI Master and Slave雲林科技大學電子系 許明華Additional Peripherals UART 16550 UART 16450 IIC Master & Slave Ethernet 10/100 MACFuture Peripherals ATM Utopia Level 2 SDRAM �統設計」教育改進計畫 DIP聯盟
The FPGA µp Demo BoardDRAM Moduleµp 8051or AVRA/D, D/A ModuleSRAM Module雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
The Hardware Module of FPGA µp Demo Board8051 or AVR雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
Application Specific Demo Board (Natl. Yunlin Univ.)ADC ICImage Sensor InputPowerLEDFPGA I/O PinUARTDIP Sw.JTAGFPGA I/O Pin雲林科技大學電子系 許明華E2PROMFPGA I/O �統設計」教育改進計畫 DIP聯盟
ARM SoC Development PlatformARM IntegratorARM 720TCore moduleXilinxXCV2000EAPASIC Development PlatformLogic module雲林科技大學電子系 �與系統設計」教育改進計畫 DIP聯盟
ARM Integrator/AP System controller (FPGA)Clock generatorFlash Memory(32MB)Boot RomSRAM(512k)System expansion(CM,LM)PCI Interface, EBI Interface雲林科技大學電子系 ��路與系統設計」教育改進計畫 DIP聯盟
System ArchitecturePeripheral input/outputSystem busSystem controllerFPGAPCI HostBridgeEBIHDRCore ModuleconnectorsFlashStandardPCIEXPLogic ModuleconnectorsSlotsGPIOPCI PCIbridge雲林科技大學電子系 ��計畫 DIP聯盟
System controller FPGASystembusExtrnalSystem busInterfaceSystem bus (AHB) PCI bridgecontrollerArbiterStaticmemorycontrollerPCI bridgeLocal busInterfacePCI Host BridgeExternalBusInterfaceFlash,SSRAM and ROMIAHB/APBbridgePeripheral bus (APB)Counter/timersReal timeclockGPIOUART *2KMIPeripheral input/output雲林科技大學電子系 許明華LED/switchstatus pts �與系統設計」教育改進計畫 DIP聯盟
Core Module(CM720T)ARMFPGA雲林科技大學電子系 許明華SDRAM (DIMM) 256KB to 1MB Synchronous SRAM SDRAM DIMM socket (up to 256MB) AMBA system bus interface to platformboard Clock generators Reset controller JTAG interface to Multi-ICE �設計」教育改進計畫 DIP聯盟
CM System ArchitectureSSRAMClockgeneratorStatus / ControlregisterResetcontrollerMemory busARM coreSDRAMSSRAMController(PLD)SDRAMcontrollerSystem busbridgeFPGASystem busMulti-ICE雲林科技大學電子系 許明華System bus ��體電路與系統設計」教育改進計畫 DIP聯盟
Logic Module(LM-XCV600E ) 1MB ZBT SRAM 9 General-purpose LEDs 8 General-purpose switches Clock generators Push button FPGA programming via Multi-ICE ��系 �與系統設計」教育改進計畫 DIP聯盟
LM System �電子系 許明華Interface module connectorModule/motherboard connectorsLA �與系統設計」教育改進計畫 DIP聯盟
System ArchitectureCore ModuleSys ontrollerInterruptControllerAPB BusFPGASSRAM雲林科技大學電子系 許明華AP ModuleSSRAM(512k)AHB BusLogicModulePCI SlotARM720TPCI/CPCIBridgeROMSDRAMCntlSSRAMCntlPCI SlotSSRAMASB/PCIBridgeSDRAMPCI 教育改進計畫 DIP聯盟
True Dual-PortTM 4K bit RAM Clock management Multiply clock Divide clock De-skew clock Chi p to Back lane PCI 33MHz 3.3V PCI 33MHz 5.0V PCI 66MHz 3.3V GTL, GTL , AGP Chip to Memory HSTL-I, HSTL-III HSTL-IV SSTL3-I, SSTL3-II SSTL2-I, SSTL2-II CTT Chip to Chip LVTTL, LVCMOS SelectI/OTM Technology Logic and Distributed RAM 4Kx1 2Kx2 1Kx4 512x8 .
MOE (MBBS) 2072 Topper: IAAS - Ag./Vet. Entrance 2072 Bikalpa Bhatta IOM (MBBS) 2072 Sujan Pokhrel IOE 2072 Sushil Chapagain IOE 2072 Deepak Bhattarai IOE 2072 Akash Kalwar IOE 2072 Srijana Shrestha AFU 2072 Binita Sharma IOE 2073 Shambhav Kharel IOE / 2073 Deepak Neupane IOE, WRC / 2073 Dipesh Gautam IOE, WRC / 2073 Silaj Baral IOE, WRC / 2073 .
In nitely often equal reals x;y 2!! are in nitely often equal (ioe) i 91n : x(n) y(n): A !! is an in nitely often equal (ioe) family i 8x 9y 2A : y is ioe to x: A !! is a countably in nitely often equal (ioe) family i 8fx i ji !g9y 2A : y is ioe to every x n: Yurii Khomskii (Hamburg University) I.o.e.-trees add Cohen reals Arctic III 2 / 22
PSI AP Physics 1 Name_ Multiple Choice 1. Two&sound&sources&S 1∧&S p;Hz&and250&Hz.&Whenwe& esult&is:& (A) great&&&&&(C)&The&same&&&&&
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The program, which was designed to push sales of Goodyear Aquatred tires, was targeted at sales associates and managers at 900 company-owned stores and service centers, which were divided into two equal groups of nearly identical performance. For every 12 tires they sold, one group received cash rewards and the other received
Step 1: Replace ASIC RAMs to FPGA RAMs (using CORE Gen. tool) Step 2: ASIC PLLs to FPGA DCM & PLLs (using architecture wizard), also use BUFG/IBUFG for global routing. Step 3: Convert SERDES (Using Chipsync wizard) Step 4: Convert DSP resources to FPGA DSP resources (using FPGA Core gen.)
College"Physics" Student"Solutions"Manual" Chapter"6" " 50" " 728 rev s 728 rpm 1 min 60 s 2 rad 1 rev 76.2 rad s 1 rev 2 rad , π ω π " 6.2 CENTRIPETAL ACCELERATION 18." Verify&that ntrifuge&is&about 0.50&km/s,∧&Earth&in&its& orbit is&about p;linear&speed&of&a .
In this thesis, FPGA-based simulation and implementation of direct torque control (DTC) of induction motors are studied. DTC is simulated on an FPGA as well as a personal computer. Results prove the FPGA-based simulation to be 12 times faster. Also an experimental setup of DTC is implemented using both FPGA and dSPACE. The FPGA-based design .
