Design Of Voltage Boosting Rectifiers For Wireless Power Transfer Systems

of a full-wave rectifier is shown in Fig. 2.2. A full-wave rectifies converts 100% of the input AC signal to DC. Vac Vrect Fig. 2.2: Full-wave rectifier If VMAX and IMAX are the maximum voltage amplitude and the maximum current amplitude of the sinusoidal wave, then the average output voltage and output current are given by, VAV 2*VMAX / π 0.636*VMAX (6) IAV 2*IMAX / π 0.636*IMAX (7) The efficiency of a full-wave rectifier is defined as the ratio of the output DC power to the input AC power. The output power is given by, PDC 2*VMAX*IMAX/(π)2 (3) PAC 2*(VMAX/2)*(IMAX/2) (4) The input power is given by, The efficiency (PDC/PAC) is given by, η 2*(2/π)2 0.812 (5) The efficiency of a full wave rectifier is 81.2%, which is twice the efficiency of a half-wave rectifier. 7

2.3 Rectifier Architectures Rectifier architectures working at low-input voltages are explored in this literature. Mazzilli, Francesco, et al. discusses four standard architectures of rectifier circuits [6]. Fig. 2.3 (a) is a standard NMOS bridge rectifier. For rectification, this architecture requires the input voltage to be twice the threshold voltage of the transistors, to turn on the rectifier. This limits the input voltage to be higher than twice the threshold, and to rectify voltages lower than that, devices with lower threshold voltage are to be implemented. Fig. 2.3 (b) is a gate cross-connected bridge rectifier, where the gates of the NMOS transistors are cross-connected. Cross-connecting the gates increases the gate-source voltage of the transistors, thereby reducing the voltage required to turn the transistor on, i.e. the threshold voltage. Fig. 2.3: Rectifier topologies: (a) NMOS differential-drive bridge rectifier, (b) NMOS differentialdrive gate cross-connected bridge rectifier, (c) NMOS doubler, (d) NMOS-PMOS differential-drive gate cross-coupled bridge rectifier [6]. Fig. 2.3 (c) is a standard voltage doubler circuit which rectifies the input AC voltage and doubles the voltage level. The transistors act as switches charging the capacitor C to the input voltage during the positive half cycle of the input. During the negative half cycle, the capacitor C 8

gets charged to twice the input voltage and discharges through M10 thereby charging the output capacitor to twice the input voltage. The drop across the transistors is required to be as low as possible to achieve higher efficiencies. Multiple stages of the voltage doubler can be cascaded to achieve a higher voltage conversion efficiency (VCE), which is the ratio of the output DC voltage to the input AC RMS voltage. Fig. 2.3 (d) is a gate cross-coupled bridge rectifier with NMOS and PMOS transistors. The usage of both NMOS and PMOS improves the efficiency as the NMOS-PMOS pairs act as switches in both the positive and negative half-cycles of the input, instead of just one half-cycle. This helps in yielding a DC voltage higher than the other four architectures. The drawback of using an NMOS-PMOS rectifier is, a reverse current flows from the output to input when the input voltage while oscillating, falls below the output DC voltage. This causes the efficiency of the rectifier to drop. To avoid this effect, the NMOS-PMOS rectifier circuits are accompanied by a control circuit. A simple control circuit has been proposed in [7]. Two NMOS-PMOS inverters are connected to the PMOS switches to turn the diodes off when they start conducting in the reverse direction (Fig. 2.4). Fig. 2.4: Control circuit proposed in [7] 9

Fig. 2.5: N-Stage voltage doubler proposed in [8] [8] presents a multi-stage NMOS-based voltage doubler circuit. The circuit is shown in Fig. 2.5. A detailed analysis of the characterization of an NMOS-based voltage doubler is discussed in the section II of the [8]. The design has been optimized for two cases: maximum voltage and maximum efficiency. The optimum transistor sizing and the optimal number of stages yield an efficiency of 17.6% for the maximum voltage approach and an efficiency of 30.5% for the maximum efficiency approach. While designing a multi-stage rectifier for a low-power system, it is important to consider the sizing of the devices, the number of stages and the efficiency. A review on voltage boosting circuitry for low-power transfer applications is presented in [9]. It outlines various contemporary boost rectifier architectures designed for low-power applications [10]-[14]. Various NMOS-based bridge rectifiers [12], [13] and diode-based architectures [10], [11], [14] have been discussed. A novel bridgeless boost rectifier is proposed in [10]. The circuit is designed using diodes arranged as shown in Fig. 2.6. The bridgeless structure has a high output current ripple. To solve this issue, a bridgeless interleaving boost converter is proposed in [11] (Fig. 2.7). Compared to the 10

boost converter in [10], the total loss observed in the bridgeless interleaving boost converter is lower than the standard bridgeless boost converter. Fig. 2.6: One-stage bridgeless boost converter proposed in [10] An inductive power management system has been proposed in [12]. It has a rectifier constructed using NMOS transistors connected to form a rectifier. The maximum efficiency reported for 10mW is 77%. A three-stage full-wave rectifier is designed for an energy harvesting system in [13]. The architecture is shown in Fig. 2.8. The capacitor banks CC are used to tune the rectifier to the antenna. The NMOS rectifier achieves an efficiency of 31.5% for -15dBm input power. Fig. 2.7: Improved bridgeless boost converter proposed in [11] The architectures discussed above achieve efficiencies less than 80% for an input power less than 10mW. There is a need to obtain higher efficiencies for lower input voltages, as the target 11

applications like the optogenetic implants operate with voltages below 200mV. Fig. 2.8: Three-stage rectifier proposed in [13] Another important design parameter of a rectifier is its frequency range of operation. According to [15] and [16], the optimum frequency for inductively-coupled WPT systems is in the 100MHz frequency range, in the presence of a biological tissue. Khan, Mohd Tauheed et.al. presents a rectifier (Fig. 2.9) designed in the 32nm CMOS process which uses a bootstrap capacitor in the circuit to reduce the forward voltage drop [17]. Fig. 2.9: Rectifier with bootstrap capacitor proposed in [17] 12

As NMOS transistors have low input impedance, a capacitor is connected at the input to increase the input impedance, thereby turning the NMOS transistor for a lower voltage. The rectifier is found to be stable up to the 40 MHz – 50 MHz frequency range. The efficiency of the rectifier is observed to drop rapidly for frequencies above 50 MHz. Fig. 2.10: Block diagram of the three-stage voltage multiplier used in [18] Fig. 2.11: First stage of the voltage multiplier used in [18] Asmeida, Akrem, et al. talks about a three-stage voltage multiplier for an RF energy harvesting circuit [18]. The rectifier model uses Schottky diodes for rectification. The block diagram of the three-stage voltage multiplier is shown in the Fig. 2.10. The received signal from the UWB antenna is fed to the rectifier through a matching circuit. Each stage of the three-stage 13

rectifier is a voltage multiplier shown in Fig. 2.11. The rectifier is observed to be operating in 1.8 GHz to 2.4 GHz. The rectifier achieves a maximum efficiency of 86% for an input voltage of 3.75V. Schottky diodes have very low threshold voltages, and hence are used for faster switching [19]. The prime challenges in designing a rectifier for a biomedical implant system are The efficiency. The output voltage yield. The minimum input voltage the rectifier can convert. The operating frequency ranges. 14

CHAPTER 3 DESIGN ARCHITECTURE Considering the design challenges mentioned in the previous chapter, a multi-stage rectifier design with Schottky diodes is presented. 3.1 Schottky Diode Unlike a standard diode with a semiconductor-semiconductor junction, Schottky diodes have a metal-semiconductor junction which allows them to turn-on at a much lower voltage, which is usually in the range of 100 mV – 700 mV. Looking at the energy band diagrams of p-n junction and the metal-semiconductor Schottky junction from figures 3.1 and 3.2 [20], the depletion region in the Schottky contact is much lower than the p-n junction contact. Due to the lower potential barrier, Schottky diodes have a lower threshold voltage and hence reduces the power consumption. Fig. 3.1: Energy band-diagram of a p-n junction [20] 15

Fig. 3.2: Energy band-diagram of a metal-semiconductor Schottky contact [20] The I-V characteristics of a Schottky diode with non-ideal behavior are given by [21], I IS [exp(qVD)/nKT)-1] (5) where IS is the reverse saturation current, q is the electronic charge, VD is the voltage across the diode, n is a dimensionless parameter called the ideality factor, k is the Boltzmann constant, and T is the absolute temperature. Fig. 3.3: I-V Characteristics of a Schottky diode Fig. 3.4: I-V Characteristics of a MOSFET The I-V characteristics curve of a 0.5µm CMOS process Schottky diode is shown in the Figure 3.3. The diode starts conducting for a voltage above the forward voltage which is close to 16

100 mV. The I-V characteristics of a 0.5µm CMOS process MOS transistor can be seen in Figure 3.4. From the figures, the forward/threshold voltage of a Schottky diode is lower than a MOSFET by 500 mV. The forward voltage (Vf) of the Schottky diode varies with the technology process. The Vf of the Schottky diode in the 0.5µm CMOS process is 0.142V (Fig. 3.3). The threshold voltage of the Schottky diode also depends upon the sizing. The size is characterized by the length and width. A longer channel (longer width) increases the threshold voltage, as the depletion barrier increases. So, the width of the diode has to be adjusted so that the diode turns on for a minimum threshold voltage. 3.2 Proposed Architecture The proposed rectifier is a 10-stage voltage-doubler. Figure 3.5 shows the architecture of the rectifier. The rectifier is built using 20 Schottky diodes and 20 capacitors. The characterization of 10-stages is discussed in section 3.2.3. Fig. 3.5: Rectifier Architecture 17

3.2.1 One-Stage Architecture To understand the working principle of the rectifier, it is important to understand the working of the first single-stage of the rectifier (Fig 3.6). Fig. 3.6: One-Stage Architecture working principle Consider an AC signal Vmcosωt where Vm is the amplitude, is given as an input to the rectifier. During the negative half cycle, the diode D1 is turned on, D2 is turned off and the capacitor C1 is charged to an amplitude of Vm. During the next positive cycle, the diode D1 is turned off, D2 is turned on, and the capacitor C1 gets charged to a voltage 2Vm and discharges through D1 thereby charging C2 to a voltage 2Vm. This is in an ideal scenario without considering the voltage drop across the Schottky diode. Considering the forward voltage of the diode, the output voltage of one stage is given as, Vout 2*(Vm – Vdiode) (6) where Vdiode is the forward voltage of the Schottky diodes. 3.2.2 10-Stage Architecture The single stage discussed above is cascaded with 9 more single-stages to form a multistage system. The voltage is doubled at the end of each stage, and the at the end of 10-stages, the equivalent voltage will be 2*10 times the input voltage. Fig. 3.7 shows the 10-stage architecture. For an input voltage of say Vm, the voltage output at 10-stages will be 2*10*(Vm – Vdiode). 18

Fig. 3.7: 10-Stage architecture working principle To generalize the output voltage for N-stages, the output DC voltage can be defined as, VDC 2*N*( Va – Vdiode) (7) 3.2.3 10-Stage Characterization Maximum output voltage is a prime characteristic for a voltage boosting rectifier. Ideally, the output voltage increments as the number of stages are increased. But, as the number of stages are increased, the total power consumed also increases, as the components in each stage consume a certain amount of power. The power consumed through each stage is the power consumed by the diodes and the capacitors. Fig. 3.8 shows the output voltage and power consumption of the circuit for 10 and 12 stages. From the figure, the output voltages for the 10 and 12 stages are comparable, but the power consumption in the 12-stage design is greater than the 10-stage design. It shows that, as the number of stages is increased, the output voltage surely increases, but the energy lost through the stages also increases. A trade-off between the power consumption and the number of stages has been made to produce the required output with minimum losses. 19

Fig. 3.8: Power consumption with output DC voltages for different stages [9] 20

CHAPTER 4 SIMULATION RESULTS The circuit has been designed and simulated using the Cadence Virtuoso Custom IC Design Tool in the 0.5µm CMOS process and the 130nm CMOS process libraries. The performance of the circuit varies from process to process as the properties of the components change with the process. As the 130nm CMOS process has smaller process parameters than the 0.5µm CMOS process, performance variation of the circuit in both the processes is expected. The circuit performance has been tested in terms of output voltage boost, operating frequency range, voltage conversion efficiency and power conversion efficiency. 4.1 0.5µm Process The results of the proposed rectifier in the 0.5µm CMOS process are published in [9]. The I-V characteristics of the Schottky diode in this process are shown in the Figure 4.1. The forward voltage of the Schottky diode is about 160 mV in this process. Fig. 4.1: 0.5μm Schottky Diode I-V Characteristics [9] 21 Fig. 4.2: Output DC voltages for each stage [9]

Fig. 4.3:Vdc vs Frequency [9] Fig. 4.4:Vin vs VCE [9] The len

Rectifiers are divided into two types: Half-wave rectifiers and full-wave rectifiers. 2.1 Half-Wave Rectifier A half-wave rectifier passes only one-half of the sine wave to convert it to a DC signal. A half-wave rectifier built using diodes is shown in the Fig 2.1. A single diode is used in a half -wave rectifier.