Volume 3, Issue 2, March – April 2014 ISSN 2278-6856 .
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.comVolume 3, Issue 2, March – April 2014ISSN 2278-6856Performance of Various Sense AmplifierTopologies in sub100nm Planar MOSFETTechnologyParita Patel1, Sameena Zafar2 and Hemant Soni31Rajiv Gandhi Proudyogiki Vishwavidyalaya, Patel College OfScience & Technology, Ratibad, 462044,India2,3Patel College Of Science & Technology, Rajiv Gandhi ProudyogikiVishwavidyalaya, Ratibad, 462044,IndiaAbstract:Performance of sense amplifiers hasconsiderable impact on the speed of caches used inmicroprocessors. A small difference in voltage level of bitlines of memory cell is amplified by the sense amplifier. Dueto higher density of memory, the bit line capacitanceincreases and that limits the speed of voltage senseamplifiers. Current sense amplifier which is independent ofbit line capacitance is a good choice in high density RAM.Under the aegis of the Moore's law, we have to deal with itsdarker side with problems like leakage and short channeleffects. Once we go beyond 45nm regime, process variationshave emerged as a significant design concern. Processvariation induced mismatches in sense amplifiers lead tosignificant loss of yield for that we need to come up withprocess variation tolerant circuit styles and new devices.Multiple sense amplifier techniques - in addition to theconventional voltage sense amplifier. It analyzes currentsense amplifier, charge transfer sense amplifier as wells ascurrent latched sense amplifier and compares them in speedand power consumption to the voltage sense amplifier. Allthe sense amplifiers are also analyzed in the presence ofprocess variations and some reported FinFET basedtechniques are implemented in planar MOSFET technologyto combat mismatch. All circuits are designed andsimulated in a 45nm process technology using Ng-Spicecircuit simulator.Keywords: Delay, Power dissipation, Sense amplifiersVSA,CSA,CTSA.1. INTRODUCTIONStatic Random Access Memories (SRAMs) are animportant component of microprocessors and system-onchips. SRAMs are used as large caches in microprocessorcores and serve as storage in various system-on-chip likegraphics, audio, video and image processors. SRAMsused in high performance microprocessors and graphicschips have high speed requirements. At the same time,SRAMs used in application processors which go intomobile, handheld and consumer devices have very lowpower requirements. Since SRAMs serve as large storageon these chips, it’s very important to get maximumdensity out of these. Traditionally a large number ofSRAM bit cells, up to 1024 in some cases, are connectedto a common bit-line to get the highest density and arrayefficiency. This results in a large capacitance on the bitlines which necessitates using differential senseVolume 3, Issue 2 March – April 2014amplifiers for speed reasons. Sense amplifiers detect thedata being read by sensing a small differential voltageswing on the bit-lines rather than waiting for a full railto-rail swing. Depending on the performance and powerrequirements, it’s very important for the sense amplifiersto operate fast and do so while burning a minimumamount of power. The large bit-line capacitance is a bigperformance bottleneck. Conventional Voltage SenseAmplifiers need a minimum amount of differentialvoltage to be developed on the bit-lines for reliableoperation. The amount of time required to develop thisdifferential voltage is linearly proportional to bit-linecapacitance. The dynamic power consumed in precharging the bit-lines increases with the differentialvoltage that needs to be developed. Low powerrequirements of mobile and embedded chips require senseamplifiers which burn less power than the traditionalvoltage sense amplifier techniques.From the past few decades, the growth of the electronicsindustry is very fast and also the use of integrated circuitsin computing, telecommunications and consumerelectronics. In the 1958, there was only a single transistoron the chip called single transistor era and at present dayULSI (Ultra Large Scale Integration) systems with morethan 50 million transistors in a single chip. Today thesize of the memory is decreasing and the storing capacityis increasing. As the storing capability increased, the timeresponse for the data writing and reading from thememory should be very fast. The speed gap between theMPUs and memory devices has been increased in the pastdecade. The MPU speed has improved by a factor of 4 to20 in the past decade. On the other hand, in spite of theexponential progress in storage capacity, minimum accesstime for each quadrupled storage capacity has improvedonly by a factor of two.In the memory, it is common to reduce the voltage swingon the bit lines to a value significantly below the supplyvoltage. This reduces both the propagation delay and thepower consumption. Noise and other disturbances may beoccurred in the memory array, for this sufficient noisemargin is obtained even for these small signal swings.During the interfacing of the memory to the externalPage 42
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.comVolume 3, Issue 2, March – April 2014ISSN 2278-6856field, the amplification of the internal swing is required.This is achieved by the sense amplifiers. Design of a highperformance and efficient sense amplifier is veryimportant to design SRAMS but with increasingparameter variations, the developing of a reliable and fastsense amplifier is a big challenge in itself. Senseamplifiers play a major role in the functionality,performance and reliability of memory circuit.In a large embedded SRAM there may be many thousandsof sense amplifiers and each one of them will have a veryhigh yield requirement for the product to have a goodoverall yield. A single failing sense amplifier implicatesthe whole memory but as technology becomes more andmore advanced and Moore's law still governing thesemiconductor industry, the control of process variationsand manufacturing uncertainty becomes more and morecritical. The sense amplifier performance degradation dueto process variation and resulting yield loss is morepronounced than before. It is important for the designer tobe able to understand mismatch effects, since sensingshould be done as fast as possible, subject to sensitivityconstraints imposed by the parameter variations inherentin fabrication processes. Despite careful designing, smallvariations in parameters like threshold voltage andeffective channel length due to process operatingconditions [4], lead to an input offset which affects theperformance of the sense amplifier. The analysis of thesevariations provides a good understanding of the impact ofdevice mismatches in differential sense amplifier. Toguarantee reliability of the sense amplifiers either wehave to come up with new process variation tolerantcircuit styles, techniques or the replacement ofconventional bulk type MOSFET.structure and organization. Reliability and powerdissipation are large concern of the semiconductormemory designer. The propagation delay and the powerconsumption of the memory cell can be reduced bylowering the voltage swing on the bit lines. By reducingthe voltage on the bit lines there will be a very smalldifference between bit lines and it will be very difficult todifferentiate logic ‘0’ and logic ‘1’ on the bit lines. Thisproblem is eliminated and better results are achieved bythe Sense Amplifier.2.1 Static Random Access Memory (SRAM)The most compelling issue in designing large memoriesis to keep the sizes of the cell as small as possible, thisshould be done so that other important design qualitiessuch as speed and reliability do not highly affected. Thereare different type of memories like read only, volatile,non-volatile, and read-write memories. Here, only SRAMis discussed. RAM is a volatile memory. The data storedin this memory is lost when the power supply is switchoff. It retains its memory patterns for as long as power isbeing supplied. Basically, RAM can be classified into twocategories:1. Static RAM (SRAM)2. Dynamic RAM (DRAM)SRAM utilizes a flip flop mechanism. It does not need torefresh as DRAM. A block diagram of RAM is shown inFig.1.At the intersection of row line (word line) andcolumn line (bit line) is a memory cell. Some peripheralcircuits likeThis work explores multiple sense amplifiers – CurrentSense Amplifier (CSA), Charge Transfer Sense Amplifier(CTSA), and compares them in speed and power to theVoltage Sense Amplifier (VSA). A current senseamplifier operates by sensing the bit cell current directlyrather than waiting on a differential voltage to develop onthe bit-lines. The operation of charge transfer senseamplifier is based on charge sharing from the highcapacitance bit-lines to the low capacitance senseamplifier nodes. This also is presents the design of a sixtransistor bit cell which is used in all the experiments. Allwork is done in 45nm CMOS technology with a 1Vsupply. The sense amplifier designs are evaluated in a128x128 SRAM array with 128 bit cells on the word-lineand 128 bit cells connected to the bit-line.2.THEORYModern digital systems require the capability of storinglarge amount of data information with high speed.Memories circuits or systems store digital information inlarge extent. Memory circuits are of different types like,SRAM, DRAM, ROM, EPROM, EEPROM, Flash andFRAM, each form has a different cell design, the basicVolume 3, Issue 2 March – April 2014Figure 1 Block diagram of RAM [5].latches, decoders and buffers are used to select particularmemory cell from the array provided row and columnaddresses. Sense amplifiers are included for the full swingoutput voltage level after reading the data on memorycells.Page 43
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.comVolume 3, Issue 2, March – April 2014ISSN 2278-68562.1.1 6T SRAM cellof the node by transistor M4. Due to the fast dischargingof the Q, a value ‘0’ will be set at this node.2.2 Sense Amplifiers2.2.1 Voltage Mode Sense Amplifier (VSA)Sense amplifier which detects the voltage difference onthe bit lines is called voltage mode sense amplifier. Thereare some voltage mode sense amplifiers like single endedsense amplifiers, differential amplifiers and Crosscoupled sense amplifiers. Different types of senseamplifier are used in different types of memory cellsaccording to the proper design and efficient performance.Figure 2 Six-transistor CMOS SRAM cell [5].The SRAM cell should be sized as small as possible toachieve high memory densities. A 6T SRAM is shown inFig.2. It is made of six transistors so it is called 6TSRAM. In this 6T SRAM two inverters (M1, M2 and M3,M4) are cross coupled. Each bit of data is stored on thesefour transistors in an SRAM cell. This storage cell hastwo stable states which are as ‘0’and ‘1’. Two additionalaccess transistors M5 and M6 are used to control theaccess to a storage cell during read and write operationsand these are connected to the bit lines and word line. Forthe accurate operation the size of the transistors aredesigned properly.2.1.2 CMOS SRAM Read OperationAssume that a ‘1’ is stored at Q, so the ‘0’ will be at QB.Both the bit lines are pre-charged to VDD. Read cyclewill not start until the word line is low. As the word linewill be high, both the access transistors M5 and M6 willbe turned on and the read cycle initiate. During a correctread operation, the values stored in Q and QB aretransferred to the bit lines by leaving BL at its pre-chargevalue and by discharging BLB through M1-M5. As the‘1’ is stored at Q, due to which the transistor M1 will beturned ON and the transistor M3 will be turned OFF asthe ‘0’ is stored at QB. Transistor M5 is already on due tohigh word line, a direct path will be forms between BLBand ground as both the transistors M1and M5 are ON.Now the BLB will be discharged through transistors M1and M5. BL remains high in this case and BLB isdischarged and it takes long time to reach ground leveldue to high bit line capacitance. Therefore, senseamplifier is needed to amplify the differential voltage ofbit lines to full swing voltage levels at the faster rates.Figure .3 Cross-coupled voltage mode SA [10].Fig.3 shows the schematic of Cross-coupled voltage modeSA. M1 and M2 are the access transistors, whereas M3M6 forms cross-coupled inverters. When SAEN is low,M1 and M2 are turned ON and voltage on BL and BLBwill be transferred to SL and SLB respectively. Due topositive feedback, higher voltage level goes to VDD andother level goes towards zero.In the basic cross-coupled SA, the nodes SL and SLB areinput and output terminals at the same time. Therefore,the circuit cannot be connected directly to the bit linesince the circuit would attempt to discharge the bit linecapacitance during the decision phase and would increasedelay and power. A solution is either to separate the bitline by a multiplexer or to use pass gates, forming adecoupling resistor. Both devices cause a voltage dropthat deteriorates the available input voltage difference.This way the voltage swing at the bit lines can easilyreduce by half, resulting in lower speed and noise margin.2.1.3 CMOS SRAM Write OperationFor the proper SRAM write operation, assume that a ‘1’is stored in the cell Q, then the value stored at QB will be‘0’. Due to the values stored at Q and QB, transistors M2and M3 will be turned off. As the word line becomeshigh, the write cycle will start. Now, for the value ‘0’ is tobe stored at Q, bit line BL is kept at ‘0’.By keeping theproper sizes of the transistors, the transistor M6 willdischarge the node Q very fast as compare to the chargingFigure 4 Current latched voltage mode SA [1].Volume 3, Issue 2 March – April 2014Page 44
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.comVolume 3, Issue 2, March – April 2014ISSN 2278-6856This drawback does not occur for the latch circuit shownin Fig.4 because of a high-impedance input differentialstage. It was introduced by Kobayashi et al. in 1993 [1].This sense amplifier combines strong positive feedbackwith a high resistive input. The current flow of thedifferential input transistors M1 and M2 controls theserially connected latch circuit. A small differencebetween the currents through M1 and M2 converts to alarge output voltage. This current latched SA is fasterthan conventional cross coupled SA.During reset phase when SAEN 0V, the output nodes ofthe SA (O1 and O2) are reset to VDD through the resettransistors M6 and M9. During evaluation phase whenSAEN VDD, M3 turns ON and the input transistors M1and M2 starts to discharge O1and O2 node voltages toGND. When any of these node voltages falls from VDDto VDD-Vthn, NMOS transistors of the cross coupledinverters turn ON initiating positive feedback. Furtherwhen any of output node voltage drops to VDD-Vthp,PMOS transistors of the inverters turns ON and furtherenhances the positive feedback and converts a small inputvoltage difference to large full scale output. Inverters areused further to speed up the sensing process.Current mode sense amplifier is used to detect the currentdifference between the bit lines to determine whether a‘1’ or ‘0’ is stored in the memory cell. It directlymeasures the cell read current and transfers to the outputcircuits. This approach can overcome the restriction ofgain reduction brought on by voltage mode senseamplifier at low power supply voltage. The simpleststructure of the current mode sense amplifier is describedin Fig.5. The conventional current sense amplifierbasically consists of four equal sized PMOS transistors asshown in Fig.5. It features a current sensing charactersince it represents a virtual short circuit to the bit lines,which transfer the cell current directly to the outputcircuits [2]. If memory cell stores ‘0’ then when it isaccessed, it draws some current. The difference in thecurrent flowing through both branches will be equal tocell current. The current in DLB is higher than current inDL as shown in Fig.5.This differential current isconverted into full swing differential voltage in nextstage.2.2.2 Current Mode Sense Amplifier (CSA)In advanced memories the capacitances of the bit line isincreasing due to technology scaling and the increasingnumber of cells attached to the column. In such memoriesvoltage mode cannot keep up to their performance therebyleading to the need for faster sensing techniques that arenot affected by the bit line capacitance. Current modesense amplifiers are applied to reduce the sense circuitdelays as they provide low common input/outputimpedances. The small input impendence presented to thebit-lines result in reduced voltage swings, cross-talk andsubstrate currents.Figure 6 Modified current mode sense amplifier[4].Figure 5 Conventional current mode sense amplifier[10].Volume 3, Issue 2 March – April 2014The modified current sense amplifier consists of twoparts: a current transporting circuit with unity gaincurrent transfer characteristics and a sensing circuitwhich senses the differential current and converts it intofull swing differential voltage as shown in Fig.6. It is amodification of [3] presented in [4].The circuit [3] hasbeen modified by shifting the sense amplifier enablesignal closer to the output. All the nodes of the circuit hasbeen pre-charged to full VDD or pre-discharged toground.The current sense amplifier operates in two phases: precharge and evaluate. During the pre-charge phase, thePage 45
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.comVolume 3, Issue 2, March – April 2014ISSN 2278-6856bit-lines are pre-charged through pre-charge devicesconnected to the bit-lines (not shown here). The senseamplifier output nodes SA and SA# are also pre-chargedhigh through M11 and M12 PMOS devices. Theoperating current of the sense amplifier is determined bythe sizes of devices M5-M8. At the end of the pre-chargephase, pre-charge and equalization devices M11-M13 areturned OFF. During the evaluation phase, Ysel is pulledlow and current is immediately transported to the nodes Aand B through the drains of M3 and M4.The difference incurrent flowing through A and B will be equal to the cellcurrent. The sense amplifier is enabled two-inverter delayafter the SAen is pulled high during which bias currentflows through two legs of the sense amplifier, while M14keeps the output equalized. After this two inverter delay,M14 is disabled and the differential current causes adifferential voltage to be developed at SA and SA#. Thisdifferential voltage us then amplified to CMOS logiclevels by the high-gain positive feedback cross-coupledinverters formed by M5-M8.The sensing delay isrelatively insensitive to bit-line capacitance as theoperation is not dependent on the development of adifferential voltage across the bit-lines. Unlike the voltagesense amplifier, the output nodes are not tied to the highcapacitance bit-lines and are able to respond very quickly.The CSA can have lower voltage swing on bit-lines. Thisis because the cross coupled PMOS pair M1 and M2 cutsoff the discharge path to ground for both bit-lines.Suppose BL is high and BL# is going low. This causesnodes Int and A to go high causing M2 to be cut off.Therefore, the path from the low going BL# to ground iscut off, reducing the voltage swing on it. This schemeenhances the speed of the sense amplifier further due tothe fact that there is a flow of bias current before thesense amplifier is actually enabled. This results in smallincrease in the static power consumption [4].2.2.3 C
Volume 3, Issue 2, March – April 2014 ISSN 2278-6856 Volume 3, Issue 2 March – April 2014 Page 44 2.1.1 6T SRAM cell Figure 2 Six-transistor CMOS SRAM cell [5]. The SRAM cell should be sized as small as possible to achieve high memory densities. A 6T SRAM is shown in Fig.2
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