LTC2500-32 - 32-Bit Oversampling ADC With Configurable .
LTC2500-3232-Bit Oversampling ADCwith Configurable Digital FilterFEATURESDESCRIPTION 0.5ppm INL (Typ)nn 104dB SNR (Typ) at 1Mspsnn 148dB Dynamic Range (Typ) at 61spsnn Guaranteed 32-Bit No Missing Codesnn Configurable Digital Filter with Synchronizationnn Relaxed Anti-Aliasing Filter Requirementsnn Dual Output 32-Bit SAR ADCnn 32-Bit Digitally Filtered Low Noise Outputnn 24-Bit Differential 7-Bit Common Mode 1MspsOutput with Overrange Detectionnn Wide Input Common Mode Rangenn Guaranteed Operation to 85 Cnn 1.8V to 5V SPI-Compatible Serial I/Onn Low Power: 24mW at 1Mspsnn 24-Lead 7mm 4mm DFN PackagesThe LTC 2500-32 is a low noise, low power, high performance 32-bit ADC with an integrated configurable digitalfilter. Operating from a single 2.5V supply, the LTC2500-32features a fully differential input range up to VREF, withVREF ranging from 2.5V to 5.1V. The LTC2500-32 supportsa wide common mode range from 0V to VREF simplifyinganalog signal conditioning requirements.nnThe LTC2500-32 simultaneously provides two outputcodes: (1) a 32-bit digitally filtered high precision lownoise code, and (2) a 32-bit no latency composite code.The configurable digital filter reduces measurement noiseby lowpass filtering and downsampling the stream of datafrom the SAR ADC core, giving the 32-bit filtered outputcode. The 32-bit composite code consists of an overrangedetection bit, a 24-bit code representing the differentialinput voltage and a 7-bit code representing the commonmode input voltage. The 32-bit composite code is availableeach conversion cycle, with no cycle of latency.APPLICATIONSSeismologyEnergy Explorationnn Automatic Test Equipmentnn High Accuracy InstrumentationnnThe digital filter is highly configurable through the SPIcompatible interface and features many distinct filter typesthat suit a variety of applications. The digital lowpass filterrelaxes the requirements for analog anti-aliasing. MultipleLTC2500-32 devices can be easily synchronized usingthe SYNC pin.nnAll registered trademarks and trademarks are the property of their respective owners. Protectedby U.S. patents, including 7705765, 7961132, 8319673, 8576104, 8810443, 9231611,9054727, 9331709 and patents pending.TYPICAL APPLICATIONIntegral Nonlinearity vsOutput Code1.8V TO 5.1V2.5V2.00.1µFIN , IN–VREFARBITRARY0VVREFDIFFERENTIALVREFVDDIN 32-BITSAR LOW PASSWIDEBAND DIGITALFILTER0VDIFFERENTIAL INPUTS IN /IN– WITHWIDE INPUT COMMON MODE RANGEREF2.5V TO 5.1V32-BIT24-BITIN LARDLBSDOBSCKB250032 TA0147µF(X7R, 1210 SIZE)1.0INL ERROR .5INPUT VOLTAGE (V)5250032 TA01b250032fbFor more information www.linear.com/LTC2500-321
LTC2500-32TABLE OF CONTENTSFeatures. 1Applications. 1Typical Application . 1Description. 1Absolute Maximum Ratings. 3Order Information. 3Pin Configuration. 3Electrical Characteristics. 4Converter Characteristics for Filtered Output (SDOA). 4Dynamic Accuracy for Filtered Output (SDOA). 4Converter Characteristics for No latency Output (SDOB). 4Dynamic Accuracy for No Latency Output (SDOB). 5Reference Input. 5Digital Inputs and Digital Outputs. 6Power Requirements. 6ADC Timing Characteristics. 6Typical Performance Characteristics. 8Pin Functions.11Functional Block Diagram.12Timing Diagram.12Applications Information.13Overview. 13Converter Operation. 13Transfer Function. 13Analog Input. 13Input Drive Circuits. 14ADC Reference. 21Dynamic Performance. 22Power Considerations. 22Timing and Control. 23Decimation Filters. 23Digital Filter Types. 26Digital Interface. 33Preset Filter Modes. 36Filtered Output Data. 36No Latency Output Data. 45Board Layout.51Package Description.52Revision History.53Typical Application.54Related Parts.542250032fbFor more information www.linear.com/LTC2500-32
LTC2500-32ABSOLUTE MAXIMUM RATINGSPIN CONFIGURATION(Notes 1, 2)Supply Voltage (VDD).2.8VSupply Voltage (OVDD).6VReference Input (REF).6VAnalog Input Voltage (Note 3)IN , IN–.(GND – 0.3V) to (REF 0.3V)Digital Input Voltage(Note 3). (GND – 0.3V) to (OVDD 0.3V)Digital Output Voltage(Note 3). (GND – 0.3V) to (OVDD 0.3V)Power Dissipation. 500mWOperating Temperature RangeLTC2500C-32. 0 C to 70 CLTC2500I-32.–40 C to 85 CStorage Temperature Range. –65 C to 150 CORDER INFORMATIONTOP VIEWRDLA 1RDLB 2VDD 3GND 4IN 5IN– 6GND 7REF 8REF 9PRE 10GND 11GND 1225GND24 GND23 GND22 OVDD21 BUSY20 SDOB19 SCKB18 SCKA17 SDOA16 SDI15 DRL14 SYNC13 MCLKDKD PACKAGE24-LEAD (7mm 4mm) PLASTIC DFNTJMAX 125 C, θJA 40 C/WEXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO nfoLEAD FREE FINISHTAPE AND REELPART MARKING*PACKAGE DESCRIPTIONTEMPERATURE 4-Lead (7mm 4mm) Plastic DFN0 C to 70 ad (7mm 4mm) Plastic DFN–40 C to 85 CConsult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.For more information on lead free part marking, go to: http://www.linear.com/leadfree/For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels throughdesignated sales channels with #TRMPBF suffix.250032fbFor more information www.linear.com/LTC2500-323
LTC2500-32ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA 25 C. (Note 4)SYMBOLPARAMETERCONDITIONSVIN Absolute Input Range (IN )VIN–Absolute Input Range (IN–)VIN – VIN–Input Differential Voltage RangeVIN VIN – VIN–VCMCommon Mode Input RangeIINAnalog Input Leakage CurrentCINAnalog Input CapacitanceCMRRInput Common Mode Rejection RatioMINMAXUNITS0VREFV0VREFVl VREFVREFVl0VREFV(Note 5)l(Note 5)lTYP10nASample ModeHold Mode455pFpFNo Latency OutputVIN VIN– 4.5VP-P, 2kHz Sine128dBCONVERTER CHARACTERISTICS FOR FILTERED OUTPUT (SDOA)The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA 25 C.(Note BitsNo Missing Codesl32BitsTransition Noise(Note 6) See Table 2DFDown-Sampling FactorINLIntegral Linearity Error(Notes 7, 8)l–2ZSEZero-Scale Error(Notes 7, 9)l13Zero-Scale Error Drift(Note 7)FSETYPl4Full-Scale Error(Notes 7, 9)Full-Scale Error Drift(Note 7)16384 0.52013 7l–100 10ppmppmppb/ C100 0.05ppmppm/ CDYNAMIC ACCURACY FOR FILTERED OUTPUT (SDOA)The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA 25 C andssinc filter. (Notes 4, 9)SYMBOLPARAMETERCONDITIONSDRDynamic RangeDF 4IN IN– VCM, VREF 5V, DF 64IN IN– VCM, VREF 5V, DF VERTER CHARACTERISTICS FOR NO LATENCY OUTPUT (SDOB)The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA 25 C.(Notes ifferentialCommon Modell247BitsBitsNo Missing Codes:DifferentialCommon Modell247BitsBitsTransition Noise:DifferentialCommon Mode4MIN2.31ppmRMSLSBRMS250032fbFor more information www.linear.com/LTC2500-32
LTC2500-32CONVERTER CHARACTERISTICS FOR NO LATENCY OUTPUT (SDOB)The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA 25 C.(Notes 4)SYMBOLPARAMETERCONDITIONSINLIntegral Linearity Error:DifferentialCommon Mode7-Bit OutputZero-Scale Error:DifferentialCommon Mode7-Bit OutputZSEMINTYPMAXl–2 0.5 0.12ppmLSBl–130 113ppmLSBZero-Scale Error Drift:DifferentialFSEFull-Scale Error:DifferentialCommon Mode 7l7-Bit Output–100Full-Scale Error Drift:Differential 10 1UNITSppb/ C100 0.05ppmLSBppm/ CDYNAMIC ACCURACY FOR NO LATENCY OUTPUT (SDOB)The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA 25 C andAIN –1dBFS. The specifications are for the differential output (Notes 4, Noise Distortion) RatiofIN 2kHz, VREF 5Vl100104fIN 2kHz, VREF 5VlSNRSignal-to-Noise RatioTHDTotal Harmonic Distortion100fIN 2kHz, VREF 5VfIN 2kHz, VREF 2.5VlSFDRSpurious Free Dynamic RangefIN 2kHz, VREF �3dB Input Linear Bandwidth34MHzAperture Delay500psAperture Jitter4Transient Response115MAXFull-Scale SteppsRMS125nsREFERENCE INPUTThe l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA 25 C. (Notes 4)SYMBOLPARAMETERCONDITIONSMINVREFReference Voltage(Note 5)lIREFReference Input Current(Note 11)lTYPMAX5.1V0.91.4mA2.5UNITS250032fbFor more information www.linear.com/LTC2500-325
LTC2500-32DIGITAL INPUTS AND DIGITAL OUTPUTSThe l denotes the specifications which apply over thefull operating temperature range, otherwise specifications are at TA 25 C. (Note 4)SYMBOLPARAMETERVIHHigh Level Input VoltageCONDITIONSlVILLow Level Input VoltagelVIN 0V to OVDDMINTYPMAXUNITS0.8 0VDDVV10µAIINDigital Input CurrentCINDigital Input CapacitanceVOHHigh Level Output VoltageIO –500 µAlVOLLow Level Output VoltageIO 500 µAlIOZHi-Z Output Leakage CurrentVOUT 0V to OVDDlISOURCEOutput Source CurrentVOUT 0V–10mAISINKOutput Sink CurrentVOUT OVDD10mAl–100.2 OVDD5pFOVDD – 0.2V–100.2V10µAPOWER REQUIREMENTSThe l denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA 25 C. (Note 5.25VVDDSupply Voltagel2.375OVDDSupply Voltagel1.71IVDDIOVDDIPDSupply CurrentSupply CurrentPower Down Mode1Msps Sample Rate1Msps Sample Rate (CL 20pF)Conversion Done (IVDD IOVDD IREF)PDPower DissipationPower Down Mode1Msps Sample Rate (IVDD)Conversion Done (IVDD IOVDD IREF)ll9.51614350mAmAµA241535875mWµWADC TIMING CHARACTERISTICSThe l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA 25 C. (Note 4)SYMBOLPARAMETERfSMPLMaximum Sampling FrequencyfDRAfDRBCONDITIONSMINMAXUNITSl1MspsOutput Data Rate at SDOAl250kspsOutput Data Rate at SDOBl1MspstCONVConversion TimetACQAcquisition TimetCYCTime Between ConversionstMCLKHConversion High TimetMCLKLMinimum Low Time for MCLK(Note 13)tBUSYLHMCLK to BUSY DelayCL 20pFltACQ tCYC – tCONV – tBUSYLH (Note KA, SCKB Quiet Time from MCLK (Note 12)l10nstSCKASCKA Period(Notes 13, 14)l10nstSCKAHSCKA High Timel4nstSCKALSCKA Low Timel4nstSSDISCKAtHSDISCKASD1 Setup Time from SCKA SD1 Hold Time from SCKA (Note 13)(Note 13)ll41nsnstDSDOASDOA Data Valid Delay from SCKA CL 20pF, OVDD 5.25VCL 20pF, OVDD 2.5VCL 20pF, OVDD 1.71Vlll68.58.59.5nsnsns250032fbFor more information www.linear.com/LTC2500-32
LTC2500-32ADC TIMING CHARACTERISTICSThe l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA 25 C. (Note 4)SYMBOLPARAMETERCONDITIONSMINTYPMAXtHSDOASDOA Data Remains Valid Delay fromSCKA CL 20pF (Note 12)ltDSDOADRLLSDOA Data Valid Delay from DRL CL 20pF (Note 12)l5nstENABus Enable Time After RDLA (Note 13)l16nstDISABus Relinquish Time After RDLA (Note 13)l13ns(Notes 13, 14)l10nsl4nsl4ns1UNITSnstSCKBSCKB PeriodtSCKBHSCKB High TimetSCKBLSCKB Low TimetDSDOBSDOB Data Valid Delay from SCKB CL 20pF, OVDD 5.25VCL 20pF, OVDD 2.5VCL 20pF, OVDD 1.71VllltHSDOBSDOB Data Remains Valid Delay fromSCKB CL 20pF (Note 12)ltDSDOBBUSYLSDOB Data Valid Delay from BUSY CL 20pF (Note 12)l5nstENBBus Enable Time After RDLB (Note 13)l16nstDISBBus Relinquish Time After RDLB (Note 13)l13ns8.58.59.51nsnsnsnsNote 8: Integral nonlinearity is defined as the deviation of a code from astraight line passing through the actual endpoints of the transfer curve.The deviation is measured from the center of the quantization band.Note 9: Bipolar zero-scale error is the offset voltage measured from–0.5LSB when the output code flickers between 0000 0000 0000 00000000 0000 0000 0000 and 1111 1111 1111 1111 1111 1111 11111111. Full-scale bipolar error is the worst-case of –FS or FS untrimmeddeviation from ideal first and last code transitions and includes the effectof offset error.Note 10: All specifications in dB are referred to a full-scale 5V input witha 5V reference voltage.Note 11: fSMPL 1MHz, IREF varies proportionally with sample rate.Note 12: Guaranteed by design, not subject to test.Note 13: Parameter tested and guaranteed at OVDD 1.71V, OVDD 2.5Vand OVDD 5.25V.Note 14: tSCKA, tSCKB of 10ns maximum allows a shift clock frequency upto 100MHz for rising edge capture.Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition for extended periods may affect devicereliability and lifetime.Note 2: All voltage values are with respect to ground.Note 3: When these pin voltages are taken below ground or above REF orOVDD, they will be clamped by internal diodes. This product can handleinput currents up to 100mA below ground or above REF or OVDD withoutlatchup.Note 4: VDD 2.5V, OVDD 2.5V, REF 5V, VCM 2.5V, fSMPL 1MHz.Note 5: Recommended operating conditions.Note 6: Transition noise is defined as the noise level of the ADC with IN and IN– shorted.Note 7: The DC specifications at SDOA are measured and guaranteed atSDOB. The operation of the digital filters is tested separately to guaranteethe same DC specifications at SDOA.tWIDTH0.8 OVDD0.2 OVDDtDELAYtDELAY0.8 OVDD0.8 OVDD0.2 OVDD0.2 OVDD50%50%250032 F01Figure 1. Voltage Levels for Timing Specifications250032fbFor more information www.linear.com/LTC2500-327
LTC2500-32TYPICAL PERFORMANCE CHARACTERISTICSREF 5V, fSMPL 1Msps, no latency output, unless otherwise noted.Integral Nonlinearity vs InputVoltageDifferential Nonlinearity vs InputVoltage2.01.01.50.880000–0.50.2COUNTSDNL (LSB)INL ERROR 5INPUT VOLTAGE (V)–1.05–5250032 G01DC Histogram Filtered Output,DF 4, SSINC Filter1000–2.502.5INPUT VOLTAGE (V)0–1551000σ 0.7ppmDC Histogram Filtered Output,DF 1024, SSINC Filter1000σ 0.17ppm800600600600COUNTS800200400200–4–3–2 –1012OUTPUT CODE (ppm)304–1–0.500.5OUTPUT CODE (ppm)0σ 0.018ppm2000.4250032 ��140–140–160–1600125250375FREQUENCY (kHz)SNR 116dBTHD –120dBSINAD 114dBSFDR 121dB–20–60–1800.4128k Point FFT Filtered Output,fIN 2kHz, DF 4, SSINC FilterAMPLITUDE (dBFS)AMPLITUDE (dBFS)400–0.200.2OUTPUT CODE (ppm)250032 G06SNR 104dBTHD –120dBSINAD 104dBSFDR 121dB–20–40–0.200.2OUTPUT CODE (ppm)0–0.4116k Point FFT fIN 2kHz8000–0.4400250032 G05DC Histogram Filtered Output,DF 16384, SSINC Filter600σ 0.049ppm200250032 G04100015250032 G03800400–7.507.5OUTPUT CODE (ppm)250032 G02DC Histogram Filtered Output,DF 64, SSINC FilterCOUNTSCOUNTS6000–0.4–1.50σ 2.4ppm0.4–1.0COUNTSDC Histogram100000.61.0–2.0TA 25 C, VDD 2.5V, OVDD 2.5V, VCM 2.5V,500250032 G08–1800316294FREQUENCY (kHz)125250032 G09250032fbFor more information www.linear.com/LTC2500-32
LTC2500-32TYPICAL PERFORMANCE CHARACTERISTICSREF 5V, fSMPL 1Msps, no latency output, unless otherwise noted.0128k Point FFT Filtered Output,fIN 200Hz, DF 64, SSINC Filter128k Point FFT Filtered Output,fIN 100Hz, DF 1024, SSINC Filter8k Point FFT Filtered Output,fIN 11Hz, DF 16384, SSINC Filter0DR DE 180–200–20046FREQUENCY (kHz)80122250032 G10SNR, SINAD (dBFS)DYNAMIC RANGE C4SSINCFLAT PASSBAND4101001000DOWNSAMPLING FACTORSNR102101100SINAD99989796951638402550SNR, SINAD (dBFS)SNR, SINAD (dBFS)–110–115–120–125–130255075 100 125 150 175 200FREQUENCY (kHz)THD, Harmonics vs ReferenceVoltage, fIN 2kHz102–120SINAD1011009998971010250032 –40–30–20–10INPUT LEVEL (dB)0250032 G16250032 G12–115104SNR31–105–14075 100 125 150 175 200FREQUENCY (kHz)105103–100SNR, SINAD vs ReferenceVoltage, fIN 2kHz1051523FREQUENCY (Hz)THD2ND3RD250032 G14SNR, SINAD vs Input Level,fIN 2kHzSINAD8–135250032 G131040THD, Harmonics vs InputFrequencySNR, SINAD vs Input Frequency150110–200488250032 G11Filtered Output Dynamic Rangevs DF120244366FREQUENCY (Hz)HARMONICS, THD (dBFS)2HARMONICS, THD (dBFS)0DR 149dB–20–40AMPLITUDE (dBFS)AMPLITUDE (dBFS)0DR 128dB–20TA 25 C, VDD 2.5V, OVDD 2.5V, VCM 2.5V,952.533.544.5REFERENCE VOLTAGE (V)5250032 G17–1452.533.544.5REFERENCE VOLTAGE (V)5250032 G18250032fbFor more information www.linear.com/LTC2500-329
LTC2500-32TYPICAL PERFORMANCE CHARACTERISTICSREF 5V, fSMPL 1Msps, no latency output, unless otherwise noted.–110THD, HARMONICS ND100–40–151035TEMPERATURE ( C)6085–140–40Full-Scale Error vs Temperature–151035TEMPERATURE ( C)60–FS1035TEMPERATURE (oC)6010493210–1–2–3–151035TEMPERATURE ( C)60250032 G2220100–40–151035TEMPERATURE ( C)106085250032 03.544.5REFERENCE VOLTAGE (V)60855250032 G26VIN V IN– 4.5V P-P SINE1100.631035TEMPERATURE ( C)CMRR vs Input Frequency1.00.42.5I OVDD250032 G24CMRR (dB)REFERENCE CURRENT (mA)POWER–DOWN CURRENT (µA)307Reference Current vs ReferenceVoltage40858250032 G23Shutdown Current vs Temperature60IVDD1–5–40851035TEMPERATURE ( C)Supply Current vs Temperature5–4–15–15250032 G21POWER SUPPLY CURRENT (mA)ZERO-SCALE ERROR (ppm)0MIN INL–4–4085Offset Error vs Temperature FS–10–40–1250032 G20105MAX INL0–3250032 G19–51–2–135101FULL–SCALE ERROR (ppm)INL vs Temperature4–115105SNR, SINAD (dBFS)THD, Harmonics vs Temperature,fIN 100HzINL ERROR (ppm)106SNR, SINAD vs Temperature,fIN 2kHzTA 25 C, VDD 2.5V, 0VDD 2.5V, VCM 2.5V,800.010.1110FREQUENCY (kHz)100500250032 G27250032fbFor more information www.linear.com/LTC2500-32
LTC2500-32PIN FUNCTIONSRDLA (Pin 1): Read Low Input A (Filtered Output). WhenRDLA is low, the serial data output A (SDOA) pin is enabled.When RDLA is high, SDOA pin is in a high impedancestate. Logic levels are determined by OVDD.DRL (Pin 15): Data Ready Low Output. A falling edgeon this pin indicates that a new filtered output code isavailable in the output register of SDOA. Logic levels aredetermined by OVDD.RDLB (Pin 2): Read Low Input B (No Latency Output).When RDLB is low, the serial data output B (SDOB) pinis enabled. When RDLB is high, SDOB pin is in a highimpedance state. Logic levels are determined by OVDD.SDI (Pin 16): Serial Data Input. Data provided on this line,in synchrony with SCKA, can be used to program the digitalfilter and DGC/DGE modes. Input data on SDI is latched onrising edges of SCKA. Logic levels are determined by OVDD.VDD (Pin 3): 2.5V Power Supply. The range of VDD is2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic capacitor.SDOA (Pin 17): Serial Data Output A (Filtered Output).The filtered output code appears on this pin (MSB first)on each rising edge of SCKA. The output data is in 2’scomplement format. Logic levels are determined by OVDD.GND (Pins 4, 7, 11, 12, 23, 24): Ground.IN (Pin 5): Positive Analog Input.IN– (Pin 6): Negative Analog Input.REF (Pins 8, 9): Reference Input. The range of REF is 2.5Vto 5.1V. This pin is referred to the GND pin and should bedecoupled closely to the pin with a 47µF ceramic capacitor(X7R, 1210 size, 10V rating).PRE (Pin 10): Preset Input. By setting PRE high, the SDIpin is used to select between two preset digital filter modes.Setting PRE low allows the digital filter to be configuredby entering a configuration word at SDI. Logic levels aredetermined by REF, with range of REF being 2.5V to 5.1V.MCLK (Pin 13): Master Clock Input. A rising edge on thisinput powers up the part and initiates a new conversion.Logic levels are determined by OVDD.SYNC (Pin 14): Synchronization Input. A pulse on thisinput is used to synchronize the phase of the digital filter.When applied across multiple devices, a SYNC pulse synchronizes all the devices to the same phase. Logic levelsare determined by OVDD.SCKA (Pin 18): Serial Data Clock Input A (Filtered Output).When SDOA is enabled, the filtered output code is shiftedout (MSB first) on the rising edges of this clock. Logiclevels are determined by OVDD.SCKB (Pin 19): Serial Data Clock Input B (No LatencyOutput). When SDOB is enabled, the no latency outputcode is shifted out (MSB first) on the rising edges of thisclock. Logic levels are determined by OVDD.SDOB (Pin 20): Serial Data Output B (No Latency Output).The 32-bit no latency composite output code appears onthis pin (MSB first) on each rising edge of SCKB. Theoutput data is in 2’s complement format. Logic levels aredetermined by OVDD.BUSY (Pin 21): BUSY Indicator. Goes high at the start ofa new conversion and returns low when the conversionhas finished. Logic levels are determined by OVDD.OVDD (Pin 22): I/O Interface Digital Power. The range ofOVDD is 1.71V to 5.25V. This supply is nominally set tothe same supply as the host interface (1.8V, 2.5V, 3.3V, or5V). Bypass OVDD to GND (Pin 23) with a 0.1µF capacitor.GND (Exposed Pad Pin 25): Ground. Exposed pad mustbe soldered directly to the ground plane.250032fbFor more information www.linear.com/LTC2500-3211
LTC2500-32FUNCTIONAL BLOCK DIAGRAMVDD 2.5VREF 2.5V TO 5.1VOVDD 1.8V TO 5VLTC2500-32SDIIN SDOA 32-BITSAR 4RDLBMCLKBUSYDRLCONTROL LOGICSYNCPREGND250032 FBDTIMING DIAGRAMRDLA RDLB WER DOWN AND 4DB12DB10DB8DB6DB4DB2DB0CB5CB3CB1250032 TD250032fbFor more information www.linear.com/LTC2500-32
LTC2500-32APPLICATIONS INFORMATIONThe LTC2500-32 is a low noise, low power, high performance 32-bit ADC with an integrated configurable digitalfilter. Operating from a single 2.5V supply, the LTC2500-32features a fully differential input range up to VREF, withVREF ranging from 2.5V to 5.1V. The LTC2500-32 supportsa wide common mode range from 0V to VREF simplifyinganalog signal conditioning requirements.The LTC2500-32 simultaneously provides two outputcodes: (1) a 32-bit digitally filtered high precision lownoise code, and (2) a 32-bit no latency composite code.The configurable digital filter reduces measurement noiseby lowpass filtering and down-sampling the stream of datafrom the SAR ADC core, giving the 32-bit filtered outputcode. The 32-bit composite code consists of an overrangedetection bit, a 24-bit code representing the differentialinput voltage and a 7-bit code representing the commonmode input voltage. The 32-bit composite code is availableeach conversion cycle, with no cycle of latency.The digital filter is highly configurable through the SPIcompatible interface and features many distinct filter typesthat suit a variety of applications. The digital lowpass filterrelaxes the requirements for analog anti-aliasing. MultipleLTC2500-32 devices can be easily synchronized usingthe SYNC pin.a 24-bit code representing the differential voltage and a7-bit code representing the common mode voltage arecombined to form a 32-bit composite code. The 32-bitcomposite code is available each conversion cycle, withoutany cycle of latency.TRANSFER FUNCTIONThe LTC2500-32 digitizes the full-scale differential voltageof 2 VREF into 232 levels, resulting in an LSB size of 2.3nVwith a 5V reference. The ideal transfer function is shownin Figure 2. The output data is in 2’s complement format.OUTPUT CODE (TWO’S 1000.000111.111111.110100.001FSR FS – –FS1LSB FSR/4294967296100.000–FSR/2–1 0V 1FSR/2 – 1LSBLSBLSBINPUT VOLTAGE (V)250032 F02Figure 2. LTC2500-32 Transfer FunctionANALOG INPUTCONVERTER OPERATIONThe LTC2500-32 operates in two phases. During the acquisition phase, a 32-bit charge redistribution capacitorD/A converter (CDAC) is connected to the IN and IN– pinsto sample the analog input voltages. A rising edge on theMCLK pin initiates a conversion. During the conversionphase, the 32-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing thesampled inputs with binary-weighted fractions of the reference voltage (e.g. VREF/2, VREF/4 VREF/4294967296).At the end
lead free finish tape and reel part marking* package description temperature range ltc2500cdkd-32#pbf ltc2500cdkd-32#trpbf 250032 24-lead (7mm 4mm) plastic dfn 0 c to 70 c ltc2500idkd-32#pbf ltc2500idkd-32#trpbf 250032 24-lead (7mm 4mm) plastic dfn –40 c to 85 c
nuclear facilities. This work proposes a novel form of synthetic oversampling based on artificial neural network architecture and empirically demonstrates that it is superior to the state-of-the-art in synthetic oversampling on the target domain. In particular, we utilize gamma-ray spectral data collected for security purposes
Windows XP Professional 32-Bit/64-Bit, Windows Vista Business 32-Bit/64-Bit, Red Hat Enterprise Linux WS v4.0 32-bit/64-bit, Red Hat Enterprise Desktop v5.0 32-bit/64-bit (with Workstation Option), SUSE Linux Enterprise (SLE) desktop and server v10.1 32-bit/64-bit Resources Configuration LUTs
A. Modulator Order, Quantizer Levels, and Oversampling Ratio Trade-offs The oversampling ratio (OSR) can be at most FS (2 FBW) 16. After examining the empirical SQNR limit versus OSR and modulator order [1], I saw that a single bit quantizer cannot meet the design specification, which leads me to consider a multi-bit quantizer. I chose to .
8127FS–AVR–02/2013 4. Register Summary Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F SREG I T H S V N Z C Page 12 0x3E SPH Stack Poin
The design of a fifth-order sigma-delta modu lator (as in the AD1879 duall8 bit ADC) is certainly not a trivial matter, and neither is the digital filter. The sigma-delta converter is inherently an oversampling converter, although oversampling is just one of the techniques contributing to the overall per formance.
Microsoft Windows 7, 32-bit and 64-bit Microsoft Windows 8 & 8.1, 32-bit and 64-bit Microsoft Windows 10, 32-bit and 64-bit Microsoft Windows Server 2008 R2 Microsoft Windows Server 2012, 64-bit only RAM: Minimum 2 GB for the 32-bit versions of Microsoft Windows 7, Windows 8, Windows 8.1, and Windows 10.
Implementation o Load bit o Read logic o Write logic Multi-bit register Bit out load in if load(t-1) then out(t) in(t-1) else out(t) out(t-1) 1-bit register o Register’s width: a trivial parameter o Read logic o Write logic Bit. . . w-bit register out load in w w Bit Bit Aside: Hardware Simulation Relevant topics from the HW simulator tutorial:
Archaeological Illustration ARCL0036 UCL - INSTITUTE OF ARCHAEOLOGY COURSE NUMBER: ARCL0036 Archaeological Finds Illustration 2018/2019 Year 2, 0.5 unit 15 Credits Co-ordinator: Stuart Laidlaw Co-ordinator's e-mail tcfasjl@ucl.ac.uk Co-ordinator's room number is 405 Telephone number 020 7679 4743 Internal 24743 The Turnitin 'Class ID' is 3884493 and the 'Class Enrolment Password' is IoA1819 .
