Verilog - Operators

Verilog - OperatorsIVerilog operators operate on several data types to produce an outputINot all Verilog operators are synthesible (can produce gates)ISome operators are similar to those in the C languageIRemember, you are making gates, not an algorithm (in most cases)

Verilog - OperatorsArithmetic OperatorsIIThere are two types of operators: binary and unaryBinary operators:Iadd( ), subtract(-), multiply(*), divide(/), power(**), modulus(%)//suppose that: a 4’b0011;//b 4’b0100;//d 6; e 4; f 2;//then,a b //add a and b; evaluates to 4’b0111b - a //subtract a from b; evaluates to 4’b0001a * b //multiply a and b; evaluates to 4’b1100d / e //divide d by e, evaluates to 4’b0001. Truncates fractional parte ** f //raises e to the power f, evaluates to 4’b1111//power operator is most likely not synthesibleIf any operand bit has a value ”x”, the result of the expression is all ”x”.If an operand is not fully known the result cannot be either.

Verilog - OperatorsArithmetic Operators (cont.)Modulus operator yields the remainder from division of two numbersIt works like the modulus operator in CModulus is synthesible316-77% 2;% 4;% 2;% ototo10-1, takes sign of first operand1, takes sign of first operand

Verilog - OperatorsArithmetic Operators (cont.)I Unary operatorsIIi.e., -4 5!!!!!!!!!!!!!!!Operators ” ” and ”-” can act as unary operatorsThey indicate the sign of an operand// negative four// positive fiveNegative numbers are represented as 2’s compliment numbers !!!Use negative numbers only as type integer or real !!!Avoid the use of sss ’ base number in expressions !!!These are converted to unsigned 2’s compliment numbers !!!This yields unexpected results in simulation and synthesis !!!

Verilog - OperatorsArithmetic Operators (cont.)I The logic gate realization depends on several variablesIIIIcoding stylesynthesis tool usedsynthesis constraints (more later on this)So, when we say ” ”, is it a.IIIripple-carry adderlook-ahead-carry adder (how many bits of lookahead to be used?)carry-save adderWhen writing RTL code, keep in mind what will eventually be neededContinually thinking about structure, timing, size, power

Verilog - OperatorsArithmetic Operators (cont.)16-bit adder with loose constraints:set max delay 2 [get ports sum*]max delay 0.8ns, area 472 85 gates

Verilog - OperatorsArithmetic Operators (cont.)16-bit adder with tighter constraints:set max delay 0.5 [get ports sum*]max delay 0.5ns, area 2038 368gates

Verilog - OperatorsLogical OperatorsIVerilog Logical OperatorsIII//suppose(a && b)(b a)(!a)(!b)logical-and(&&) //binary operatorlogical-or( ) //binary operatorlogical-not(!) //unary operatorthat: a 3//evaluates//evaluates//evaluates//evaluatesand b 0, then.to zeroto oneto 0to 1//with unknowns: a 2’b0x; b 2’b10;(a && b) // evaluates to x//with expressions.(a 2) && (b 3) //evaluates to 1 only if both comparisons are true

Verilog - OperatorsLogical Operators (.cont)I Logical operators evaluate to a 1 bit valueI0 (false), 1 (true), or x (ambiguous)IOperands not equal to zero are equivalent to oneILogical operators take variables or expressions as operators

Verilog - OperatorsRelational Operators (.cont)Igreater-than ( )Iless-than ( )Igreater-than-or-equal-to ( )Iless-than-or-equal-to ( )Relational operators return logical 1 if expression is true, 0 if false//let a 4, b 3, and.//x 4’b1010, y 4’b1101, za b //evaluates to logicala b //evaluates to logicaly x //evaluates to logicaly z //evaluates to x 4’b1xxxzeroone1!!! Note: These are expensive and slow operators at gate level !!!

Verilog - OperatorsEquality Operators - ”LT” is big and slow//8-bit less than detector//if a is less than b, output is logic onemodule less8(input [7:0] a,b,outputz);assign z (a b) ? 1’b1 : 1’b0;endmoduleResults from synthesis:.U20.U10U13U12.U14.U4U8U7U6U9.U5U3

Verilog - OperatorsEquality OperatorsIlogical equality ( )Ilogical inequality (! )Ilogical case equality ( )Ilogical case inequality (! )Equality operators return logical 1 if expression is true, else 0Operands are compared bit by bitZero filling is done if operands are of unequal length (Warning!)Logical case inequality allows for checking of x and z valuesChecking for X and Z is most definitely non-synthesible!

Verilog - OperatorsEquality Operators (cont.)//let a 4, b 3, and.//x 4’b1010, y 4’b1101,//z 4’b1xxz, m 4’b1xxz, n 4’b1xxxa x ! x z z m ! ogicallogicallogical01101

Verilog - OperatorsBitwise OperatorsI negation ( ), and(&), or( ), xor( ), xnor( - , - )I Perform bit-by-bit operation on two operands (except )I Mismatched length operands are zero extendedI x and z treated the samebitwise AND0 1 x0 0 0 01 0 1 xx 0 x xbitwise OR0 1 x0 0 1 x1 1 1 1x x 1 xbitwise negation01xresult10xbitwise XOR0 1 x0 0 1 x1 1 0 xx x x xbitwise XNOR0 1 x0 1 0 x1 0 1 xx x x x

Verilog - OperatorsBitwise Operators (cont.)ILogical operators result in logical 1, 0 or xIBitwise operators results in a bit-by-bit value//let x 4’b1010, y 4’b0000x y//bitwise OR, result is 4’b1010x y //logical OR, result is 1

Verilog - OperatorsBitwise operators give bit-by-bit 3]//8-bit wide ANDmodule and8(input [7:0] a,b,output [7:0] z);assign z a & [7]a[7:0]a[7:0]z[7:0]

Verilog - OperatorsReduction OperatorsI and(&), nand( &), or( ), nor( ) xor( ), xnor( , )IOperates on only one operandIPerforms a bitwise operation on all bits of the operandIReturns a 1-bit resultIWorks from right to left, bit by bit//let x 4’b1010&x //equivalent to 1 & 0 & 1 & 0. Results in 1’b0 x //equivalent to 1 0 1 0. Results in 1’b1 x //equivalent to 1 0 1 0. Results in 1’b0A good example of the XOR operator is generation of parity

Verilog - OperatorsReduction Operatorsd in[3]U10d in[2]//8-bit parity generator//output is one if odd # of onesmodule parity8(input [7:0] d in,outputparity out);assign parity out d in;endmoduled in[5]n5d in[7:0]d in[4]U8n6U6parity outparity outn8n7d in[7]U9d in[7:0]d in[6]d in[1]U7d in[0]

Verilog - OperatorsShift OperatorsIright shift ( )Ileft shift ( )Iarithmetic right shift ( )Iarithmetic left shift ( )IShift operator shifts a vector operand left or right by a specifiednumber of bits, filling vacant bit positions with zeros.IShifts do not wrap around.IArithmetic shift uses context to determine the fill bits.// let xy x y x y x 4’b11001; // y is 4’b01101; // y is 4’b10002; // y is 4’b0000

Verilog - OperatorsArithmetic Shift OperatorsI arithmetic right shift ( )IIShift right specified number of bits, fill with value of sign bit ifexpression is signed, othewise fill with zero.arithmetic left shift ( )IShift left specified number of bits, filling with zero.

Verilog - OperatorsConcatenation Operator {,}IProvides a way to append busses or wires to make bussesIThe operands must be sizedIExpressed as operands in braces separated by commas//let ay {b,y {a,y {a, 1’b1, b 2’b00, c 2’b10, d 3’b110c} // y is then 4’b0010b, c, d, 3’b001} // y is then 11’b10010110001b[0], c[1]} // y is then 3’b101

Verilog - OperatorsReplication Operator { { } }IRepetitive concatenation of the same numberIOperands are number of repetitions, and the bus or wire//lety {y {y {a 1’b1, b 2’b00, c 2’b10, d 3’b1104{a} }// y 4’b11114{a}, 2{b} }// y 8’b111100004{a}, 2{b}, c } // y 8’b1111000010

Verilog - OperatorsConditional Operator ?:I Operates like the C statementIIconditional expression ? true expression : false expression ;The conditional expression is first evaluatedIIIIf the result is true, true expression is evaluatedIf the result is false, false expression is evaluatedIf the result is x:IIIIboth true and false expressions are evaluated,.their results compared bit by bit,.returns a value of x if bits differ, OR.the value of the bits if they are the same.This is an ideal way to model a multiplexer or tri-state buffer.

Verilog - OperatorsConditional Operator (cont.)d in0[6]U11d out[6]d in1[6]d in0[7:0]d in0[5]U12d in1[5]d in1[7:0]d in0[4]U13d in1[4]//8-bit wide, 2:1 muxmodule mux2 1 8wide(input sel,input [7:0] d in1, d in0,output [7:0] d out);assign d out sel ? d in1 : d in0;endmoduled out[4]U14d in0[3]d in1[3]d in0[2]U15d out[2]d in1[2]d in0[1]U16d in1[1]d in0[0]U17d out[0]U10d out[7]d in1[0]d out[7:0]d in0[7]d in0[7:0]d in1[7]d in1[7:0]selseld out[7:0]

Verilog - OperatorsConditional Operator (cont.)n16d in[6]d in[5]d in[4]//8-bit wide,//active-low enabled tri-state buffermodule ts buff8(input [7:0] d in,inputen n,output [7:0] d out);assign d out en n ? d in : 8’bz;endmoduled in[3]d in[2]d in[1]d in[0]d out tri[5]d out tri[4]d out tri[3]d out tri[2]d out tri[1]d out tri[0]d out[6]d out[5]d out[4]d out[3]d out[2]d out[1]d out[0]d out[7:0]d in[7:0]en nen nd out tri[6]U2d out tri[7]d out[7]d out[7:0]d in[7]d in[7:0]

Verilog - OperatorsMore Lexical ConventionsIThe ”assign” statement places a value (a binding) on a wireIAlso known as a continuous assignIA simple way to build combinatorial logicIConfusing for complex functionsIMust be used outside a procedural statement (always)//two input mux, output is z, inputs in1, in2, selassign z (a b);assign a in1 & sel;assign b in2 & sel;

Verilog - OperatorsSome More Lexical ConventionsIThe order of execution of the assign statements is unknownIWe must fake parallel execution. gates operate in parallelIThe assign statements ”fire” when the RHS variables changeIRHS a, b, in1, in2, selIThe values of a, b, and z are updated at the end of the timestepIIn the next time step if variables changed the next result is postedIThis repeats until no further changes occurIThen. time advances//two input mux, output is z, inputs in1, in2, selassign z (a b);assign a in1 & sel;assign b in2 & sel;

Modulus operator yields the remainder from division of two numbers It works like the modulus operator in C Modulus is synthesible 3 % 2; //evaluates to 1 . I Operands not equal to zero are equivalent to one I Logical operators take variables or expressions as operators. Verilog - Operators Relational Operators (.cont) I greater-than ( )