CAN FD V1 - Xilinx
CAN FD v1.0LogiCORE IP Product GuideVivado Design SuitePG223 October 5, 2016
Table of ContentsIP FactsChapter 1: OverviewCore Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Chapter 2: Product SpecificationStandards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Chapter 3: Designing with the CoreOperating Modes and States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5762707071Chapter 4: Design Flow StepsCustomizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73767777Chapter 5: Example DesignOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79CAN FD v1.0PG223 October 5, 2016www.xilinx.comSend Feedback2
Chapter 6: Test BenchAppendix A: Verification, Compliance, and InteroperabilityCompliance Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Appendix B: Migrating and UpgradingMigrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Appendix C: DebuggingFinding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84868687Appendix D: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CAN FD v1.0PG223 October 5, 2016www.xilinx.comSend Feedback898990903
IP FactsIntroductionThe Xilinx LogiCORE IP CAN with FlexibleData-Rate (CAN FD) core is ideally suited forautomotive and industrial applications such asautomotive body control units, automotive testequipment, instrument clusters, sensorcontrols, and industrial networks. The core canbe used in stand-alone mode or connected toXilinx MicroBlaze processors or the ARM Cortex-A9 processors in Zynq -7000 AllProgrammable SoC.IMPORTANT: It is required to have a valid Bosch CANFD protocol license before selling a device containingthe Xilinx CAN FD IP core.LogiCORE IP Facts TableCore SpecificsSupportedDevice Family(1)UltraScale Families,UltraScale Architecture,Zynq -7000 All Programmable SoC, 7 SeriesSupported UserInterfacesAXI4-LiteResourcesPerformance and Resource Utilization web pageProvided with CoreDesign FilesFeaturesExample DesignVerilogTest BenchVerilog Designed to ISO 11898-1/2015 specificationConstraints File Supports both CAN and CAN FD frames Parameterized support to select between ISOCAN FD frame or non-ISO CAN FD frameformats (1)SimulationModel Supports up to 64 bytes CAN FD frames Supports flexible data rates 4 Mb/s Transmitter Delay compensation up to threedata bit TX and RX mailbox buffers with a userconfiguration depth 32-deep Sequential RX buffers (FIFO mode) with32 ID Filter-Mask pairs Message with lowest ID transmitted first Supports TX Message Cancellation Separate error logging for fast data rateEncrypted RTLXDCNot ProvidedSupportedS/W Driver (2)Standalone and LinuxTested Design Flows(3)Vivado Design SuiteDesign EntrySimulationFor supported simulators, see theXilinx Design Tools: Release Notes Guide.SynthesisVivado SynthesisSupportProvided by Xilinx at the Xilinx Support web pageNotes:1. For a complete listing of supported devices, see the Vivado IPcatalog.2. Standalone driver details can be found in the SDK directory( install directory /SDK/ release /data/embeddedsw/doc/xilinx drivers.htm). Linux OS and driver support informationis available from theXilinx Wiki page.3. For the supported versions of the tools, see theXilinx Design Tools: Release Notes Guide .1. CAN FD frame format specified in ISO 11898:2015 specification [Ref 1] is called ISO CAN FD frame format. CAN FD frame formatspecified in Bosch CAN FD specification [Ref 2] is called non-ISO CAN FD frame format.CAN FD v1.0PG223 October 5, 2016www.xilinx.com4Product SpecificationSend Feedback
IP FactsOther Features Timestamp for transmitted and received messages Supports the following: Disable Auto-retransmission (DAR) mode Snoop (Bus Monitoring) mode Sleep mode with Wake-up interrupt Internal Loopback modeCAN FD v1.0PG223 October 5, 2016www.xilinx.comSend Feedback5
Chapter 1OverviewThis product guide describes features of the Xilinx LogiCORE IP CAN FD core and thefunctionality of the various registers in the design. In addition, the core interface and itscustomization options are defined in this document.Information on the CAN or CAN FD protocol is outside the scope of this document, andknowledge of the relevant CAN and CAN FD specifications is assumed.Figure 1-1 illustrates the high-level architecture of the CAN FD core and provides theinterface connectivity.X-Ref Target - Figure 1-1;LOLQ[ & 1)' &RUH2EMHFW /D\HU //&7UDQVIHU /D\HU 0 &7%007; %ORFN 5 0 ;, /LWH, )5HJLVWHU 0RGXOH&'&6\QF& 1 )' 3URWRFRO (QJLQH3 5;& 1 %XV ;, /LWH %XV RVW&RQWURO7;5%005; %ORFN 5 0 ;, &ORFN 'RPDLQ& 1 &ORFN 'RPDLQ; Figure 1-1:CAN FD Core Layered Architecture and ConnectivityNote: The core requires an external PHY to be connected to communicate on the CAN bus.CAN FD v1.0PG223 October 5, 2016www.xilinx.comSend Feedback6
Chapter 1:OverviewCore DescriptionThe core functions are divided into two independent layers as shown in Figure 1-1. Objectlayer interfaces with the Host Control through the AXI4-Lite interface and works in the AXI4clock domain. The Transfer Layer interfaces with the external PHY and operates in the CANclock domain. Information exchanges between the two layers is done through the CDCsynchronizers. The CAN FD object layer provides a state-of-the-art transmission andreception method to manage message buffers.Object Layer (Logical Link Layer)The object layer is divided into the following submodules: Register Module – This module allows for read and write access to the registersthrough the external Host interface. TX Buffer Management Module – TX Buffer Management Module (TBMM) interfaceswith the CAN FD protocol engine to provide the next buffer to transmit on the CANbus. It manages the Host access to the TX block RAM. RX Buffer Management Module – RX Buffer Management Module (RBMM) interfaceswith the CAN FD protocol engine to provide storage for message reception from theCAN bus. It manages the Host access to the RX block RAM.Transfer Layer (Medium Access Control Layer)Transfer layer provides the following main functions: Initiation of the transmission process after recognizing bus idle (compliance withinter-frame space). Serialization of the frame Bit stuffing Arbitration and passing into receive mode in case of loss of arbitration ACK check Presentation of a serial bitstream to PHY for transmission CRC sequence calculation including stuff bit count for FD frames Bit rate switchingReception of a serial bitstream from the PHY. Deserialization and recompiling of the frame structure Bit de-stuffingCAN FD v1.0PG223 October 5, 2016www.xilinx.comSend Feedback7
Chapter 1: Transmission of ACK Bit rate switching Bit timing functions. Error detection and signaling. Recognition of an overload condition and reaction.OverviewLicensing and Ordering InformationIMPORTANT: It is required to have a valid Bosch CAN FD protocol license before selling a devicecontaining the Xilinx CAN FD IP core.License CheckersIf the IP requires a license key, the key must be verified. The Vivado design tools haveseveral license checkpoints for gating licensed IP through the flow. If the license checksucceeds, the IP can continue generation. Otherwise, generation halts with error. Licensecheckpoints are enforced by the following tools: Vivado synthesis Vivado implementation write bitstream (Tcl command)IMPORTANT: IP license level is ignored at checkpoints. The test confirms a valid license exists. It doesnot check IP license level.License TypeThe core is provided under the terms of the CAN FD LogiCORE IP License Agreement forAutomotive or Non-Automotive applications. Click here for more information aboutobtaining a CAN FD license.For more information, visit the CAN FD product web page.Information about other Xilinx LogiCORE IP modules is available at the Xilinx IntellectualProperty page. For information on pricing and availability of other Xilinx LogiCORE IPmodules and tools, contact your local Xilinx sales representative.CAN FD v1.0PG223 October 5, 2016www.xilinx.comSend Feedback8
Chapter 2Product SpecificationStandardsThe CAN FD core conforms to the ISO-11898-1/2015 standard specification.PerformanceFor full details about performance and resource utilization, visit the Performance andResource Utilization web page.Resource UtilizationFor full details about performance and resource utilization, visit the Performance andResource Utilization web page.Port DescriptionsThe Host interface of the CAN FD core is the AXI4-Lite Interface. Table 2-1 defines the coreinterface signaling.Table 2-1:CAN FD Core I/O SignalsSignal NameInterfaceTypeDefaultDescriptionAXI4-Lite Interface Signalss axi * (1)S AXI LITE––See the Vivado AXI Reference Guide (UG1037)[Ref 6] for the description of the AXI4 signals.Clock, Interrupt and PHY Signalsip2bus intreventInterruptcan clkClockCAN FD v1.0PG223 October 5, 2016O0x0I–Active-High interrupt line. (2)(3)CAN Clock input. Oscillator frequency toleranceas per the standard specification.www.xilinx.comSend Feedback9
Chapter 2:Table 2-1:Product SpecificationCAN FD Core I/O Signals (Cont’d)Signal NameInterfaceTypeDefaultDescriptioncan phy txPHYO1CAN bus transmit signal to PHY.can phy rxPHYI–CAN bus receive signal from PHY.Notes:1. The core does not support wstrb signal on the AXI4-Lite interface.2. The interrupt line is level sensitive. Interrupts are indicated by the transition of the interrupt line logic from 0 to 1.3. The AXI4-Lite interface signals and ip2bus intrevent are synchronous to s axi aclk clock.Register SpaceThe CAN FD core requires 8 KB memory mapped space to be allocated in system memory.Division of this addressable space within the core is shown in Table 2-2.Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (* wdata) signal,and is not impacted by the AXI Write Data Strobe (* wstrb) signal. For write access, both the AXIWrite Address Valid (* awvalid) and AXI Write Data Valid (* wvalid) signals should be assertedtogether.Table 2-2:CAN FD Address Space DivisionStart Address End AddressSectionNotes0x00000x00FFCore Registers SpaceThis space is implemented with flip-flops. SeeTable 2-3 and Table 2-4.0x01000x0FFFTX Message SpaceThis space is implemented with TX block RAM andprovides storage for a maximum 32 TX buffers. SeeTable 2-28.RX Message SpaceThis space is implemented with RX block RAM.For RX Sequential buffer mode (FIFO mode), itprovides storage for 32-deep message FIFO and 32ID Filter-Mask pairs. See Table 2-32.For RX Mailbox buffer mode, it provides storage formaximum 48 RX Buffers and respective ID Masks.See Table 2-38.0x10000x1FFFCAN FD v1.0PG223 October 5, 2016www.xilinx.comSend Feedback10
Chapter 2:Table 2-3:Product SpecificationCAN FD Core Register Address MapStartAddressNameAccessDescription0x0000SRRRead, WriteSoftware Reset Register0x0004MSRRead, WriteMode Select Register0x0008BRPRRead, WriteArbitration Phase Baud Rate PrescalerRegister0x000CBTRRead, WriteArbitration Phase Bit Register0x0010ECRReadError Counter Register0x0014ESRRead, Write1 to clearError Status Register0x0018SRReadStatus Register0x001CISRReadInterrupt Status Register0x0020IERRead, WriteInterrupt Enable Register0x0024ICRWriteInterrupt Clear Register0x0028TSRRead, WriteTimestamp Register0x002C0x0084Reserved–Reserved space. Write has no effect. Readalways returns 0.0x0088DP BRPRRead, WriteData Phase Baud Rate Prescaler Register0x008CDP BTRRead, WriteData Phase Bit Timing Register0x0090TRRRead, WriteTX Buffer Ready Request Register0x0094IETRSRead, WriteInterrupt Enable TX Buffer Ready RequestServed/Cleared Register0x0098TCRRead, WriteTX Buffer Cancel Request Register0x009CIETCSRead, WriteInterrupt Enable TX Buffer CancellationRequest Served/Cleared Register0x00A00x00ACReserved–Reserved space. Write has no effect. Readalways returns 0.0x00B0RCS0Read, WriteRX Buffer Control Status Register 00x00B4RCS1Read, Write0x00B8RCS2Read, Write0x00BCReserved–Reserved space. Write has no effect. Readalways returns 00x00C0IERBF0Read, WriteInterrupt Enable RX Buffer Full Register 00x00C4IEBRF1Read, WriteInterrupt Enable RX Buffer Full Register 10x00C80x00DCReserved–Reserved space. Write has no effect. Readalways returns 0.CAN FD v1.0PG223 October 5, 2016NotesRegisters present inboth RX Mailbox and RXSequential/FIFO buffermode.See RX Buffer Control Status Register 0www.xilinx.comRegisters present onlyin RX Mailbox buffermode otherwisereserved.Send Feedback11
Chapter 2:Table 2-3:Product SpecificationCAN FD Core Register Address Map 00E0AFRRead, WriteAcceptance Filter (Control) Register0x00E4Reserved–Reserved space. Write has no effect. Readalways returns 0.0x00E8FSRRead, WriteRX FIFO Status Register0x00ECWMRRead, WriteRX FIFO Watermark Register0x00F00x00FFReserved–Reserved space. Write has no effect. Readalways returns 0.Registers present onlyin RX Sequential/FIFObuffer mode otherwisereserved.Core Register DescriptionsTable 2-4 shows the CAN FD core register space. The thick ruling represents the RX Mailboxspecific register bits and the gray means RX FIFO specific register bits.CAN FD v1.0PG223 October 5, 2016www.xilinx.com10Name(ResetValue)SRSTSRR 0x0)TS1[5:0]BTR (0x0)CRCERCONFIGARBLSTISR (0x0)EARBLSTIER (0x0)FMERSTERLBACKSLEEPSR (0x1)TXOKPEEBERRNORMALESR SVDRXFOFLWRSVDERXOFLWECR (0x0)ERXOKF CRCERESTAT [1:0]RSVDERRORF FMERPEE CONFIGRSVDRSVDF STERBSFR CONFIGSLPBSOFFEBSOFFESLPRSVDRXLRM BI [5:0]F BERR0x0020RXBOFLW I SRSVDETXCRS0x000C7BRP 4RXMNFRSVDERXMNF0x00008ABRStart31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9AddressCENCAN FD Core Register SpaceEERRORTable 2-4:Send Feedback12
0x00C0CAN FD v1.0PG223 October 5, ECRS16ECRS15ECRS14ECRS13ECRS12ECRS11ECRS10Send FeedbackRR0ERRS0RR1RR2TRR (0x0)IETRS(0x0)CR0ERRS1ERRS20CARBLSTICR (0x0)CTSCPEE1CTXOKRSVDTCR CRS4CR5CR66RSVDCERROR7ECRS5ECRS6DP TS2[2:0]RR7RR8TDCOFF SCRXBFLCRXBOFLW8CR7CR8TDC ENCRXMNFStartAddress 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RRS26CR26ECRS26DP SB29RCS1(0x0)CSB450x0090ECRS31TIMESTAMP ERBF26ERBF27ERBF28ERBF290x00B0CSB47Table 2-4:ERBF300x00BCERBF31Chapter 2:Product SpecificationCAN FD Core Register Space (Cont’d)TSR (0x0)DP BRP [7:0]DP TS1[3:0]RSVDName(ResetValue)ReservedDP BRPR(0x0)DP eservedIERBF(0x0)13
Chapter 2:Table 2-4:Product SpecificationCAN FD Core Register Space (Cont’d)StartAddress 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0D8UAF29ReservedUAF30RSVDUAF310x00D4AFR ervedFL[5:0]RSVDRSVDIRI0x00E4RI[4:0]FSR (0x0)RXFWM[4:0]WMR(0xF)Software Reset Register (Address Offset 0x0000)Writing to the Software Reset Register (SRR) places the core in the Configuration mode. InConfiguration mode, the core drives recessive on the bus line and does not transmit orreceive messages. During power-up, CEN and SRST bits are 0 and the CONFIG bit in theStatus Register (SR) is 1. The Transfer Layer Configuration Registers can be changed onlywhen the CEN bit in the SRR is 0. Mode Select Register bits (except SLEEP and SBR) can bechanged only when CEN bit is 0.If the CEN bit is changed during core operation, Xilinx recommends resetting the core sothat operation starts over.Table 2-5:Software Reset CAN FD v1.0PG223 October 5, 2016DescriptionReservedwww.xilinx.comSend Feedback14
Chapter 2:Table 2-5:Bits1Product SpecificationSoftware Reset Register (Cont’d)NameAccess DefaultValueCENR/WDescriptionCAN EnableThe Enable bit for the core.1 core is in Loopback, Sleep, Snoop, or Normal mode depending on theLBACK, SLEEP, and SNOOP bits in the MSR0 core is in the Configuration modeNote: If the CEN bit is cleared during core operation, Xilinx recommends resetting0the core so that operations starts over.0SRSTWOResetThe software reset bit for the core.1 core is resetIf a 1 is written to this bit, all core configuration registers (including theSRR) are reset. Reads to this bit always returns 0.Note: After performing soft or hard reset, wait for 16 AXI4 clock cycles before0initiating next AXI4-Lite transaction.Mode Select Register (Address Offset 0x0004)Writing to the Mode Select Register (MSR) enables the core to enter Snoop, Sleep,Loopback, or Normal modes. In Normal mode, the core participates in normal buscommunication. If the SLEEP bit is set to 1, the core enters Sleep mode. If the LBACK bit isset to 1, the core enters Loopback mode. If the SNOOP mode is set to 1, the core entersSnoop mode and does not participate in bus communication but only receives messages.IMPORTANT: LBACK, SLEEP, and SNOOP bits should never be set to 1 at the same time. At any givenpoint, the core can either be in Loopback, Sleep, or Snoop mode. When all three bits are set to 0, thecore can enter Normal mode subject to other conditions.Table 2-6:Mode Select RegisterBitsName31:8Reserved7ABRAccess–R/WCAN FD v1.0PG223 October 5, 2016DefaultValueDescription0Reserved0Auto Bus-off Recovery Request1 auto bus-off recovery request0 no such requestIf this bit is set, node does auto bus-off recovery irrespective of SBR bitsetting in this register.This bit can be written only when CEN bit in SRR is 0.www.xilinx.comSend Feedback15
Chapter 2:Table 2-6:Bits65432Product SpecificationMode Select Register WR/WCAN FD v1.0PG223 October 5, 2016DefaultValueDescription0Start Bus-off Recovery Request1 start bus-off recovery request0 no such requestNode stays in bus-off state until SBR bit is set to 1 (provided ABR bit inthis register is not set).This bit can be written only when node is in bus-off state.This bit auto clears after node completes the bus-off recovery or leavebus-off state due to hard/soft reset or CEN deassertion.0Disable Protocol Exception Event Detection/Generation1 disable Protocol Exception Event detection/generation by CAN FDreceiver if “res” bit in CAN FD frame is detected as 1. In this case, CAN FDreceiver generates Form error.0 PEE detection/generation is enabled. If CAN FD receiver detects “res”bit as 1, it goes to Bus Integration state (PEE config) and waits for Bus Idlecondition (11 consecutive nominal recessive bits). Error counter remainsunchanged.This bit can be written only when CEN bit in SRR is 0.0Disable Auto retransmission1 disable auto retransmission on CAN bus to provide single shottransmission0 auto retransmission enabledThis bit can be written only when CEN bit in SRR is 0.0CAN FD Bit Rate Switch Disable Override1 makes core transmit CAN FD frames only in nominal bit rate (byoverriding TX Message element BRS bit setting)0 makes core transmit CAN FD frames as per BRS bit in TX MessageelementThis bit can be written only when CEN bit in SRR is 0.0SNOOP Mode Select/RequestThe Snoop mode request bit.1 request core to be in Snoop mode0 no such requestThis bit can be written only when CEN bit in SRR is 0.Make sure that Snoop mode is programmed only after system reset orsoftware reset.For the core to enter Snoop mode, LBACK and SLEEP bits in this registershould be set to 0.The features of Snoop mode are: Core transmits recessive bits on to CAN bus Receives messages that are transmitted by other nodes but does notACK. Stores received messages in RX block RAM based on programmedID filtering. Error counters are disabled and cleared to 0. Reads to error counterregister returns zero.www.xilinx.comSend Feedback16
Chapter 2:Table 2-6:Bits10Product SpecificationMode Select Register scription0Loopback Mode Select/RequestThe Loopback mode request bit.1 request core to be in Loopback mode0 no such requestThis bit can be written only when CEN bit in SRR is 0.For the core to enter Loopback mode, SLEEP and SNOOP bits in thisregister should be set to 0.0Sleep Mode Select/RequestThe Sleep mode request bit.1 request core to be in Sleep mode0 no such requestThis bit is cleared when the core wakes up from the Sleep mode.For core to enter Sleep mode, LBACK and SNOOP bits in this registershould be set to 0.Arbitration Phase (Nominal) Baud Rate Prescaler Register (Address Offset 0x0008)The CAN clock for the core is divided by (programmed prescaler value 1) to generate thequantum clock needed for sampling and synchronization.Table 2-7:Bits31:87:0Arbitration Phase Baud Rate Prescaler ueDescription0Reserved0Arbitration Phase (Nominal) Baud Rate PrescalerThese bits indicate the prescaler value.The actual value is one more than the value written to the register.These bits can be written only when CEN bit in SRR is 0.Arbitration Phase (Nominal) Bit Timing Register (Address Offset 0x000C)Table 2-8:Arbitration Phase Bit �R/WCAN FD v1.0PG223 October 5, on Jump WidthIndicates the Synchronization Jump Width as specified in the standardfor Nominal Bit Timing.The actual value is one more than the value written to the register.These bits can be written only when CEN bit in SRR is 0.www.xilinx.comSend Feedback17
Chapter 2:Table 2-8:Product SpecificationArbitration Phase Bit Register ueDescription0Reserved11:8TS2[3:0]R/W0Time Segment 2Indicates the Phase Segment 2 as specified in the standard for NominalBit Timing.The actual value is one more than the value written to the register.These bits can be written only when CEN bit in SRR is 0.7:6Reserved–0Reserved0Time Segment 1Indicates the Sum of Propagation Segment and Phase Segment 1 asspecified in the standard for Nominal Bit Timing.The actual value is one more than the value written to the register.These bits can be written only when CEN bit in SRR is 0.5:0TS1[5:0]R/WError Count Register (Address Offset 0x0010)The ECR is a read-only register. Writes to the ECR have no effect. The value of the errorcounters in the register reflect the values of the transmit and receive error counters in thecore.The following conditions reset the Transmit and Receive Error counters: When 1 is written to the SRST bit in the SRR. When 0 is written to the CEN bit in the SRR. When core enters Bus-Off state. During Bus-Off recovery until the core enters Error Active state (after 128 occurrencesof 11 consecutive recessive bits).IMPORTANT: When in Bus-Off recovery, the Receive Error counter is advanced/incremented by 1 whena sequence of 11 consecutive nominal recessive bits is seen.Note: In SNOOP mode, error counters are disabled and cleared to 0. Reads to Error Counter Registerreturns 0.Table 2-9:Error Counter REC[7:0]R0Receive Error CountIndicates the value of Receive Error Counter.7:0TEC[7:0]R0Transmit Error CountIndicates the value of Transmit Error Counter.BitsName31:16CAN FD v1.0PG223 October 5, 2016Descriptionwww.xilinx.comSend Feedback18
Chapter 2:Product SpecificationError Status Register (Address Offset 0x0014)The Error Status Register (ESR) indicates the type of error that has occurred on the bus. Ifmore than one error occurs, all relevant error flag bits are set in this register. The ESR is awrite 1 to clear register. Writes to this register do not set any bits, but clear the bits that areset.Table 2-10:Error Status e–0Reserved0Bit Error in CAN FD Data Phase (1)1 indicates bit error occurred in Data Phase (Fast) data rate0 indicates bit error has not occurred in Data Phase (Fast) data rateafter the last write to this bitIf this bit is set, writing a 1 clears it.0Stuff Error in CAN FD Data Phase1 indicates stuff error occurred in Data Phase (Fast) data rate0 indicates stuff error has not occurred in Data Phase (Fast) data rateafter the last write to this bit.If this bit is set, writing a 1 clears it.0Form Error in CAN FD Data Phase1 indicates form error occurred in Data Phase (Fast) data rate0 indicates form error has not occurred in Data Phase (Fast) data rateafter the last write to this bit.If this bit is set, writing a 1 clears it.0CRC Error in CAN FD Data Phase1 indicates CRC error occurred in Data Phase (Fast) data rate0 indicates CRC error ha
1. CAN FD frame format specified in ISO 11898:2015 specification [Ref 1] is called ISO CAN FD frame format. CAN FD frame format specified in Bosch CAN FD specification [Ref 2] is called non-ISO CAN FD frame format. LogiCORE IP Facts Table Core Specifics Supported Device Family(1) UltraScale Families, UltraScale Architecture,
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